PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC...

25
1 PM: Media, Attachment, and Usage Dave Eggleston, Intuitive Cognition Consulting

Transcript of PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC...

Page 1: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

1

PM: Media, Attachment, and Usage Dave Eggleston, Intuitive Cognition Consulting

Page 2: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

2

I DRAM! (But…)

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Data Source: J. Thomas Pawlowski, JTP, “Prospects for Memory”, SC’19 MCHPC

2010 2020 units Market $40B (2010) $100B (2018) $B Price -37% -8% $/year Capacity >2x <2x Gb/chip/2 years DIMM Bandwidth +31% +31% GB/sec/year Channels/CPU 2 8 (going to 16) DIMMs/Channel 4-8 2 (going to 0.5) Channels/DIMM 1 2

•  DRAM tech and price scaling has slowed way down •  Running out of tricks to keep DDR bandwidth increasing •  Can PM do (part of) the DRAM job? More than that?

Page 3: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

3 3

PM Media What, Why, and Who

3

Page 4: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

4

PM Media: What Options

Source: J. Müller, GLOBALFOUNDRIES, “Ferroelectric Memories & Beyond”, IEDM 2019 © 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Page 5: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

5

PM Media: Something New!

Source: R.Chau, Intel, “Innovations for Moore’s Law Continuum”, IEDM 2019 © 2020 SNIA Persistent Memory Summit. All Rights Reserved.

1T-1C Ferro HfOx Bitcell* 1E4 sec data retention 1E9 endurance cycles

* Verbal mention in talk

Page 6: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

6

PM Media: Why we Love/Hate each

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Page 7: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

7

PM Media: Who is Doing What

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Rumored Activity Source: Industry announcements & scuttlebutt

Page 8: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

8 8

PM Attach Options, DIMMs, Fabrics, Pooling, and Who

8

Page 9: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

9

PM Attach: Options aplenty

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Source: P. Faraboschi, HPE, “The Data Access Continuum”, SC’19 MCHPC

PM

Page 10: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

10

PM Attach: DIMMs getting complicated

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Source: D. Rhoden, Montage, “Server Memory Evolution”, JEDEC Training Class Oct 2019

•  RDIMMs

•  LRDIMMs

•  UDIMMs

•  DDIMMs

•  Optane DIMMs

•  NVDIMM-N

•  NVDIMM-P

•  Etc…

Page 11: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

11

PM Attach: Think Beyond the DIMM

Memory Controller

Internal ASIC

L1

L2

LLC

Storage Controller

NVMe

Memory Controller

External

ASIC/FPGA

CXL

PCIe

DDR/ NVDIMM

PM NVDIMM

DRAM

Cache Coherence DRAM

PM

NVDIMM**

** Functionally equivalent to NVDIMM-N, not in DIMM form factor

NAND

MRAM CPU

2019

Processor

OMI DDIMM

2021

•  Today memory is direct-attached to the CPU •  New emerging interfaces will add high-speed differential CPU-attach options •  Systems will be aware of what type of memory or storage is available and how it is connected •  Lots of new types of memory, persistent memory and storage products are possible!

Source: A. Sainio, SMART, “PM Benefits AI/ML”, IMC Summit 2019

Cache Coherence

Page 12: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

12

PM Attach: Think Pooling and Fabrics

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Source: P. Faraboschi, HPE, “The Data Access Continuum”, SC’19 MCHPC

Page 13: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

13

PM Attach: Who is Doing What

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Rumored Activity Source: Industry announcements & scuttlebutt

NVDIMM-P DDR-T NVDIMM-N _________________ _________________ _________________

Page 14: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

14 14

PM Usage Value Prop, Tiering, Pooling, Computational Memory

14

Page 15: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

15

PM Usage: Value Propositions

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

1.  PM = More Memory

Pro: Existing applications want it

Con: Compete directly vs. DRAM on price

2.  PM = Persistent & Coherent

Pro: Take full advantage of features

Con: Application needs to know

Source: D. Eggleston, Intuitive Cognition Consulting, “Overview of PM”, FMS 2019

Page 16: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

16

PM Usage: Data Tiering

HotTier

WarmTier

ColdTier

WithDRAM

OLAP(In-MemoryProcessing)

OLTP

DRAM8-256GB

NVMeSSD1TB

SAS/SATASSD10TB

WithPersistentMemory

PersistentMemory16GB–>1TB

CollapseHot&WarmTiertoprocessorstorecriticaldata

SAS/SATASSD10TBProcesseddata

&Transactionalops

HotData WarmData ColdDataOLAP–OnlineAnalyticalProcessingOLTP–OnlineTransactionProcessing

Transactionlogs

Persistent

Coherent

Source: A. Sainio, SMART, “PM Benefits AI/ML”, IMC Summit 2019 © 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Page 17: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

17

PM Usage: Move SSD tasks into PM

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Source: A. Huffman, Intel, “Solid State Transformation of the Data Center”, SDC 2018

Persistent

Coherent

9x the Read IOPS!

Page 18: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

18

PM Usage: Move SSD tasks into PM

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Source: J. Xie, Formulus Black, “PM Delivers Superior ROI”, Webinar 2020

2.4x the transactions... @ 50% lower $ per transaction!!!

Persistent

Coherent

Page 19: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

19

PM Future: “Pooled Memory Appliance”

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Source: J. Thomas Pawlowski, JTP, “Prospects for Memory”, SC’19 MCHPC

Page 20: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

20

PM Future: “Pooled Memory Appliance”

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Source: P. Faraboschi, HPE, “The Data Access Continuum”, SC’19 MCHPC

Persistent

Coherent

Page 21: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

21

PM Future: “Computational Memory”

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Persistent

Coherent

A new initiative?

Source: S. Bates, Eideticom, “Successfully Deploying PM and Acceleration”, PIRL 2019

Page 22: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

22 22

Conclusions 4 Things I think I think

22

Page 23: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

23

1.  I DRAM! (But…) •  Watch: Tech and Price scaling stall gets worse

2.  3DXP/PCM still the top PM Media for the job •  Watch: Ferro HfOx 1T-1C research advances

3.  DIMM slots too precious for PM •  Watch: CXL becomes primary PM attachment; big bandwidth increase

4.  Best PM usage values Persistence and Coherence •  Watch: Pooled Memory Appliances and “Computational Memory”

4 Things I Think I Think

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.

Page 24: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

24 24

Thank you Please visit www.snia.org/pmsummit for presentations

24

Dave Eggleston Intuitive Cognition Consulting Technology & Business Strategy Email: [email protected] Twitter: @NVM_DaveE LinkedIn: linkedin.com/in/deggleston/

Page 25: PM: Media, Attachment, and Usage...PM Attach: Think Beyond the DIMM Memory Controller Internal ASIC L1 L2 LLC Storage Controller NVMe Memory Controller Externa l ASIC/FPGA CXL PCIe

25

Abstract The commercialization of Persistent Memory is well underway, fundamentally changing the way processors load and store information. The characteristics of the non-volatile memory media (3DXP, PCM, MRAM, RRAM, others) determine the basic performance, reliability, and cost that Persistent Memory can deliver to the system. Brand new methods of processor attachment (DDR5, DDR-T, NVDIMM, CXL, CCIX, Gen-Z, OpenCAPI) for Persistent Memory promise to broaden its usage far beyond “DRAM replacement”, opening up vast resources enabling memory and power hungry applications.

In this talk, the speaker will:

•  Discuss the basic characteristics of Persistent Memory Media

•  Articulate how Persistent Memory enhances server architectures

•  Identify, compare, contrast the new methods for Persistent Memory attachment

•  Propose innovative ways applications will utilize Persistent Memory to overcome memory and power limitations

•  Discuss who is doing what within the Persistent Memory ecosystem

© 2020 SNIA Persistent Memory Summit. All Rights Reserved.


PrimeCell Dynamic Memory Controller (PL340) Technical ...infocenter.arm.com/help/topic/com.arm.doc.ddi0331f/... · PrimeCell Dynamic Memory Controller (PL340) Technical Reference

PrimeCell Dynamic Memory Controller (PL340) Technical ...infocenter.arm.com/help/topic/com.arm.doc.ddi0331f/... · PrimeCell Dynamic Memory Controller (PL340) Technical Reference

Hyperstone S6 Flash Memory Controller Specification

Hyperstone S6 Flash Memory Controller Specification

Memory Controller Interface

Memory Controller Interface

CS 150 - Spring 2007 – Lec #10: Memory Controller - 1 SDRAM Memory Controller zStatic RAM Technology y6T Memory Cell yMemory Access Timing zDynamic RAM.

CS 150 - Spring 2007 – Lec #10: Memory Controller - 1 SDRAM Memory Controller zStatic RAM Technology y6T Memory Cell yMemory Access Timing zDynamic RAM.

Spartan-6 FPGA Memory Controller

Spartan-6 FPGA Memory Controller

7 Memory and ProgrammableLogicProgrammable …robotics.chonbuk.ac.kr/Courses/2012Spring_DigitalLogic...2011-05-26 ASIC LAB. 3 1024x16 Memory1024x16 Memory The1K*16memoryhas10bitsThe

7 Memory and ProgrammableLogicProgrammable …robotics.chonbuk.ac.kr/Courses/2012Spring_DigitalLogic...2011-05-26 ASIC LAB. 3 1024x16 Memory1024x16 Memory The1K*16memoryhas10bitsThe

Synergetic Combination of ASIC & Memory · SYNCOAM Co., Ltd SEPS525 160 RGB x 128 Dots, 262K Colors PM-OLED Display Driver and Controller 1/46 Synergetic Combination of ASIC & Memory

Synergetic Combination of ASIC & Memory · SYNCOAM Co., Ltd SEPS525 160 RGB x 128 Dots, 262K Colors PM-OLED Display Driver and Controller 1/46 Synergetic Combination of ASIC & Memory

ASIC IMPLEMENTATION OF I2C MASTER BUS CONTROLLER FIRM IP CORE

ASIC IMPLEMENTATION OF I2C MASTER BUS CONTROLLER FIRM IP CORE

Introduction to Design Considerations of DRAM Memory Controllers · 2017. 2. 15. · 5 . 5 . Host (CPU), Memory Controller and Memory Memory Controller is a widget that supports specific

Introduction to Design Considerations of DRAM Memory Controllers · 2017. 2. 15. · 5 . 5 . Host (CPU), Memory Controller and Memory Memory Controller is a widget that supports specific

Z80 Direct Memory Access Controller Specifications

Z80 Direct Memory Access Controller Specifications

ControlLogix Controller and Memory Board

ControlLogix Controller and Memory Board

The Memory Controller

The Memory Controller

32-Bit Memory System design: Design of Memory Controller ...eprints.utar.edu.my/1543/1/Documention.pdf · 32-Bit Memory System design: Design of Memory Controller for Micron SDR SDRAM

32-Bit Memory System design: Design of Memory Controller ...eprints.utar.edu.my/1543/1/Documention.pdf · 32-Bit Memory System design: Design of Memory Controller for Micron SDR SDRAM

Complete DDR Memory Power Supply Controller

Complete DDR Memory Power Supply Controller

A Memory Controller for FPGA Applications

A Memory Controller for FPGA Applications

Keystone Architecture DDR3 Memory Controller (Rev. E) · PDF fileKeystone Architecture DDR3 Memory Controller User's Guide ... 2.6 DDR3 Memory Controller Interface ... 4.23 DDR PHY

Keystone Architecture DDR3 Memory Controller (Rev. E) · PDF fileKeystone Architecture DDR3 Memory Controller User's Guide ... 2.6 DDR3 Memory Controller Interface ... 4.23 DDR PHY

Requirements for the NSW VMM3 readout ASIC and the NSW Readout Controller ASIC NSW Readout Working Group NSW Electronics Design Reviews, February 2015.

Requirements for the NSW VMM3 readout ASIC and the NSW Readout Controller ASIC NSW Readout Working Group NSW Electronics Design Reviews, February 2015.

SDRAM Memory Controller

SDRAM Memory Controller

External Memory Controller (EMC)

External Memory Controller (EMC)

Efficient Memory Controller Architectures and their ...

Efficient Memory Controller Architectures and their ...