PLL Frequency Synthesizers, Phase Noise and Wide Band

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No d’ordre: 99 ISAL 086 Année 1999

THESE

présentée

DEVANT L’INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON

pour obtenir

LE GRADE DE DOCTEUR

FORMATION DOCTORALE: Dispositifs de l’électronique intégréeECOLE DOCTORALE: Electronique, Electrotechnique, Automatique (EEA)

par

Marina, de Queiroz Tavares

SYNTHETISEUR DE FREQUENCE A BOUCLE DE VERROUILLAGE DE PHASE:

ETUDE DU BRUIT DE PHASE ET DE BOUCLES A LARGE BANDE

Soutenue le 09/Décembre/1999 devant la Commission d’Examen

Jury

Richard-GRISEL Professeur - Université Picardie rapporteurMichiel-STEYAERT Professeur - K.U. Leuven rapporteurJean-Pierre-CHANTE Professeur - INSA de Lyon directeurBruno-ALLARD Maître de Conférences - INSA de Lyon examinateurPhilippe-KLAEYLE Ingénieur - Philips Semiconductors - Caen examinateurEduard-Stikvoort Chercheur - ingénieur – Philips Nat.Lab. – Eindhoven examinateur

Cette thèse a été préparée chez Philips Semiconductors – Caen, en collaboration avec leLaboratoire CEGELY de l’INSA de Lyon

Title: PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Keywords: frontend/ tuners / PLL / phase noise / stability / gm-C oscillators

Abstract:

PLL frequency synthesizers are widely used in telecommunication receivers and transmitters, aspart of the frequency conversion block. They consist of a tunable oscillator and a programmablephase controlling loop.Current tendencies in PLL development focus noise performance and a higher integration level.The first is connected to the new digital modulation techniques, often demanding a higher CNRin the signal chain. And the second concerns a global trend towards smaller and more compactsystems.

This thesis discusses and develops PLL system models to study stability and noise aspects. Themodel results are employed in IC and application design, being confirmed via measurements.The stability approach investigates the robustness of the PLL system, typically working withvery large gain variations. A top-down system to circuit approach, studies noise generation andtransmission. Finally testchip realizations of PLLs with fully gm-C integrated oscillators arepresented.

The thesis was conducted within the context of a collaboration between the CEGELY-INSA deLyon and Philips Semiconductors, more specifically in the production and development centre ofCaen.

PhD student:Marina de Queiroz Tavares

Advisor:Prof. Jean-Pierre ChanteDirector of the CEGELY laboratory

ii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Contents:

Index iiList of figures vList of Tables viiiList of symbols and abbreviations ixPreface xiv

1. Introduction 1

1.1. The frontend in a telecommunication receiver 2 1.2. The frontend in TV broadcasting 3 1.3. Current tendencies: low noise and higher integration 9 1.4. PLL systems : different application contexts 14 1.5. PLL frequency synthesizers constituting blocks and nomenclature 15 1.5.1. VCO 16 1.5.2. Dividers 17 1.5.3. Phase Detector – Charge Pump 17 1.5.4. Loop Filter 19

2. PLL Phase Model and Loop Filter calculation 21

2.1. Phase Model for PLL synthesizers 22 2.1.1. Requirements in the Time and Frequency Domain 24 2.1.2. Second-Order Loop 26 2.1.3. Third and Fourth Order Loop 28 2.2. Algorithm for Loop Filter Calculation 34 2.2.1. Nominal Design 34 2.2.2. Robust design including Gain Variation and 3rd Pole compensation 36 2.2.3. Summary steps and numerical example 40

3. Application Related Constraints 43 3.1. Reference Breakthrough 44 3.2. VCO Noise Representation and Phase Noise Units 46 3.3. Optimum Closed Loop Bandwidth 50 3.4. PLL Closed Loop Bandwidth 52 3.4.1. w3dB derivation from BRL(s) 53 3.4.2. w3dB derivation from was 59 3.5. Maximum Phase Jitter 61 3.6. Gain Stability Boundary 65

Contents iii

4. Active Loop Filters: AC & disturbances issues 69 4.1. Non-ideal Filter Impedances 70 4.1.1. Fully 3rd order passive filter 71 4.1.2. Amplifier AC characteristics 72 4.1.3. Amplifier with single pole 74 4.1.4. Numerical example 76 4.1.5. Input impedance: Zin 79 4.1.6. Summary of AC boundaries for filter design 80 4.2. Disturbances and Noise Propagation 80 4.2.1. Random Electrical Noise 81 4.2.2. Supply Disturbances 82 4.2.3. Amplifier Noise 82 4.2.4. Filter Components Noise 83 4.2.5. Transfer functions table 84 4.2.6. Simulation Example 85

5. Limitations of the LTI Phase Model 89 5.1. Three-state comparator: frequency and phase detector 91 5.1.1. Minimum phase deviation range 92 5.2. DC range limitations 94 5.2.1. Loop filter time domain response 94 5.2.2. Numerical examples and design considerations 96 5.3. Lock convergency approaches 99 5.3.1. Frequency approach 100 5.3.2. Phase approach 103 5.3.3. Comparing the frequency and phase approaches: 105 5.4. Discrete trasfers for the PLL Phase Model 109 5.4.1. The sampler 109 5.4.2. The holder 111 5.4.3. Continuous equivalent with transmission delay 114

6. Phase Noise: theoretical to practical approach 119 6.1. Electrical Noise: random sources representation & measurements 120 6.1.1. Electrical noise as a random process 121 6.1.2. Measuring Phase Noise 123 6.2. Phase Noise Notations 125 6.2.1. Interchanging Modulation Types 125 6.2.1.1. Angular modulation 127 6.2.2. Phasors Notations 128 6.2.3. Slope approach 133 6.3. Large Signal Linearization 135 6.3.1. Time and Frequency representation 135 6.3.2. Linear Time Variable transfer 136

iv PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

7. Phase Noise in the PLL context 141 7.1. Translating the SNF into phase, time, voltage and current noise 143 7.2. Sampling effects: SNF x fcp 147 7.2.1. Narrow bandwidth noise sources 149 7.2.2. Large bandwidth noise sources 151 7.3. Detailing noise sources in different PLL blocks 154 7.3.1. D-flip flop 154 7.3.2. Charge Pump 158 7.4. Behavioural Models 159 7.4.1. Frequency domain 159 7.4.2. Time domain 160 7.5. Implementation Loss due to Phase Deviations 162 7.5.1. Signal to noise ratio and implementation loss 163 7.5.2. Digital Demodulator: clock and carrier recovery loops 167

8. Testchips Realized 169 8.1. Gm-C oscillator 170 8.1.1. Structure 171 8.1.2. Results 172 8.2. TC2 : Mixer-Oscillator-PLL circuit for satellite direct conversion 173 8.2.1. Double Loop Synthesizer 173 8.2.2. TC2 structure 175 8.2.3. TC2: results 177 8.3. TC3 : single PLL plus QCCO circuit 180 8.4. Comparative analysis: phase jitter and implementation loss 183 8.4.1. Configurations compared 183 8.4.2. Conditions for the simulations 184 8.4.3. Results and conclusions 187

9. Conclusion 191

Bibliography 193

List of Figures v

List of figures

Chapter 1 Figure 1.1 Communication transceiver: TX and RX systems 2Figure 1.2 Heterodyne Receiver _ Terrestrial TV Frontend 4Figure 1.3 DVB Satellite transmission modes 6Figure 1.4 Satellite Receiver Frontend: heterodyne and ZIF architectures 7Figure 1.6 Local Oscillator Spectral Purity X SNR 9Figure 1.7 Carrier Spectrum 10Figure 1.8 QPSK constellation + phase deviation 11Figure 1.9 Phase Noise requirements 12Figure 1.10 PLL frequency synthesizer: block diagram 16Figure 1.11 VCO and tunable resonator 16Figure 1.12 Phase Detector & Charge Pump block diagram 18Figure 1.13 Phase detector & Charge pump: transfer and state machine 19

Chapter 2 Figure 2.1 PLL linear Phase Model 23Figure 2.2 Vtune time response for a frequency step 25Figure 2.3 Locked VCO output spectrum 25Figure 2.4 3rd order Loop Filter Impedance 29Figure 2.5 4th order PLL: Open and Closed Loop Bode Plots 31Figure 2.6 4th order PLL: Root Locus diagram 31Figure 2.7 Gain Variation X Stability in Bode Plots 33Figure 2.8 The influence of r21 in the gain-bandwidth variation 36Figure 2.9 Numerical example of robust filter design 42

Chapter 3 Figure 3.1 BB noise representation of the VCO 47Figure 3.2 Free running VCO power spectrum density 49Figure 3.3 PSD of a VCO locked by a PLL 49Figure 3.4 Peaking X Optimum Closed Loop bandwidth 50Figure 3.5 Combined Spectrum: PLL + VCO noise contributions 52Figure 3.6 Rootlocus for w3dB location 58Figure 3.7 Rootlocus for was location 60Figure 3.8 Optimizing Total Phase Deviation 63Figure 3.9 Maximum SSB noise requirement 64

Chapter 4 Figure 4.1 Active Loop Filter 70Figure 4.2 Fully 3rd order passive filter impedance 72Figure 4.3 Active Filter AC model 73Figure 4.4 Loop rootlocus with active filter 75Figure 4.5 Active Filter example: Bode plots 77Figure 4.6 Active filter: input impedance 79

vi PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Figure 4.7 Supply disturbances 82Figure 4.8 Amplifier noise 83Figure 4.9 Filter components noise 83Figure 4.10 Noise simulation schematic 85Figure 4.11 Noise simualtion results 86

Chapter 5 Figure 5.1 Phase-detector & Charge Pump transfer 91Figure 5.2 Maximum Phase Detection Range & Cycle slips 92Figure 5.3 Condition for unlimited frequency tracking range 93Figure 5.4 Loop Filter: time response for current pulses 94Figure 5.5 Time response through normalized functions 96Figure 5.6 Convergence towards lock: phase deviation sequence 99Figure 5.7 Frequency approach convergence criterion 103Figure 5.8 Phase approach convergence criterion 104Figure 5.9 Comparing frequency and phase approaches 105Figure 5.10 Convergence approaches X lead-lag spacing r21 107Figure 5.11 Convergence approaches X gain variation 108Figure 5.12 Discrete model for digital blocks 110Figure 5.13 Discrete phase detector input: ∆ϕn 111Figure 5.14 Charge Pump DAC output 112Figure 5.15 Continuous equivalent with transmission delay 114Figure 5.16 Frequency and Time response for the continuous+delay model 115

Chapter 6 Figure 6.1 Spectrum Analyzer Output 124Figure 6.2 FM & PM carriers 128Figure 6.3 SSB superposed noise: AM + PM decomposition (phasor) 129Figure 6.4 Superposed Noise: AM + PM decomposition (spectrum) 130Figure 6.5 Phase modulated carrier by DSB superposed noise 131Figure 6.6 Phase deviation from DSB sidebands 132Figure 6.7 Slope approach: voltage & time deviations 133Figure 6.8 Periodic transfer determined by a large signal 136Figure 6.9 Large Signal Transfer: ideal and hyperbolic-tangent limitations 138

Chapter 7 Figure 7.1 PLL block diagram with signal+noise inputs 142Figure 7.2 Noise Transfer Slopes 143Figure 7.3 Synthesizer Noise Floor 144Figure 7.4 Sampled Loop Model 148Figure 7.5 Large bandwidth noise folding 152Figure 7.6 DFF plus superposed noise in the clock input: time domain signals 155Figure 7.7 DFF plus superposed noise in the clock input: frequency domain signals 155

List of Figures vii

Figure 7.8 Charge Pump current noise levels within one period 158Figure 7.9 Behavioural model for AC and noise simulations 160Figure 7.10 Behavioural model for transient simulations 161Figure 7.11 Digital Demodulator and Decoder 162Figure 7.12 Noise Power added by the LO sidebands 164Figure 7.13 Behavioural Model of the Carrier Recovery loop 167

Chapter 8 Figure 8.1 Gm-C integrated oscillator 171Figure 8.2 Double loop MOPLL: block diagram 174Figure 8.3 Block diagram of TC2 176Figure 8.4 Photo of a testchip TC2 177Figure 8.5 TC2 _ in-loop spectrum for N1=7 and fcp1=300Mhz 179Figure 8.6 TC2 _out-of-loop spectrum for N1=6 and fcp1=300MHz 179Figure 8.7 TC3 _ single low noise PLL plus QCCO 181Figure 8.8 Simulation result for the SSB phase noise _ linear scale 182Figure 8.9 Spectra for ∆fstep =125kHz and flo =900MHz 186Figure 8.10 Phase noise simulation for DL+QCCO with and without demodulator 186

viii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

List of tables

Chapter 1 Table 1-1 DVB standards: bandwidth and modulation types 10

Chapter 2 Table 2-1 2nd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ] 37Table 2-2 3rd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ] 38Table 2-3 3rd order filter : Open Loop Bandwidth recentering 39

Chapter 3 Table 3-1 Comparing the denominators of B(s) and BRL(s) 54Table 3-2 Rootlocus approach for wcl : parameters of BRL(s) 58Table 3-3 Gain Stability Boundary 65Table 3-4 Maximum Normalized Gain Variation 66

Chapter 4 Table 4-1 Fully 3rd order passive filter: ∆PhM and ∆GM 72Table 4-2 Active Filter example: Phase Margin degradation 78Table 4-3 Disturbances transfer functions 84Table 4-4 Noise sources voltage spectrum density 87

Chapter 6 Table 6-1 Phase Modulated Carrier 126Table 6-2 Phase Noise X CNR 132

Chapter 7 Table 7-1 Data sheet points from: TSA5059 - low noise PLL 145Table 7-2 The influence of fcp change for narrow band noise 151Table 7-3 The influence of fcp change for large band noise 153Table 7-4 Implementation Loss X Phase deviations 166

Chapter 8 Table 8-1 Measurements of the frequency coverage of the QCCO 172Table 8-2 Double Loop: minimum step and comparison frequencies. 175Table 8-3 Parameters of the two zero-IF configurations being compared 183Table 8-4 Parameters and outputs for comparative analysis 184Table 8-5 Settings of the demodulator block 185Table 8-6 Phase Jitter and implementation loss for rs=30Msps and fLO = 2,2GHz 188Table 8-7 Phase Jitter and implementation loss for rs=3Msps and ∆fstep = 125kHz 188Table 8-8 Margin for degradations in the oscillators phase noise performance 189

List of Symbols and Abbreviations ix

List of Symbols and Abbreviations

Symbols

α: gain of the open loop transfer function [A.Hz/V]αn: nominal gain value for loop filter calculation [A.Hz/V]αnpf: nominal gain value after the compensation wrt the post-filter [A.Hz/V]δϕi: phase noise density [rad/sqrt(Hz)]δii: current noise density [A/sqrt(Hz)]δti: time noise density [s/sqrt(Hz)]δvi: voltage noise density [V/sqrt(Hz)]∆ϕ: phase deviation or phase error [rad]∆ϕn(nT): phase deviation as a discrete variable [rad]∆Ψn(w): Fourier transform of ∆ϕn(nT)∆ϕp: peak value of a phase deviation [rad]∆fstep: minimum tuning step of a synthesizer [Hz]ϕdiv: phase of the main divider output [rad]ϕe: phase error at the phase detector input [rad]ϕm: phase of the single tone modulating signal vm(t) [rad]ϕn: phase of the single tone noise component vn(t) [rad]ϕosc: phase of the controlled oscillator [rad]ϕref: phase of the reference input [rad]ξ: ksi, damping factor, dimensionlessσϕ: total phase deviation [rad or °]τ: time delay [s]τrst: time delay for the reset of the phase detector [s]θn(t): phase modulating noise

Ac: amplitude of the carrier signal [V]Am: amplitude of the modulating signal [V]an(t): amplitude modulating noiseAn: amplitude of a single tone noise component, vn(t) [V]As: amplitude of the spurious sidebands wrt the carrier amplitude [dBc]B(s): closed loop transfer function ϕosc/ϕref, dimensionlessBRL(s): approximation of B(s) derived from the root locusBvco(s): closed loop transfer function ϕosc/vnvco [rad/V]Bvco-BPF(s): band-pass filter approximation for Bvco(s) [rad/V]B3LPF(s): 3rd order low-pass filter approximation for B(s)DB(s): denominator of the closed loop transfer function B(s)DG(s): denominator of the transconductance of the loop amplifierDs(s): denominator of Zs(s)F(s): loop filter transfer function in Laplace variable [Ω]fi: intersection frequency for the PLL and VCO noise asymptotes [Hz]fc: carrier frequency [Hz]fcl: bandwidth of the closed loop transfer function B(s) [Hz]

x PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

fcp: comparison frequency at the phase detector [Hz]fj , Fj: frequency of j [Hz]fm: frequency of the modulating signal [Hz]fn: frequency of a single tone noise component, vn(t) [Hz]fno: offset frequency of vn(t) wrt the carrier [Hz]foffset: frequency increment with respect to the frequency of a reference signal [Hz]fol: zero-crossing frequency for the open loop transfer function H(s) [Hz]foln, folnpf: frequencies related to woln and wolnpf [Hz]fosc: frequency of the controlled oscillator [Hz]frecover: intersection between flicker and white noise contributions of a transistor [Hz]fp2, fp3: frequencies of 2nd and 3rd poles of the loop filter [Hz]fz1: frequency of the zero of the loop filter [Hz]f3dB: 3dB attenuation frequency for the closed loop transfer function B(s) [Hz]GChP-ZOH(s): transfer function of the charge pump as a ZOH [A/rad]GChP-pw(s): transfer function of the charge pump as a holder with Tw delay [A/rad]gfrap: function expressing the maximum fcl, derived from the frequency approachgphap: function expressing the maximum fcl, derived from the phase approachgm: transconductance [Ω-1]Gmo: DC value of the transconductance of the loop amplifierGvo: DC value of the voltage gain of the loop amplifierg(x,r21): function expressing the time response of vtune , dimensionlesshPLS(t), HPLS(f): transfer function related to a periodic large signalH(s): open loop transfer function ϕdiv/ϕe, dimensionlessIaverage: average current at the output of the charge pump [A]Icp: charge pump current [A]Ileakage: leakage current at the tuning input [A]IZOH(w), iZOH(t): output of the charge pump for a ZOH approach [A]Ipw(w), ipw(t): output of the charge pump with a delay equals Tw [A]ini, Ini: current noise density from component i [A/sqrt(Hz)]Kϕ: sensitivity of the phase detector plus charge pump comparator [A/rad]Kcco: frequency sensitivity of a current-controlled oscillator [Hz/A]Ko: VCO frequency sensitivity [rad/(s.V)]Kvco: VCO frequency sensitivity [Hz/V]L(f), LdB(f): single-side band phase noise [1/Hz, dBc/Hz]Lpll(f): L(f) in the in-loop zone of a locked VCO spectrum [dBc/Hz]Lvco(f): L(f) of the free-running oscillator [dBc/Hz]nlim: aliasing factor related to the sampling of large bandwidth noise, dimensionlessN: PLL main divider ratio, dimensionlessNpll: noise of the PLL as a phase noise density [rad/sqrt(Hz)]Ns(s): numerator of Zs(s)PhM: phase margin for a open loop transfer function [°]p: normalized time deviation Td/Tcp

Q: charges [C]Vtune: tuning voltage for the VCO [V]

List of Symbols and Abbreviations xi

RJ(τ): autocorrelation function of the random process JRpu: pull-up resistor in an active loop filter [Ω]rpf: post-filter factor for the compensation of αn and woln

r21: 2nd-pole to zero ratio for loop filterr31: 3rd-pole to zero ratio for loop filterSϕ(f), SϕdB(f): mean square phase fluctuation power [rad2/Hz, dBc/Hz]SJ(f): power spectrum density of JTcp: comparison period [s]Td: delay or time interval between the two inputs of the phase detector [s]Tp2, Tp3, Tz1: time constants related to the zero and poles of the loop filter [s/rad]Vd(s), vd(t): voltage disturbance signal [V]vM(t): tuning voltage for a 2nd order filter impedance [V]vni, Vni: voltage noise density from component i [V/sqrt(Hz)]vn(t): single tone noise component [V]vnf: voltage noise density from the loop filter at the input of the VCO [V/sqrt(Hz)]vnvco: inherent noise of the VCO as a voltage noise source [V/sqrt(Hz)]w: angular frequency [rad/s]wa: pole of the loop amplifier [rad/s]was: intersection frequency for the asymptotes of the root locus [rad/s]wc: angular frequency of the carrier signal [rad/s]wcl: bandwidth of the closed loop transfer function B(s) [rad/s]wcp: angular comparison frequency [rad/s]wn: natural frequency [rad/s]wol: zero-crossing angular frequency for the open loop transfer function H(s) [rad/s]woln: nominal value of wol for loop filter calculation [rad/s]wolnpf: nominal value of wol after the compensation wrt the post-filter [rad/s]wp2, wp3, wz1: angular frequencies related to the zero and poles of the loop filter [rad/s]ws: sample angular frequency [rad/s]w3dB: angular frequency related to f3dB [rad/s]x: bandwidth ratio foln/fcp

ZF(s), Zfilter(s): impedance of the loop filter [Ω]ZFa(s): impedance of the active loop filter [Ω]ZFai(s): impedance of the active loop filter with a non-ideal input impedance [Ω]ZF3(s): full 3rd order impedance of the loop filter [Ω]Zin: input impedance [Ω]Zs(s): series version for the lead-lag filter impedance [Ω]Zo: output impedance [Ω]Zp(s): parallel version for the lead-lag filter impedance [Ω]Z3(s): post-filter impedance [Ω]Z3u(s): impedance of the post-filter in parallel to the pull-up resistor [Ω]

xii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Abbreviations

AC: alternate current, refers to small signal frequency domain models (commonly named AC models in analog simulations)ADC: analog to digital converterAGC: automatic gain controlAM: amplitude modulationBB: base bandBiCMOS: IC founding process with both BJT and CMOS devicesBPF: band-pass filterbw: bandwidthCMOS: complementary metal-oxide-semiconductorsCNR: carrier to noise ratioDAB: digital audio broadcastingDAC: digital to analog converterDBS: direct broadcast satelliteDC: direct current, refers to the quiescent state of a circuitDDS: direct digital synthesisDFF: D-type flip flopDSB: double-side bandDVB: digital video broadcastingft: frequency of unity current gain for a transistorFM: frequency modulationGm-C: transconductance and capacitor integrator for a ring oscillatorIC: integrated circuitIF: intermediate frequencyI/Q: in phase and quadrature signalsI2C: bidirectional 2-wire bus for inter-IC programming and controlLC: inductor and capacitor resonatorLHP: left hand plane in a s-space (Laplace transform)LNA: low noise amplifierLO: local oscillatorLPF: low pass filterLTI: linear time invariable systemMCPC: multi-channel per carrierMOPLL: mixer-oscillator plus phase-locked-loop circuitNPN: n-type bipolar junction transistorOFDM: orthogonal frequency division multiplexing, type of multicarrier modulationPLL: phase locked loopPM: phase modulationPMOS: P-channel metal-oxide-semiconductorPNP: p-type bipolar junction transistorPSD: power spectrum densityPWM: pulse width modulationQAM: quadrature amplitude modulation, type of digital modulationQCCO: quadrature current controlled oscillator

List of Symbols and Abbreviations xiii

QPSK: quadrature phase-shift keying, type of digital phase modulationRBW: resolution bandwidth in a spectrum analyzerRF: radio frequencyRHP: right hand plane in a s-space (Laplace transform)RX: receiver in a telecommunication systemSAW: surface acoustic wave filtersSCPC: single-channel per carrierSDD: satellite demodulator and decoderSNF: synthesizer noise floorSNR: signal to noise ratioSSB: single-side bandsqrt: square rootTC2, TC3: testchips #2 and #3TDM: time division multiplexingTR: transient analysis in analog simulationTV: televisionTX: transmitter in a telecommunication systemVHF: very high frequency, television broadcasting bandUHF: ultra high frequency, television broadcasting bandVCO: voltage controlled oscillatorV/I: voltage to current converterVSB: vestigial side band, type of modulationwrt: with respect toWSS: wide sense stationary, property of some stochastic processesXosc: crystal oscillatorZIF: zero-IF receiver, architecture of a frontendZOH: zero order holder3W: unidirectional 3-wire bus for inter-IC programming

xiv PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Preface

The central issue of this thesis is the stability and noise performance of PLL frequencysynthesizers.Frequency synthesizers are a common block of the frontend of RF telecommunication systems.In particular, PLL synthesizers are extensively used for their programming flexibility, ease ofintegration and low production cost.We focus on the context of TV broadcasting tuners, where the new standards of digitalmodulation broadcasting (DVB) which are appearing, and the continuous trend for higherintegration levels, are bringing new issues for IC design and application.Most of the thesis dissertation is concerned with models: calculations and behavioural simulationtools, which were developed to support the activities of design and engineering for the integratedcircuits in frequency synthesizers.The design of a monolithic mixer-oscillator and PLL synthesizer is also presented and used as apractical example to compare the simulations and calculation tools with measurement results.

Chapter one introduces the context of the TV tuner and the current tendencies in architectureand IC requirements. These tendencies point to low phase noise synthesizers, implemented invery monolithic architectures with integrated oscillators. The constituent blocks of the PLLsynthesizer are presented, describing their basic functionality.Chapter two studies the stability and robustness of a phase-locked loop in a tuner application,where the gain parameters vary within a large range. An algorithm for the loop filter calculationis developed. It allows a systematic and consistent approach to combine the IC parameters andthe filtering requirements.Application constraints related to phase deviations and reference breakthrough are discussed inthe light of this algorithm, in chapter three. This is the beginning of a top-down analysis aboutthe phase noise in the local oscillator (LO) signal. The noise performances of the PLL and theVCO are adjusted by centering the closed loop bandwidth of the feedback. An example of phasejitter optimization for a satellite synthesizer is discussed.Chapter four examines the active loop filter configurations and continues the noise analysis, ina first example that descends to a circuit implementation level. The AC characteristics of thefilter amplifier exemplify the first non-ideal aspects of the phase model of the PLL.In chapter five we continue to discuss other limitations of the linear time invariable model of thefrequency synthesizer. They concern the maximum feedback bandwidth for a loop that ispartially discrete, and the maximum comparison frequency that still guarantees the frequencytracking behaviour of the tri-state phase detector. A discrete time domain approach is comparedto a continuous frequency model with an equivalent delay.Chapter six presents the theoretical basis of the generation of phase noise, and discussesdifferent possibilities of notation that are compared to measurement and simulation tools. Therelationships among the different notations are explored. The assumptions of a narrow band FMmodulation and a periodic steady behaviour are combined, in order to develop a linear timevariable transfer for the noise.

List of Symbols and Abbreviations xv

In chapter seven, the phase noise issue is detailed to the circuit level, by an analysis of the noiseperformance of the different constituent blocks of the PLL. The parameters that can distinguishthe dominant noise sources in measurements are identified, and two simulation examples arepresented. Furthermore we discuss behavioural models to mix system and circuit descriptions insimulations. We also present considerations about the implementation loss in the receiver due tothe phase deviations in the LO signal. Practical examples, simulations and measurements, arepresented in chapter eight, where these analytical tools are used to design and evaluate twotestchips. The testchip designs are briefly presented, they contain a PLL and a monolithic Gm-Coscillator that covers the satellite band L (950MHz to 2150MHz). Testchip TC2 is part of adouble synthesizer with a comparison frequency that goes up to 330MHz, with an in-loop noisein the order of –108dBc/Hz. Testchip TC3 explores the maximum bandwidth of a single loopPLL and confirms the theoretical approach of chapter five. Finally we compare the spectra oftwo synthesizers: a single loop PLL plus an LC oscillator and a double loop synthesizer plus aGm-C oscillator, both for a QPSK near zero-IF receiver. The comparison refers to the allocationof implementation loss in a tuner, due to the phase deviations in the LO. Two examples of highand low bit rate channels are discussed, and the margin for production for the most criticalparameters is calculated.

This thesis was developed in the industrial site of Philips Semiconductors in Caen, Normandie,France. It was part of a collaboration contract between Philips Semiconductors and the INSA deLyon, or more specifically the electrical engineering laboratory CEGELY.

I would like to thank all of the colleagues within Philips Caen and Philips Eindhoven for theirhelp and support.

Caen, June 99,

Marina de Queiroz Tavares

Chapter 1 / Introduction 1

Contents:

1 Introduction 1

1.1 The frontend in a telecommunication receiver.........................................................................................2

1.2 The frontend in TV broadcasting .............................................................................................................3

1.3 Current tendencies: low noise and higher integration.............................................................................9

1.4 PLL systems : different application contexts .........................................................................................14

1.5 PLL frequency synthesizers constituting blocks and nomenclature .......................................................151.5.1 VCO...............................................................................................................................................161.5.2 Dividers..........................................................................................................................................171.5.3 Phase Detector – Charge Pump......................................................................................................171.5.4 Loop Filter .....................................................................................................................................19

Figures:

Figure 1.1 Example of a communication transceiver: TX and RX systems................................................2Figure 1.2 Heterodyne Receiver _ Terrestrial TV Frontend.......................................................................4Figure 1.3 DVB Satellite transmission modes...............................................................................................6Figure 1.4 Satellite Receiver Frontend: heterodyne and ZIF architectures...............................................7Figure 1.5 Local Oscillator Spectral Purity X SNR .....................................................................................9Figure 1.6 Carrier Spectrum........................................................................................................................10Figure 1.7 QPSK constellation + phase deviation........................................................................................11Figure 1.8 Phase Noise requirements ..........................................................................................................12Figure 1.9 PLL frequency synthesizer: block diagram..............................................................................16Figure 1.10 VCO and tunable resonator .......................................................................................................16Figure 1.11 Phase Detector & Charge Pump block diagram ......................................................................18Figure 1.12 Phase detector & Charge pump: transfer and state machine .................................................19

Tables:

Table 1-1 DVB standards: bandwidth and modulation types......................................................................10

1 Introduction

In this chapter we locate the context of this thesis by introducing basic aspects and innovationtendencies for the frontends of TV broadcasting receivers.This thesis focuses on the frequency synthesizer block, which is a constituent part of thefrontend.PLL frequency synthesizers are a common element of different telecommunication receivers thatare produced on a large scale. This choice is connected to their compactness and low cost, bothof which are continuously improved by larger integration levels.Furthermore, emerging digital modulation techniques are imposing new requirements on thisblock, which carries out the frequency conversion of the input data.Finally, we shortly describe the constituent elements of the PLL synthesizer, so as to presenttheir functionality and general structure.

2 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

1.1 The frontend in a telecommunication receiver

Communication and transport are probably the key technological fields that most changed dailylife in the 20th century. Our world became smaller, because it may be rapidly crossed by wavesand engines taking information and people worldwide.

The term communication system is employed here to include transceivers that convert data intoelectromagnetic waves (transmitters_TXs) and the other way around (receivers_RXs), in order totransmit this data through a fast moving media such as air, metallic cables, optical fibers andothers.The TX and RX have two basic parts, namely:• Backend: data processor and (de)modulator;• Frontend: frequency translator and selectivity.The first one is in charge of transforming data into a convenient manageable electrical signalthat is later transposed into a well defined frequency window (channel) by the second.i

Figure 1.1 Example of a communication transceiver: TX and RX systems

The spread of communication systems relies on the advance of modulation techniques, digitalsignal treatment and RF-frequency electronics. The first two greatly increased the amount andquality of transmitted information, and the last one enabled the utilization of an increasing rangeof the frequency spectrum.However this spectrum range is limited by the physical properties of the conducting materialsand the maximum working frequencies of the electronic devices employed. So furtherexploitation of this already crowded spectrum depends on a greater compaction of modulateddata, or capacity to share the same frequency range (spread spectrum modulations).Occupying narrower frequency bands with higher information density decreases the margin forsignal degradation in the up and down conversion of the data in the TX and RX systems. In otherwords, modulation types with increasing bandwidth efficiency require higher signal-to-noiseratio (SNR) for a correct reception.

i There are also communication systems that use base band transmissions, i.e. the data is directly transmitted after

modulation, without being frequency translated. However the applications are usually restricted by their maximumdata flow.

Frontend Backend

inputdata

data processor+

Modulator

Up

Conversion

outputdata

Demodulator+

data processor

DownConversion

+Selectivity


Up and down conversions are carried out by mixing data signals with carrier signals in TXs, orby mixing channels with carrier signals in RXs. Therefore the loss of quality due to thisoperation depends on the mixer and carrier qualities.Mixer performance is usually specified in terms of conversion gain, noise figure and linearityparameters, amongst others. There is a compromise between the parameters of gain on one sideand linearity and noise figure on the other. This compromise has to be solved in combinationwith the specifications of the filtering and amplification stages, taking into account theconstraints of consumption and signal quality.The carrier signal performance includes factors such as frequency tunability and spectrum purity.The frequency tunability refers to the coverage of a frequency range, with a certain resolution orminimum variation step. The carrier spectrum quality is often defined by a carrier-to-noise ratio(CNR), specified in accordance to the modulation nature and SNR requirements of the datasignal.

Carrier signal generation can be split into three basic types:- Direct digital synthesis (DDS), using sine look-up tables, accumulators and digital clocks.

They are often limited in speed and quality by the maximum clock frequency. Thus, they aremore frequently employed in band-base (BB), or intermediate-frequency (IF) stages; mainlyafter analog-to-digital data conversion (ADC).

- Mixer-divider chains, combining an ensemble of reference oscillators, through frequencyconversion and filtering. Increasing the precision and the frequency range is a trade off withsize, integrability and power consumption. They are often bulky systems that become hardlyintegrable as the number of reference sources increases. For non-integrated systems, theadvantage of keeping the spectral purity of the sources may be decisive.

- Feedback loops with a reference source and a programmable counter block to sweep thefrequency range of a tunable oscillator. Phase-locked loop types are the most widespread intransceiver applications. Integrability and low cost are the main advantages, but settling timesare elevated compared to methods of direct synthesis.

A wide span of systems of hybrid generation combine the basic types above to explore theadvantages of each architecture. They may be generally called multi-loop architectures, as theycompose the carrier signal through two or more loops in different concatenated and/or interlacedstructures.The scope of the present work is centered around PLL frequency synthesizers for terrestrial andsatellite TV receivers. Stability and noise issues are discussed and applied to single and doubleloop architectures.The models developed for stability and disturbance are certainly useful for other PLLapplications, but the issues and numerical examples are oriented by the primary context.

1.2 The frontend in TV broadcasting

The block schematic below represents a heterodyne receiver, detailing the elements of theselectivity and frequency conversion stages.ii

ii

The denomination heterodyne or superheterodyne, is given to receivers working with two distinct amplificationand filtering sections prior to demodulation.


Figure 1.2 Heterodyne Receiver _ Terrestrial TV Frontend

(1) 1st RF filter: large bandwidth filtering plus impedance adaptation between antenna and pre-amplifier;(2) RF pre-amplifier: 1st amplification stage (keeping SNR), plus buffer avoiding fosc leakage towards the antenna input;(3) double RF filter: middle bandwidth filtering, rejecting image channel and also blocking VCO signal ;(4) Mixer: frequency conversion kernel: conversion gain, linearity and noise figure constraints;(5) Local Oscillator (LO) + PLL tuning system: carrier generator for down-conversion, and frequency tuning for oscillator and input filters tracking;(6) IF pre-amplifier: gain prior to selective filtering to keep minimum SNR;(7) IF filter: fixed frequency very selective filtering (SAW filter);(8) IF signal treatment: amplification, demodulation and signal level detector.

TUNE

(5)

(1) (2) (3) (4) (6) (7) (8)

BBoutputdata

VAGC

Vtune

VCOor

LO

PLL

video&

audiodemod.

Leveldetector

RF stage IF stage


In figure 1.2 the incoming signal is initially modulated at the channel or RF frequency, where aprimary rough selection is carried out by filters (1) and (3). After the first frequency down-conversion, the input data appears around the IF, and passes a sharper selectivity stagerepresented by filter (7). A convenient amplification level is assured by an automatic gain control(AGC) loop, with an amplitude sensor at the BB stage.The elements constituting the tuner are indicated by the dotted arrow. In a TV set the tuner iseasily recognized by its metallic screening box, used for RF isolation.The sequence of filtering, mixing and amplification blocks reflects an important trade-offbetween selectivity and frequency tunability. For elements with a frequency dependentbehaviour, these characteristics usually oppose each other. Therefore the RF stages covering thewhole input frequency range are necessarily less selective than the IF stage, working at a fixedfrequency.RF filters and oscillator are constructed with similar resonant circuits, assuring the correlation oftheir frequency variation, also named tracking characteristic or matched filter-oscillators.The frequency tuning of the RF stages is made by the PLL block. It contains a feedback controlsystem, comparing the RF oscillator to a reference crystal oscillator. The frequency variability isguaranteed by programmable counters interpolated in the control loop.

The work in this thesis deals with stability and noise aspects of the PLL plus RF oscillatorensemble, correlating their specifications and design constraints to the tuner applicationrequirements. The tuner architectures and the issues studied are focused on the TV receptioncontext, for both terrestrial and satellite applications.In fact figure 1.2 represents a terrestrial tuner architecture, with the following typical values ofRF and IF frequencies and bandwidths:i

• RF input, channel frequency range divided in three bands:- VHF I: 47 MHz ------- 140 MHz- VHF III: 140 MHz ------ 400 MHz- UHF: 400 MHz ------ 860 MHz

The input amplifier, filtering and mixing stages are often doubled, having one set specificfor the reception of the VHF bands, and the other for UHF.

• Most standards work with: Fvco = FRF + FIF

and IF typically within the range : 39 MHz --- 55 MHz The choice of Fvco larger than FRF reduces the relative tuning range (fmax/fmin) of the localoscillator. The highest possible IF value is chosen, to ease the filtering of the image channel,but usually outside the reception bands, to avoid direct coupling between the RF input and theIF output.

• Channel bandwidth: 6 MHz --- 8 MHzMost of the channel bandwidth is occupied by the video information. The audio istransmitted through a modulated subcarrier that is placed in the high end of the channelbandwidth, between 4 and 6 MHz.

• The bandwidths of band-pass filters (1) and (3) vary significantly amongst the differentapplications. For instance, filter (3) may present a bandwidth between 7 and 25 MHz. Therejection of this same filter for the image channel is in the order of 60 dB.Filter (7) presents a sharp selectivity for the neighbouring frequencies, and a bandwidth inthe order of 5MHz.

• The AGC dynamic for the amplifying blocks of the tuner is generally between 40 and 50 dB,with another 60 dB controllable amplification capacity in the demodulator.

i The frequency values indicated for the terrestrial and satellite applications are just a rough range, close to the most

common standards. There are several standards with different values for RF, IF and channel width.


For analog standards, the minimum SNR at the IF output is in the order of 55dB, to startcausing visible errors in the video reception.

Satellite tuners have a slightly different architecture, as shown in figure 1.4.The RF transmission bandwidth, Ku-band, is rather elevated, which imposes a first frequencyconversion close to the antenna, in order to support the losses through the cable binding theantenna and the RX frontend.• 1st RF at the antenna input, Ku-band: 10.7 GHz -- 12.75 GHz ;• Constant LO frequency down-converting block: LNA (low noise amplifier)

Due to the strong attenuation between the satellite and the RX antennas, this block has tightnoise figure requirements;

• 2nd RF at LNA output, band L : 950 MHz -- 2150 MHz .

The older analog standards, (DBS - Direct Broadcast Satellite), use FM modulated channels witha bandwidth varying between 27 and 36 MHz.The more recent digital norms, (satellite DVB – Digital Video Broadcasting), have differentchannel compositions, using multiplexing in frequency and time domain (see figure 1.3). In thiscase we prefer to refer to the frequency spacing as the transponder bandwidth, regarding theensemble of signals transmitted by a single amplifier in a determined frequency window.• Transponder bandwidth: 33 MHz – 36MHz ;• MCPC (multi-channel per carrier): single modulation package multiplexing in time

(TDM) up to 8 TV channels transmitted in a bitflow with rates around 55 Mbps;

• SCPC (single-channel per carrier): several narrow bandwidth channels splitting thetransponder spacing;

• Multicast (analog+digital channels): a standard analog FM channel of 27 MHzbandwidth multiplexed in frequency with a 9MHzwide digital channel, transmitted with a powerlevel 13dB below the analog channel.

Figure 1.3 DVB Satellite transmission modes

The first RX systems for QPSK channels used a double IF heterodyne architecture, with thefollowing intermediate frequencies:• 1st IF: 460 MHz – 480 MHz; with 1st LO: Fvco1 = FRF + FIF1

• 2nd IF: 70 MHz, and a down-mixing stage with a LO containing 2 outputs in quadrature.The choice of the 2nd IF was connected to the availability of SAW filters with Nyquist slope atthis frequency. The demodulation and decoding are performed by a digital IC, whose ADC inputis connected to the band-base output of last mixing stage.The last LO converting the data to the base band has quadrature outputs, splitting the output datain I (in phase) and Q (quadrature) outputs.

36MH

MCPC SCPC MulticastQPSK QPSK FM QPSK

13dB


Figure 1.4 Satellite Receiver Frontend: heterodyne and ZIF architectures

VAGC

Vtune

SAW

VAGC

IQ BB

outputdata

RF stages

Vtune

heterodyne receiver Fvco = FIF + FRF

FIF ~ 470 MHz

2nd

1st RF

VAGC

IF and/or BB

LNAdown

converter

Near-zero IF receiver Fvco = FRF

BBoutputdataSatellite demod. & decoder

(SDD)

Vtune

VCO

PLL

90°

Demo-dulator

Leveldetector

VCO

PLL

IQ

90°

carrier&

clockrecovery

forwarderror

correction

ADC&

filters

Leveldetector


In more recent systems the Nyquist filtering is integrated in the digital IC realizing thedemodulation and signal decoding. Thus an intermediate heterodyne architecture uses a single IF(similar to the 1st IF above) and a quadrature LO at this IF frequency (see upper half of figure1.4).

Finally the latest satellite tuner ICs are concentrating in a monodyne, near-zero IF architecture(see lower half of figure 1.4). There is one single stage of frequency translation between the 2nd

RF (band L) and the BB output.It is certainly an architecture allowing greater compactness and economy in externalcomponents, but also increasing the performance constraints for the integrated blocks and thesurrounding application.The advantages are connected to the suppression of the IF stage and the replacement of the SAW– BPF by a discrete and cheaper LPF. Besides, the rejection of the image channel (which is nowthe selected channel but with a spectrum reversion) can be replaced by a proper output form,containing the necessary information to distinguish the two superposed spectra. The I and Qoutputs have this convenient format, and furthermore they are adapted to the demodulation of theQPSK modulated data.The limitations are connected to the performance of several blocks such as:- the quadrature LO, which now works in the band L, and needs to fulfill the conditions of

minimum mismatches in amplitude (<0.5dB) and quadrature (<3°);- the matching of the I/Q stages in BB;- the isolation and linearity of the RF amplifiers and mixers.In fact the monodyne RX is especially sensitive to coupling between the RF and LO signals (inthis case at the same frequency) and to interference generated by intermodulation products ofeven orders (appearing at low frequencies).

The nomenclature near-zero IF stress the fact that the LO signal is not locked to the RF input, butis programmed to a frequency close to the RF carrier. The precision is also limited by theminimum allowable tuning step in the LO controlling loop. The difference between the outputspectrum and a real BB signal are recovered by the digital demodulator in the so called, carrierrecovery loop.Figure 1.4 illustrates block schematics of a heterodyne, single IF, and a near-zero IF (named ZIFor zero-IF for short) receivers. In both configurations the AGC dynamic range, for the tuner, is tothe order of 50 dB. The bandwidths of the filters are greatly dependent on the application. Theminimum SNR at the base band output will depend on the maximum bit-error rate that can becorrected by the signal decoder. A maximum bit-error rate (BER) of 10-4 is usually acceptablefor most decoders, and it implies a minimum SNR of 11.4dB for QPSK modulated data[Sinde98a].We can note the large difference of the minimum SNR for the reception of analog terrestrial TVsignals and the satellite digitally modulated ones. However the latter suffers from much largerattenuation in the transmission path, and it would not be feasible to work with such high SNR asin the terrestrial systems.Another important difference between the terrestrial and satellite applications, besides theirfrequency ranges, is the constraint for the filtering of the neighbouring channels.Satellite transmitted channels have the same power levels at the RX input, as they come from acommon TX source.In terrestrial transmission, neighbouring channels may come from different TXs andconsequently their incoming power vary greatly according to the TX and RX “line of sight”.


The “line of sight” concerns the distance and blocking obstacles, causing attenuation andreflection of the transmitted signal.i

Figure 1.5 illustrates the importance of the carrier spectral purity for the proper reception ofneighbouring channels with different input power.

Figure 1.5 Local Oscillator Spectral Purity X SNR

The channel with lower input power, centered around fch2 , is degenerated by an adjacent channeldown converted by a noisy local oscillator.This example introduces the idea that the tuner requirements, with respect to selectivity and SNRdegradation, may be translated to corresponding specifications for the frequency synthesizerblock.From now on, we concentrate our attention on the frequency synthesizer block, marked by a grayrectangle in the frontend schematics (figures 1.2 and 1.4).In the next section we discuss some current tendencies in the development of tuner ICs, relatingthe new requirements to the emerging digital broadcasting systems.

1.3 Current tendencies: low noise and higher integration

Current trends in the tuner circuit developments are bound to the developing standards usingdigitally modulated signals, and to the continuous demand for higher integration levels.Nowadays, tuners often have one single integrated circuit (IC), a MOPLL, including the PLL,mixer-oscillator and IF amplifier blocks. This level of integration is the result of a continuousminiaturization that combines the functionality of several ICs and also integrates parts ofpreviously discrete circuitry.Furthermore the more recent digital standards, based on phase modulation techniques and/orusing closely spaced multi-carriers, are imposing new constraints on the CNR of the localoscillator. Therefore from the basic requirements of the frequency synthesizer concerning thetuning range and the resolution, other more strict parameters of spectral purity are added.

i Signal reflection causes multi-path reception, where different phase delayed versions of the input signal reach the

RX. Specially for strongly attenuated signals this is an important draw-back, decreasing the SNR and adding noisewhich is correlated to the signal.

IFRF

LO

fch1 fch2

flo

flo-fch1

flo-fch2


Figure 1.5 sketches the pollution of the input RF signal by the spectral dispersion of the localoscillator. The spectral purity is largely discussed during this work, and in the PLL synthesizercontext we will see that it is directly associated to the phase noise in the carrier signal. Thereforethe specifications of phase noise in the output of a local oscillator, are a translation of the CNRrequired for the reception. These specifications also depend on the modulation type and on theselectivity of the input filtering stages.Analog terrestrial TV standards use vestigial side-band (VSB) modulation and FM for the videoinformation and either FM and AM signals for audio. In satellite applications the analogstandards use FM signals, needed for their robustness with respect to amplitude distortions.When talking about SNR, we concentrate on the video signal because of its larger amount ofinformation compared to the audio signal. Besides the video signal needs higher signal qualityfor an interference-free (or error-free) reception.In particular for FM signals, the noise added by a local oscillator with 1/f2 power sidebands (asrepresented in figure 1.6) is demodulated at the output as a flat, white distributed noiseinterfering in the output data. Therefore in the FM context, noise specifications are often boundto the free running, or out-of-loop, carrier spectrum, transmitted by the VCO intrinsic noise.

Figure 1.6 Carrier Spectrum

Digital video broadcasting standards and services have undergone great expansion recently. InEurope the DVB-S, DVB-C, DVB-T and DAB describe the norms of video and audiotransmissions through satellite, cable and terrestrial or off-air systems.

DVB-S DVB-T DVB-C DABBasic

modulationprinciple

Single carrierQPSK modulated

Multiple carrier OFDMsubcarriers modulation:

QAM16 or QAM64

Single carrierM-QAM modulated(M=16, …64, 256)

Multiple carrier OFDMsubcarriers modulation:

DQPSKNumber ofsubcarriers

& frequencyspacing

_ 1705 / 6817mode: 2k / 8k∆f= 4.47kHz / 1.12kHz

_ 193/ 385/ 769 /1537mode: 1 / 1.5 / 2 / 3∆f= 8kHz /…/ 1kHz

Signalbandwidth

Not fixed, e.g.:33MHz – 36MHz 7.61MHz

Not fixed, e.g.:7.9MHz 1.536MHz

Gross datarates [Mbps]

Not fixed, e.g.:51.60 10.80 – 39.27

Not fixed, e.g.:34.37 2.304

Frequencyranges

10.7 – 12.75GHz2nd RF:

950 – 2150MHz

VHF IVHF III

UHF

VHF IVHF III

UHF

Slots within: VHF IIIBand L

Table 1-1 DVB standards: bandwidth and modulation types

Programmable&

tunable range

N.fcp f [Hz]

|P(f)|singlesidebandphase noise

fosc f [Hz]


The DAB system, initially imagined for audio transmission only, has developed into amultimedia standard (DMB), showing important advantages for mobile applications whencompared to the DVB-T.All these standards have source coding algorithms based on MPEG-2. Table 1-1 [Roma97]presents a short overlook of these standards.The first digital broadcasting services available were the single carrier ones, requiring simplerTX and RX. Nowadays there are also DAB radio and data transmission services, and the firstconsumer DVB-T systems are currently being tested.

The minimum signal to noise ratios vary in accordance to the bandwidth efficiency of thedifferent types of modulation and coding. For example, for a maximum BER of 10-4 , the SNR ofa DVB-C channel in QAM 64 is 24.3 dB, and in QAM 256 it equals 30.2 dB [Sinde98a], which is considerably higher than the SNR for the QPSK channel.

The underlying modulation principles are either phase or phase and amplitude based. Thus withrespect to the sensitivity of the local oscillator to the CNR, we may expect that the phaseaccuracy of the carrier becomes relevant.Indeed, the specifications for the LO spectrum become very tight. For example, tunerconstructors ask for the following phase noise performances: for QPSK receivers a maximumtotal phase deviation under 2°; or for OFDM receivers a single side-band (SSB) phase noiselower than –80dBc/Hz at a frequency offset of 1kHz.However, most of these specifications are empirically determined, and they strongly depend onthe application used for the measurements.More formally, these specifications can be derived from the allocation of implementation losseswithin the system. For DVB standards, the implementation losses due to the phase deviations ofthe LO signal should be kept below 0.2 dB [Sinde98a]. This requirement can be translated into atotal phase deviation brought by the synthesized carrier. Nevertheless, the relationship betweenthe implementation loss and the LO phase deviation depend on the characteristics of thedemodulator used in the reception.Therefore the specification for phase deviations, either as a total value in degrees or as amaximum SSB level at a certain offset, reflects the sensitivity of the ensemble, frontend plusdemodulator, to a certain noise spectrum shape.

The optimization of the phase deviation in the LO signal is one of our central subjects that isprogressively discussed in the following chapters. At this point, we give a first glance of theissue with figures 1.7 and 1.8.

In figure 1.7 we sketch the influence ofphase noise in a QPSK constellation,showing that phase deviations directlyincrease the occurrence of errors in bitdetection.

Figure 1.7 QPSK constellation + phase deviation

QPSKconstellation

∆ϕ


The total phase deviation can be calculated integrating the sidebands of the LO spectrum, asshown in figure 1.8.a. The lower and upper limits of the integral are determined by thedemodulator and channel bandwidth parameters.

Figure 1.8 continues the zoom around fosc started in figure 1.6. It shows noise specifications thatmay concern the intrinsic behaviour of the oscillator (out of loop SSB phase noise) or the PLLblocks (in loop SSB phase noise), used to tune the oscillator frequency.

Figure 1.8.a Figure 1.8.b

Figure 1.8 Phase Noise requirements

For multicarrier standards, the noise specifications are eventually determined by a maximumthreshold for the level of the sidebands, for offsets that are comparable to the frequency spacingbetween subcarriers.Figure 1.8.b shows two carrier spectra with different noise performances, and it also indicates aSSB phase noise limit for two different frequency offsets(foff-1 and foff-2).The dotted line spectrum presents a better oscillator performance than the solid line spectrum.However as the offset frequency of the noise specifications decreases, it becomes harder to fulfillthis requirement by relying only on the oscillator characteristics.The solid line spectrum shows an option where the in-loop (PLL related) noise performance isadapted to the CNR specification at both offsets: foff-1 and foff-2 . In practice this situation appearsin two contexts:• very strict noise performances related to modulation types with compact data representation

in narrow bandwidths or using multi-carriers closely spaced to each other. In TVbroadcasting the OFDM (Orthogonal Frequency Division Multiplexing) standard has themost strict specifications concerning the local carrier spectral purity.

• oscillators with a poor intrinsic noise performance, but associated to low noise PLL. Thissituation is often encountered when using completely integrated oscillators.

The second situation sends us back to the trend for higher integration levels.Currently, most of the controllable LOs are based on a resonant amplifier with an externalresonator.The large frequency range of the TV applications limits the possibility of integrating the resonantcircuit, as occurs in narrow band reception systems, like mobile telephones. Therefore otheroscillator structures, like ring or relaxation, have to be tried.

foff-1

foff-2

……

fmin fmax

fosc f [Hz]

foffset

in loopSSBphase noise

out of loopSSB

phase

∆ϕ2/2


The drawbacks of these other structures are: their poorer phase noise performance as comparedto LC resonators with high quality factors, and the impossibility to track the LC matched filtersin the input stages of the tuner.The advantages appear mostly in the zero-IF configurations, where a totally integrated oscillator,with no LC resonator, increases the robustness to RF interference.Therefore the integration tendency forces architectural modifications in the tuner. The absence ofexternal tracking filters can be more easily coped with in satellite receivers, where the uniforminput level enables a feasible compromise between selectivity and linearity requirements.ii

Furthermore, it is also in satellite applications that we see more and more frontend receptorsusing direct conversion, or ZIF receivers. Direct conversion schemes have new constraintsrelated to the suppression of the IF stage. The AGC dynamics in the RF and BB parts have toreplace the previous IF dynamics while preserving the linearity and noise figure properties.Coupling interactions between the local oscillator and the RF input signal (now in the samefrequency), have to be controlled to reduce the signal degeneration by “self-reception” or “self-demodulation”.These constraints brought an additional interest to a completely integrated oscillator sufferingform less external coupling problems. The integrated oscillators may also be piloted by a secondoscillator with an external resonator but working at a different frequency; or in other words, amulti-loop synthesizer.The use of an integrated oscillator covering a large tuning range often brings an inherentdegradation of the oscillator spectral purity. Thus achieving strict phase noise requirementsbecomes obligatory for the PLL circuitry.In fact, figure 1.8 showed that the noise requirement imposes a compromise between the PLLand the VCO noise performances. Furthermore the variable parameter adapting theseperformances is the loop bandwidth, which unfortunately is not independent of other parameterssuch as loop gain, comparison frequency, minimum tuning step and DC tuning range.In summary the following topics, that are closely related to the evolution of an analog carriergeneration for RX frontends, are guiding the issues studied in this work:

Noise and stability treatments for large bandwidth and low phase deviation PLL synthesizers in tunerapplications;

Low Phase Deviation: the VCO spectrum has to be optimized for minimum phase deviations inaccordance to the new digital modulation standards (DVB standards: QPSK, QAM, OFDM).

A combination of PLL and VCO noise performances are the IC parameters that can be specifiedto fullfil this specification. The PLL bandwidth is the compensation variable between theperformances of these two circuits.As the improvement in coverage+selectivity of the VCOs attains a limit, the noise quality of thePLLs starts to be an issue. Nevertheless, to rely on the PLL characteristics, we need to controlthe closed loop bandwidth, and learn about the constraints that limit the PLL bandwidth.Furthermore, for solutions with integrated oscillators, multi-loop schemes with large PLLbandwidths are required.

PLL synthesizers in tuners have to cope with large variations in gain parameters, in an applicationcontext that is not very flexible. So the most natural and inexpensive point for optimization is a carefulfitting of the loop filter.

The three issues above are completely entangled with each other since the optimization of thespectrum suggests bandwidth constraints that have to be guaranteed within the whole gaininterval.

ii

Another option to the input filtering is to integrated selectivity stages with structures that are matched to theintegrated oscillator. However this option is quite challenging for the aspects of power consumption and RFisolation.


These issues are the conducting line through the sequence of practical and theoretical pointstackled in this work.In the next sections a short listing of PLL applications precedes a description of the constitutingblocks of a PLL synthesizer.

1.4 PLL systems : different application contexts

Phase locked loops are feedback systems containing at least a controllable oscillator and a phasedetector. The phase detector is the comparing element between a variable or steady input and thedriven oscillator element. Frequently there is also a filter before the input of the oscillator,determining the bandwidth of the feedback action.

The first PLL applications were synchronous receptors for coherent demodulation, and the firstindustrial use on a large scale appears within the TV market (in the 50’s), for the synchronizationof horizontal and vertical scans. In particular for PLL synthesizers, the first patents appeared inthe 70’s.

The application contexts are widespread in areas such as: communications, radar, telemetry,command, time and frequency control, ranging and instrumentation systems.However with respect to their functionality there are mainly three areas:

• Carrier Tracking and Synchronization;• Coherent Demodulation of Digital and Analog Signals;• Frequency Synthesis.

In the first two, the phase detector receives a variable input, from which one tries to extract eithera carrier or the information that modulates the input signal. In the third, the oscillator is coupledto a fixed reference, in order to transfer to this, frequency and phase properties of the referencesignal.This division is also related to the PLL functioning modes: acquisition, tracking, and, locked orsynchronous mode.The acquisition mode refers to the interval during which the loop wanders within its tuningrange, searching to follow the input, but still not locked to it. The tracking mode concerns thefunction of the PLL when it follows a non constant input, whose variations have to be trackedwithin the tuning range. Finally, the locked mode refers to synthesizers with a constant input.

Some different investigation issues are seen in association with the fields of application above:• in coherent demodulators: cycle slips, limits of tracking,… .

These are phenomena described in the time domain with complicated non-linearbehaviour and modeling;

• in synthesizers: noise performances, locking time, stability, aided acquisition. Usuallydescribed in linear, frequency domain representations.

• in general: aspects concerning the increasing integration level of the PLL blocks, withlower power consumption, higher working frequencies, and in combination withother analog and digital blocks. This last point concerns the generation and sensitivityto interference in the supplies and in the substrate (for integrated blocks that share acommon substrate and/or common supplies).

The phase detector, such as the comparator block in the feedback system, specifies manycharacteristics of the control loop. It is not unusual to classify a PLL with respect to the type of


the phase detector. There are numerous references discussing the different types of phasedetectors. A general insight of different PLL applications can be found in [Wola91], and a morespecific description focused on the synthesizer context is made in [Craw94].

We would like to enumerate some phase detection principles relating their characteristics ofmemory or tracking to their respective applications:

• Mixers: non-linear element outputting the sum and difference of the frequencies ofthe input tones. A low pass filter is used to select the difference portion.The output, which represents the phase error, may depend on the amplitude of theinput signals. The tracking range is limited by the sinus periodicity.This structure is often reserved to applications with a critical phase noiserequirement, or with very high input frequencies.

• Samplers: non-linear element bringing a high frequency component to base band byaliasing with a known input tone.It has also a limited tracking range due to the ambiguity of the folded elementscoming from different harmonics of the input signals. Its advantage is related to thepossibility of extremely fast lock intervals.

• Exclusive-OR: very similar properties with the mixer type with a digital logicalimplementation.

• Two-state detectors: logical implementation containing two memory nodes, or a flip-flop, for set and reset states. The tracking zone is expanded with respect to theprevious memoryless types.

• Three-state phase and frequency detectors: two flip-flops and an asynchronous resetreturn. The tracking zone is unlimited allowing frequency and phase error correction.It is the common type used in PLL synthesizers. The three-state phase/frequencydetector and its tri-state implementation are discussed in the following section.

We close this section with the remark that the limited tracking solutions are mostly adapted tolow SNR loops, where the phase detector has to average a carrier or signal information mixedwith important noise levels, such as in carrier and clock recovery applications. In suchconditions, a memory phase detector would have difficulty to attain lock, due to the strongdeviations it would suffer in the presence of high noise levels; or in other words, due to itsabsence of error averaging.

1.5 PLL frequency synthesizers constituting blocks and nomenclature

From now on we treat exclusively the frequency synthesizer PLL. The block schematic of figure1.9 introduces the basic constituting elements and their nomenclature.The input is a crystal oscillator with a very selective output, related to an external quartzresonator. The input frequency may be changed by programming different ratios in the referencedivider; thereby choosing the frequency at the input of the phase detector: fcp (comparisonfrequency).The phase detector is a three-state type, with a current output block, named a charge pump. Theloop filter has an impedance magnitude, and it translates the current information into the tuningvoltage input for the VCO.The programmable divider, that is interpolated between the VCO and the phase detector, fixesthe ratio between fcp and the LO frequency. Therefore the dividing ratios also determine thecoverage of the tuning range of the synthesizer.


In addition, there are auxiliary service blocks, such as switches and analog-to-digital converters(ADC), that are used to command the functioning of the filtering and amplifying elements withinthe tuner.

Figure 1.9 PLL frequency synthesizer: block diagram

The following sections give further details about some central blocks of the frequencysynthesizer.

1.5.1 VCO

The VCO is often a resonant amplifier that contains a tunable band pass filter (BPF) and a gaindevice. The active device amplifies the inherent noise sources that are filtered by the resonator,before they are fed back to the amplifier input.The selectivity is then determined by the resonator. Usually, the resonant circuit is a secondorder LC structure with a tunable capacitance, composed by capacitors and varicaps.

Figure 1.10 VCO and tunable resonator

In figure 1.10, the ground signal just indicates the DC biasing of the varicap. Often, a largeresistor or inductor is added for this DC connection.The series capacitance Cp (padder) is chosen as a compromise between the diode capacitanceratio (Cmax/Cmin) and the quality factor (Q) of the resonant circuit . A minimum Cmax/Cmin is

Cp

R

Vtune

Lp

CtCd

fcp

Programminginput

LOoutput

CrystalOscillator

ReferenceDivider

PhaseDetector

ChargePump

LoopFilter

VoltageControlledOscillator

(VCO)

MainDivider

BUS

Biasing&

ServiceBlocks


required to cover the whole tuning frequency range, whereas the quality factor determines thephase noise performance of oscillator.Cp values larger than Cmax tend to be transparent for the capacitance variation. However smallervalues may be needed to improve the quality factor. This improvement is achieved by the serialassociation of the varicap, with a poorer Q, with a fixed capacitor that has a better Q.The parallel capacitor Ct assures a minimum capacitance value and it may be added tocompensate for the changes in temperature of the IC input impedance.The structure described above corresponds to a resonance oscillator, which is the most commontype of VCO that is encountered in frequency synthesizers for TV tuners. For other PLLapplications working with smaller tuning ranges, it is not unusual to also find ring and relaxationoscillators, that are tuned by a variable biasing current or voltage. In chapter 8, we discussanother controllable oscillator structure based on cascaded integrator stages.

1.5.2 Dividers

The dividers, both reference and main, are cascaded structures composed of flip-flops andcombinatory logical ports. Basically we may distinguish two structures:

• prescaler structure: composed of divide-by-2 or swallow cells;• shift counter.

The prescaler is normally at the input stage, and it works with the higher frequencies. It may befully programmable or not, depending on the limitations of frequency and sensitivity in the inputof the main divider.The swallow cells are an extension of divide-by-2 cells, containing two extra latches and somelogic ports. This additional part receives a second data and a synchronizing input that commandsthe “swallowing” of an extra clock pulse. Therefore the swallow cell can count 2+1, and the +1pulse is commanded by the 2nd synchronizing input. Several swallow cells may be connected inseries, working with a common clock and a common 2nd synchronizing input which is shiftedforward between adjacent cells. In this manner the swallow cascade may count all the integerswithin the interval: [ (2n ) , (2n+1 – 1) ] ; where n is the number of cascaded swallow cells.The reference divider usually has a limited set of dividing ratios, and it is implemented with onlydivide-by-2, or divide-by-2 plus swallow cells.The main divider often combines the prescaler with a serial counter. This counter works withlower frequencies, but it has no minimum count. The association of these two structures allowsfor continuous counting between : [ (2n ) , (2n+m+1 – 1) ] ; with n defined above, and m thenumber of flip-flops in the shift counter.

It is important to remark that the output of both main and reference dividers, is in fact thetranscription of one pulse from the input signal, enabled by a programmable counter. In lownoise synthesizers, this output is often resynchronized with the input signal in order to copy itsphase accuracy; or in other words, to eliminate the time jitter introduced by the divider cells.

1.5.3 Phase Detector – Charge Pump

The phase detector and charge pump comparator is a three state phase/frequency detector. Thismeans that it can recover both phase and frequency differences within the VCO + PLL tunableand programmable range.As mentioned in section 1.4 the three-state phase detector has 2 memory nodes, which separatelytrack the two input phases. Figure 1.11 shows a block diagram of the ensemble.


Figure 1.11 Phase Detector & Charge Pump block diagram

The Ref. (reference) input comes from the reference divider, and the Var. (variable) input fromthe main divider. The rising edges of the input signals command the DFF outputs which in turncommand the switches of the sinking and sourcing current sources. When the two outputs areequal to one, an asynchronous reset reinitializes the detector. In this manner phase differences ofup to ± 2π are detected, with an average current output that is linearly proportional to the inputphase difference.The sourcing and sinking sources have a programmable current value that is called charge pumpcurrent, or Icp .

This phase detector with two DFFs, is not capable of distinguishing phase differences with amodule above 2π. So, when the module of the phase difference exceeds 2π, the phase detectorwill slip one cycle and fall into a new linear zone around +2π or -2π.Figure 1.12 represents the transfer, output average current for input phase deviation.Note that the transfer is periodic over 2π, and that two shifted linear regions superpose eachother in every 2π interval.The phase detector behaviour for phase deviations with a module smaller than 2π, is representedby a single valued linear function with an input range: [-2π, 2π]. The thick central line in figure1.12 represents this function, and the slope of the transfer is called Kϕ , the phase detectorsensitivity.

Reference [Wola91] makes an interesting representation of different phase detectors, explainingtheir functioning through logical state machines. The state machine of our three-state phasedetector is pictured on the right side of figure 1.12.The delay interval of the assynchronous reset causes the existence of an intermitent 4th state(Off’), during which both current sources are active. This state is usually transparent for thetransfer function, since ideally the sum of both currents equals zero. Functionally this delayavoids a change in Kϕ for small input phase differences.iii

iii

Charge pump circuitry has often slower setting-up times than the asynchronous reset in the DFFs. Thus smallphase differences would be masked if the switching on interval was to small to guarantee that the current sourcesattained their nominal output value. This phenomena is called dead-zone.

programmableinput for Icp

output tuningvoltage

1

Ref

D Qref

CK

R

Varloop filterimpedance

delay

τrst

1

R

CK

D Qvar


=

rad

AIK cp

πϕ 2(1.1)

Figure 1.12 Phase detector & Charge pump: transfer and state machine

The Off state is also called high-impedance or tri-state, which explains the nomenclature tri-statedetector. Tri-state detectors can also be implemented with a voltage output. In this case the DFFoutputs command switches that short circuit the output to nodes with a fixed voltage value (lowimpedance points such as vcc and gnd). However, the advantage of the current output becomesclear with a capacitive loop impedance, because with the charge pump output a fixed currentvalue charges the filter capacitors with a constant dv/dt and Kϕ .

1.5.4 Loop Filter

The loop filter is the main subject of chapters 2 and 4, while discussing stability and noiseconcepts. It is a low pass filter (LPF) using either a passive (with no DC shift) or an activesolution. The active filters use a high gain amplifier with a large DC output range, in order toincrease the tuning range.

This chapter introduced the context of the present study, PLL frequency synthesizers, in a top-down approach.The frontend of terrestrial and satellite TV receivers was discussed, identifying the tendencies forinnovation, that are bound to the new broadcasting standards (DVB) and to the continuousdemand for higher integration levels.The investigation issues that orient this work were presented and related to the changes in thetuner architecture.The constituent blocks of the PLL synthesizer were also presented.

-I

Iaverage [A]

Icp

∆ϕ[rad]

-4π -2π 0 2π 4π

τrst

Var

Ref

Ref

SourcingQref =1Qvar =0

Var

SinkingQref =0Qvar =1

OffQref=Qvar=0

Off ’Qref=Qvar=1

Var

Ref

Chapter 2 / Phase Model for PLL Synthesizers 21

Contents:

2. PLL Phase Model and Loop Filter calculation 21

2.1. Phase Model for PLL synthesizers .......................................................................................................... 222.1.1. Requirements in the Time and Frequency Domain ....................................................................... 242.1.2. Second-Order Loop ....................................................................................................................... 262.1.3. Third and Fourth Order Loops...................................................................................................... 28

2.2. Algorithm for the Loop Filter Calculation.............................................................................................. 342.2.1. Nominal Design............................................................................................................................. 342.2.2. Robust design including Gain Variation and 3rd Pole compensation............................................. 362.2.3. Summary of steps and numerical example .................................................................................... 40

Figures:

Figure 2.1 Linear Phase Model for a PLL ................................................................................................... 23Figure 2.2 Vtune time response for a frequency step...................................................................................... 25Figure 2.3 Locked VCO output spectrum ..................................................................................................... 25Figure 2.4 3rd order Loop Filter Impedance ................................................................................................. 29Figure 2.5 4th order PLL: Open and Closed Loop Bode Plots ..................................................................... 31Figure 2.6 4th order PLL: Root Locus diagram ............................................................................................ 31Figure 2.7 Gain Variation X Stability in Bode Plots .................................................................................... 33Figure 2.8 The influence of r21 in the gain-bandwidth variation................................................................ 36Figure 2.9 Numerical example of robust filter design.................................................................................. 42

Tables:

Table 2-1 2nd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ] ............................................... 37Table 2-2 3rd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ]................................................ 38Table 2-3 3rd order filter : Open Loop Bandwidth recentering................................................................... 39

2 PLL Phase Model and Loop Filter calculation

A linear time invariant (LTI) model for the PLL synthesizer is used to study frequency and timedomain characteristics.The 2nd order loop is analyzed through standard dynamic parameters ξ and wn .A new notation is introduced to study the 3rd and 4th order loops, exploiting stability androbustness aspects.The study is constantly linked to the tuner application context, through qualitative discussionsand numerical examples.


We start our study of PLL synthesizers presenting a linear phase model that simply andefficiently describes most of the system behaviour around a locked condition. The lineardescription is related to specifications in the time and frequency domain by using a standardnotation for a 2nd order low-pass filter, in terms of its natural resonance frequency (wn) anddamping factor (ξ). The description is enlarged to treat systems of a higher order. We introduce anew notation in terms of the spacing between the zeros and poles of the transfer function of theloop filter. The new notation is used to develop an algorithm to calculate loop filters that respondto stability constraints in a large range of gain variation. The robustness of the method isexemplified by numerical examples.

2.1 Phase Model for PLL synthesizers

From this chapter on, we focus on the phase locked loops for frequency synthesis, with thefollowing constituent blocks: programmable dividers, phase detector based on flip-flops, and tri-state charge pump. We abbreviate it to PLL. In this nomenclature, the VCO block is not includedin the PLL.

A top-down approach is proposed starting with behavioural models that give an insight intofrequency and time domain characteristics. These models are based on a phase representation ofa PLL.The phase representation concerns all logic signals that are inputs of edge triggered blocks.These signals carry phase information that is related to the time interval (T) between similaredges. We may also define an average or initial time interval (Tc) and frequency (fc = 1/ Tc ),and, a phase variation with respect to these.Using the phase variation as the model parameter amounts to a base-band equivalentrepresentation, with phase modulating inputs and carrier fc .The charge pump is replaced by a constant, average current to a phase deviation slope, with thesame sensitivity as a pulse width modulation block (PWM). This linear average sensitivity isvalid for phase differences smaller than 2π, as seen in section 1.5.3 .In fact we seek a simple model where continuous linear time invariant (LTI) tools may beapplied. Such a representation is equivalent to the small signal AC models used for circuitsimulation. In our case its main limitations are the absence of DC range boundaries and theremoval of the discrete nature of the digital blocks (phase detector and dividers). Thesecharacteristics are assessed later with additional modeling in chapter 5 .For the moment, we consider that the PLL bandwidth is small enough compared to the phasedetector comparison frequency, and we suppose that this AC description is valid within thewhole DC range that may be swept.The base-band phase model in Laplace transform is shown in the block diagram of figure 2.1,with:

[ ]

[ ]V

HzK

V

HzradK

KVd

fd

Vd

wdK

vco

o

vcotune

osc

tune

osco

=

⋅=

⋅=⋅== Kππ 22

and Kϕ defined in equation (1.1)


Figure 2.1 Linear Phase Model for a PLL

The phase detector is replaced by an adder that continuously evaluates the phase differencebetween the reference input and the divider output. This phase difference is transformed in anaverage charge pump current, represented by the block with a sensitivity Kϕ.The loop filter impedance, F(s), converts this current in Vtune and the oscillator is depicted by itsfrequency slope associated with an integrator.The VCO is a frequency modulator with a voltage input and frequency selectivity determined byits resonant circuit. Our applications use a second order LC resonator that is equivalent to anintegrator in a base band representation.The linear approximation that allows the calculation of FM components by their peak phasedeviation, is valid for phase deviations considerably smaller than π.Therefore ϕosc (VCO output phase) is a valid approximation of the ratio: modulated sideband amplitude divided by carrier amplitude, for frequency modulating components with Am/fm << π i

where Am and fm indicate the amplitude and frequency of the modulating tone.

We define H(s) and B(s), as the open and closed loop transfers respectively.

s

F

s

sF

N

KvcoIcp

Ns

KsFKsH o

ref

div (s))(1)()( ⋅=⋅⋅=⋅⋅⋅== α

ϕϕ

ϕ (2.1)

with α, the open loop gain:N

KvcoIcp ⋅=α

)(

)(

)(1

)()(

sFs

sFN

sH

sHNsB

ref

osc

⋅+⋅⋅=

+⋅==

αα

ϕϕ

(2.2)

It is convenient to split the filter impedance into two polynomials representing its zeros andpoles.

i More detailed discussions of the narrow band FM context are made in sections 3.1 and 6.2.

for open loop

VCO

ϕosc[rad]

+

-

Phase DetectorCharge Pump

LoopFilter

Iaver[A]

ϕdiv[rad]

Vtune[V]

ϕe[rad]

ϕref[rad]

Kϕ F(s) Ko/s

1/ N


)()(

)()(

)(

)()(

)(

)()(

sNsDs

sNNsB

sDs

sNsH

sD

sNsF

FF

F

F

F

F

F

⋅+⋅⋅⋅=

⋅⋅

=

⇒=

αα

α

Then we may see that B(s) have the same zeros as H(s), and, their poles are equal to H(s) forα=0 (no feedback gain), and gradually change as α increases. This idea is very clearlyrepresented by the rootlocus diagram discussed in 2.1.3.

2.1.1 Requirements in the Time and Frequency Domain

The PLL system performances: locking time, step response overshoot, spurious rejection,stability, closed loop bandwidth and peaking, need to be translated into transfer functioncharacteristics to guide the design of the control function (loop filter). A summary of thesespecifications can be represented by time and frequency response envelopes, as shown in figures2.2 and 2.3.

Let us choose two measurable signals for these envelopes such as Vtune and the oscillatorspectrum.The time response (figure 2.2) corresponds to a frequency change, like a step input for fref , or aramp input for ϕref . Most often however, the frequency change is made by reprogramming themain divider ratio, N.The following parameters are indicated in the time response:

• vinitial / vfinal : initial and final values corresponding to the step input;• Mp : overshoot, normalized difference between maximum value and final value;• trise : rise time with respect to a “y” fraction of the transition step;• tsettling : settling time for error within an acceptable x% variation around vfinal .

The frequency response (figure 2.3) represents the output spectrum of a VCO in lock mode. Theparameters indicating the frequency domain specifications are:

• Pcarrier: carrier output power;• AS : comparison frequency suppression with respect to Pcarrier;• (Pcarrier-AS): spurious amplitude;• fo : oscillator frequency;• bwcl : closed loop bandwidth, or –3dB point with respect to the close in spectrum;• maximum peaking: maximum sideband value with respect to the close-in spectrum.

The specifications indicated in the time and frequency envelopes are the guiding issues discussedin the following sections.


Figure 2.2 Vtune time response for a frequency step

Figure 2.3 Locked VCO output spectrum

We start with the time requirements that may be directly related to a standard 2nd ordercharacteristic equation. Later, we introduce a convenient notation for the 3rd and 4th ordersystems, and a loop filter design algorithm to guarantee a robust stable functioning.The frequency envelope is a combination of the PLL and the VCO performances. In this chapterwe focus on the PLL characteristics. Later, in chapter 3, the complete frequency envelope isdiscussed, taking into account the inherent noise performance of the VCO. All the followingchapters use the filter notation and design tools developed in the present chapter.

vinitial

t (s)

(y).(vfinal-vinitial) + vinitial

(1+Mp).vfinal

vfinal

Vtune(t) = fo(t)/Kvco [V]

trise tsettling

-3dB

Power Spectrum Density (PSD)[dB]

maximumpeaking

Pcarrier-AS

Pcarrier

fosc+ bwcl

foscfosc+ fcp

f (Hz)


2.1.2 Second-Order Loop

We start searching for the simplest filter that would present a time response with the formindicated in figure 2.2.

As a matter of fact, an all-pass filter (simple resistor) combined with the oscillator pole wouldalready present a low-pass filter behaviour for the overall loop.However for a PLL with a phase detector-charge pump comparator, it is useful to guarantee thata frequency step is perfectly followed, having a final phase error that tends to zero.ii

In our phase model the zero final error for a phase ramp input implies an H(s) with two pureintegrators.One integrator is intrinsic to the VCO phase representation, and the other must be included in theloop filter, F(s).A feedback system with two integrators and no zero would be an oscillator, frequency controlledby the loop gain, so we must also include a zero in F(s) for stability reasons. Therefore thesimplest form of F(s) is:

Cs

TssF

⋅⋅+= 1

)( ;

which corresponds to the impedance of a R-C series branch, with T=R.C s/rad.

The open and closed transfer functions for the resulting 2nd order PLL are:

( )

( ).

)(

)(

1

1

)()(

)()(

;)(

)(1)(

2

2

sD

sN

TsC

s

TsN

sNsDs

sNNsB

sD

sN

Cs

TssH

B

B

FF

F

F

F

=+⋅+⋅

⋅+⋅=⋅+⋅

⋅⋅=

⋅=⋅

⋅+⋅=

αα

α

αα

Comparing DB(s) to a standard 2nd order equation, with wn ,undamped natural frequency, and ξ,damping factor, results in:

( ) ( )

C

wR

wC

ws

w

s

TsN

TsC

s

TsNsB

n

n

nn ⋅⋅=

⋅⋅=

=

+

⋅⋅+

⋅+⋅→←+⋅+⋅

⋅+⋅=

αξ

αξ

α

ξα

221

2

1

1

12

22

L)(

(2.3)

ii

Otherwise the error response stabilizes around ϕe-final , which implies that even in lock, the charge pump is stillinjecting an average current (Kϕ . ϕe-final ), which may increase significantly the reference spurious.

Iin

VoutR

C


The advantage of this ξ, wn representation is its direct relation to frequency and time responses.For instance the unitary step response of 1/DB(s) is:

( ) ( ) ( )

⋅⋅+⋅⋅−→←

++⋅=

⋅⋅− tw

wtwe

wswss

w

sDs dd

dt

nn

n

B

sincos12)(

122

2 σξ

σ

Im1

1

2,1

2,12

22,1

sRew

sww

wjwjws

n

nd

dnn

=⋅=

=−⋅=

⋅±−=−⋅⋅±⋅−=

ξσ

ξ

σξξ

where overshoot and settling time can be derived as functions of wn and ξ.

Using the same variables, wd and σ, we find a similar step response for B(s):

( )( ) ( ) ( )

⋅−⋅−⋅=→←

++⋅+

⋅= ⋅− tww

tweNtywswss

swwN

s

sBd

dd

t

nn

nn sincos1)(2

222

2 σξ

ξ σ

(2.4)

The integration property of the Laplace transform can be applied to equation (2.4) to derive theramp response of B(s). We may also recognize that y(t) represents the derivative of ϕosc(t) for theramp input, which is the oscillator instantaneous frequency: 2π.fosc(t), or Vtune(t).Ko.Therefore the time response of the 2nd order loop is simply fitted in its envelope requirementthrough a convenient choice of σ and wd, or ξ and wn .Next, the values of the filter components are evaluated with expressions (2.3) using ξ, wn and theopen loop gain, α.

Let us now consider the frequency domain envelope.Some aspects of the output spectrum may be obtained from the frequency response of the closedloop, B(jw).The oscillator output spectrum results from a combination of the PLL and VCO frequencyresponses. The PLL response is given by B(jw), and the input is the overall phase disturbancesdue to the PLL blocks, represented at the input of the phase detector.The 1st order filter, with a single integrator-zero, has a B(jw) close to a low pass filter (LPF),with a -20dB/dec attenuation for w>>wn , and a resonant peak inversely proportional to ξ.Hence the choices of wn and ξ, are a compromise between the time and frequency domainspecifications.Generally the resonant peak should be kept to its minimum, since it increases noise presence atthe output, and it indicates the system is approaching instability. Typically ξ is kept above 0.7.The choice of the bandwidth, wn , depends on many parameters. We have already seen the risetime and settling time in Vtune time response, and through the following chapters we tackle otherparameters, such as:

: roots of DB(s)

: damped natural frequency

: exponential envelope factor


• comparison frequency (fcp), requirement of spurious suppression, VCO free-running noiseperformance, maximum phase change for small frequency steps, and microphony and otherinterference robustness.

These questions belongs to quite different contexts, from the VCO output spectrum to a broadercontext including requirements from the application environment and from the demodulatorblock.At the moment we can state a 1st rule of thumb, common to synthesizer applications that use wn

in the range:

1030

cpn

cp ww

w≤≤

So far we have discussed ξ and wn choices for a unique, unchanging open loop gain (α) value.However we need to keep in mind that α can vary a lot in certain synthesizer applications andthis variation needs to be accommodated by the filter dimensioning.In these terms the 2nd order PLL is very convenient since it only imposes a minimum gain valuerelated to a minimum ξ, and elsewhere it is convergent.Nevertheless, its attenuation for high frequency (w>>wn) is often not enough to suppress thereference spurious to a satisfactory level. In addition the closed loop transfer B(s) for a 2nd orderloop leaves the phase noise contribution of the PLL visible within a -20dB/dec slope, which isequal to the slope of the VCO intrinsic noise. This means that a poor noise performance of thePLL would be visible even for frequencies above the closed loop bandwidth.

Indeed, most tuner synthesizers use 3rd order loop filters, resulting in a 4th order PLL.As we evolve towards higher order loops, the closed loop transfers are not so easily perceived asthe second order B(s), because their characteristic function, DB(s), is not directly factorable in 2nd

or 1st order polynomials.Thus, before discussing further aspects of the frequency envelope requirements we introducesome stability concerns in the 3rd and 4th order loops.Since we treat fairly simple systems with no zeros or poles in the right hand plane (on a S-plane),the stability may be unambiguously analyzed by the open loop frequency response parameters:phase margin (PhM) and gain margin (GM).

2.1.3 Third and Fourth Order Loops

Before we may examine the stability conditions of a 3rd or 4th order PLL, we need to introducethe corresponding loop filter impedance, and the resulting open and closed loop frequencyresponses.As mentioned in the previous section, most synthesizer applications use a 2nd or 3rd order loopfilter, in order to achieve the necessary out-of-loop rejection.These filters are implemented with additional resistors and capacitors, introducing one or twoextra poles at frequencies higher than the zero frequency. The pole at the origin is preserved tofulfill the steady error condition discussed in 2.1.2.

The following notation is adopted for the zeros and poles, frequencies and time constants:

ππ 22

1 1

11

z

zz

w

Tf =

⋅= : with fz1 and Tz1 , zero frequency [Hz] and time constant [s/rad];


ππ 22

1 2

22

p

pp

w

Tf =

⋅= and

ππ 22

1 3

33

p

pP

w

Tf =

⋅=

for the 2nd and 3rd poles, remembering that the 1st pole is a pure integrator with fp1= 0 Hz.

The resulting 3rd order filter is:

( )( ) ( )32

1

11

1)(

pp

z

TsTss

TsksF

⋅+⋅⋅+⋅⋅+⋅= (2.5)

A second order filter is obtained if either fp2 or fp3 tend to infinity. By convention our 2nd orderfilter has a finite fp2, and a Tp3 = 0.The two RC filter configurations below have approximately this transfer function as impedance:

Figure 2.4 3rd order Loop Filter Impedance

The filter impedances, Zs and Zp , are calculated as independent 2nd order terms, supposing thatthe approximations: Z3 >> Zp , and Z3 >> Zs are valid.These approximations are made to keep a transfer with real factorable poles, which greatlysimplify the filter design. Its accuracy holds for fp3 >> fp2 .

iii

( ) ( )

+⋅

⋅⋅+⋅+⋅

⋅⋅+==

21

21121

11

1

1

CC

CCRsCCs

CRs

I

VZ

in

Mp

;

( )( )211

211

1

1

CRsCs

CCRs

I

VZ

in

Ms ⋅⋅+⋅⋅

+⋅⋅+== ; and,

3333

1

1

1

ZCsCRsV

V

M

out

⋅⋅=

⋅⋅+=

Zp and Zs are composed of an integrator plus a lead-lag, zero-pole, pair.The single pole low pass filter (LPF), associated with Z3 , is often called a post-filter.A second approximation is made considering C1 >> C2 ⇒ C1 + C2 ≈ C1 , which simplifies ZF(s)in both cases to:

iii

The complete 3rd order, non-factorable, transfer is discussed in section 4.1.

R1

IinR3

Z3

Zp

C1

VoutC2 C3

VM

Z3 R3

Zs

Iin

Vout

R1

C1

C2C3

VM


( ) ( )33211

11

11

1)(

CRsCRsCs

CRs

I

VsZ

in

outF ⋅⋅+⋅⋅⋅+⋅⋅

⋅⋅+==

ZF(s) corresponds to F(s) for: Tz1 =R1 .C1 ; Tp2 =R1 .C2 ; Tp3 =R3 .C3 ; K = 1/C1 ; and, fp3 >> fp2 >> fz1 .

The spacing between fz1 and fp2 , is justifiable by the fact that the zero influence in pulling up thephase from its initial value (for w << wz) of -180° , is only visible if:

fz1 << fp2 ⇒ Tz1 >> Tp2 ; but since Tz1 / Tp2 = C1 / C2 ⇒ C1 >> C2

the open and closed loop transfer functions of the PLL with this 3rd order filter become:

( )( ) ( )321

21

11

1)(

pp

z

TsTsCs

TssH

⋅+⋅⋅+⋅⋅⋅+⋅

=α

(2.6)

( )( ) ( ) ( )1321

21

111

1)(

zpp

z

TsTsTsCs

TsNsB

⋅+⋅+⋅+⋅⋅+⋅⋅⋅+⋅

⋅=α

α(2.7)

Root locus and Bode diagram sketches showing PhM, GM, Mr, w3dB , and the closed loop rootasymptotes are plotted in figures 2.5 and 2.6.The closed loop magnitude Bode plot suggests a PLL phase transfer resembling a 3rd order LPF.This resemblance is confirmed by the root-locus that has for adequately high open loop gains, α,one pole that tends to the zero (being “cancelled”), and three others that tend to the asymptotes:

-180° + k.360° / n ; with n=3 , and k = 0, 1, 2.

The 3rd order LPF approximation for B(s) would have a transfer function, B3LPF(s) , in the form:

( ))(

12

1

)( 3

2

2

3

sB

w

s

w

sTs

NsB LPF

nn

p

=

+⋅⋅+⋅⋅+

≈ξ

(2.8)

where Tp3 is the post-filter equivalent pole, and the second order function in the ξ wn formrepresents the two other roots. These last two may be complex or real, depending on the valueof α.This simplified LPF form suggests a 1st stability boundary, analogous to a standard 2nd ordercharacteristic equation, expressed in terms of ξ and wn.

iv The boundary imposes a minimum ξvalue that may be represented in the rootlocus diagram.

iv

Later, in 3.4.1 , the LPF approximation is also used to evaluate the 3 dB closed loop bandwidth, indicated as fcl3dB

in figure 2.5.b.


Figure 2.5 4th order PLL: Open and Closed Loop Bode Plots

Figure 2.6 4th order PLL: Root Locus diagram

fig. 2.5.a

log( f ) [Hz]

fp3fp2

fz1

PhMmax

∠H(jw)[ ° ]

-90°

-180°

-270°

|H(jw)|[ dB ]

-60dB/dec

-20dB/dec

-40dB/dec

log( f ) [Hz]

fp3fp2

fz1

Open Loop : H(s)

fcl3dB

fcl3dB

log( f ) [Hz]

fp3fp2fz1∠B(jw)[ ° ]

-90°

-180°

-270°

|B(jw)|[ dB ]

NN-3dB

log( f ) [Hz]

fp3fp2

fz1

-40dB/dec

-60dB/dec

Closed Loop : B(s)

fig. 2.5.b

Res

Root Locus Ims

45°

ξ=1/√2

fz1

fp3 fp2


In figure 2.6, the dotted axes indicate a boundary of 21=ξ .

We observe that the gain value, α, has a minimum and a maximum limit value to ensure that thecomplex roots have a convenient damping, ξ. In fact for increasing α values, these two brancheswill finally cross the imaginary axis indicating an unstable behaviour.For a 2nd order filter, there are only three root branches. One is still directed towards the zero,and the other two tend to asymptotes parallel to the imaginary axis. Therefore the loop does notbecome unstable for increasing α values, but less and less damped as the equivalent ξ for thecomplex roots tends to zero.This same reasoning can be applied to the open loop Bode diagram, where a changing α valuecorresponds to shift the magnitude curve vertically, without moving the phase plot.This variation also shows a limitation for a minimum and a maximum value of α, in trying tokeep the phase margin above a suitable value.A classical security limit for a system phase margin is about: PhM ≥ 30° .

Figure 2.7 shows open and closed loop Bode plots with three different gain values:

• a centered value, αn , corresponding to the maximum phase margin for a 2nd order filter (or a3rd order loop);

• and two other gain values, geometrically equidistant to αn .

The curves plotted with dotted lines indicate the 3rd order loop transfer for the centered gainvalue, αn. The curves with solid lines correspond to the 4th loop transfer with the 3 α values.

The gain variation chosen is proportional to the lead-lag, zero-pole spacing, since,

21

21

21

min

max rr

r

n

n =⋅

=αα

αα

and r21 is defined as

1

221

z

p

f

fr = .

The filter calculation and the maximum supported gain variation are discussed in the followingsections. For the moment we observe some new parameters introduced in figure 2.7:

½ in the open loop diagrams:• wol: open loop zero crossing frequency or open loop bandwidth;• woln: central wol corresponding to the centered gain αn;

½ in the closed loop diagrams:• peak: resonant overshoot with respect to the close-in, low frequency, |B(jw)| value;• wpeak: frequency corresponding to the peak value;• w3dB: 3dB closed loop bandwidth, as indicated in figure 2.5.b.


Figure 2.7 Gain Variation X Stability in Bode Plots

Remembering that α = (Icp . Kvco)/ N, and that its variation represents the system functioningrange, we must adapt F(s) parameters to fit α ∈ [αmin , αmax] and to meet the frequency and timespecifications.In this example we observe that a gain variation of r21 implies quite significant variations ofbandwidth and PhM.Furthermore the centered gain value for the 3rd order loop, αn , is not really ideal for the 4th orderloop.Thus in the next sections we define successively:- a filter calculation algorithm for the 2nd order filter;- a centering compensation for the 3rd order filter;- and the relation between the zero-pole spacing and the maximum supportable gain variation.

fig. 2.7.a fig. 2.7.b


2.2 Algorithm for the Loop Filter Calculation

TV tuner applications very often work with quite large variations in the parameters: Kvco and N.Kvco variations are connected to the oscillator tank circuit sensitivity. In varicap based tankcircuits, the sensitivity is proportional to the varicap capacitance variation dC/dVbias.Typically this capacitance variation decreases for high Vbias values, i.e. for high values of Vtune,or at the high-end of the tuning range.N variation is directly proportional to the frequency variation inside the tuning range, pluseventually a multiplication factor to compensate changes in the reference divider ratio, R.Taking into account these two variations and one fixed Icp value results in the maximum α rangedemanded by the application.Furthermore the minimum α value is found at the high end of the VCO frequency spectrum,corresponding to the minimum Kvco and maximum N values and vice-versa for the maximum αvalue.In terrestrial applications, with a fixed Icp value, it is not rare to find α variations (αmax/αmin)higher than 100. In satellite applications they are typically to the order of 50.In the case of such large variations it is wise to use different Icp values to reduce the variation,especially if the output spectrum needs to be optimized for noise performance.However for stability reasons and user flexibility, the filter design should be centered, to ensurethe best application robustness, and as far as possible cope with all the gain variation range.

2.2.1 Nominal Design

Direct solving of the 4th order B(s) denominator with respect to fol or w3dB would be onerous andnot very enlightening with respect to the stability aspect or for an intuitive and quick filtercalculation method.Taking the phase margin aspect as a departure point and expressing it with respect to the ratios,pole frequencies divided by zero frequency, leads to a simpler approach. Let us define r31 andrecall r21 :

1

331

1

221 ;

z

p

z

p

f

fr

f

fr == ;

and express phase margin as a function of fol (wol /2π ), and the zero and poles frequencies.

−

−

=°−−∠=

=321

)180()(p

ol

p

ol

z

ololww f

farctg

f

farctg

f

farctgjwHPhM

ol

(2.9)

The maximum PhM point is somewhere between fz1 and fp2 , and intuitively we may say that iffp3 is distant enough not to have much influence on H(jwol), it should be equidistant to both fz1

and fp2 .


This idea can be confirmed solving: [ ] 0)( =fPhMdf

d

with the approximation wol << wp3

which result in: )()()( 21 pz TwarctgTwarctgwPhM ⋅−⋅≈

and maxPhM for 21

221121

r

frffff p

zpz =⋅=⋅= .

Choosing this maximum PhM frequency as fol , makes:

( )

+°−⋅=

31

2121 902)(

r

rarctgrarctgwPhM ol

(2.10)

The maximum phase margin point should be adjusted to correspond to the geometrical averageof the open loop gain range. So that gain variations towards minimum and maximum valuesimply phase margin variations around the maximum point.

( ) 1oln ===

n

wwjwHαα

[ ]α α α α α α∈ ∧ = ⋅min max min max, n

( )( )

1/111

121

12

oln11

supposing2312121

21

12

oln

oln

31

21

=⋅⋅

→+⋅+

+⋅

⋅=

>>>>

=r

Cwrrr

r

CwjwH n

rr

n

n

αααα

(2.11)

.;

;1

;

oln31

21333

21

11

1

2

1

22

oln

111

11

oln12

oln

211

wr

rCRT

r

CC

T

T

R

TC

w

CwC

TR

www

rC

pz

pp

nz

z

z

nn

⋅=⋅==⋅==

=⋅

==⋅

=⋅

=

⇒α

αα

(2.12)

The expressions above allow for the calculation of the filter components, following a maximumphase margin approach. They are valid for both 2nd and 3rd order filters.The positioning of fz1 and fp2 , the lead-lag controller, is made with respect to a 2nd order filter.The influence of the post-filter is taken into account in expressions (2.9) and (2.10) for the totalPhM, but it was not considered in the choice of the center or nominal gain value αn .A compensation for this gain centering, with respect to the PhM loss due to the post-filter, isdiscussed in the following section.


2.2.2 Robust design including Gain Variation and 3rd Pole compensation

We wish to investigate the maximum gain variation that we are able to accommodate withinconvenient PhM values.In fact expression (2.9) shows that for fixed filter parameters, the phase margin depends uniquelyon the open loop zero cross frequency, fol .Thus, we need to translate the gain variation in an open loop bandwidth variation, in order toassociate gain values with PhM values.Figure 2.8 gives an intuitive approach to the relation gain-bandwidth with respect to the filterdesign parameter, r21, i.e., the influence of r21 in the variation of wol with respect to α.

The sketches show two extreme situations, for large and small r21 values:

• for small r21 (approximately r21 < 10). The open loop slope stays practically unchangedaround the wol frequency, with a -40 dB/dec value, and wol changes are proportional tosqrt(α).

• for large r21 (approximately r21 ≥ 25), the slope around wol decreases to -20 dB/dec and wol

changes are proportional to α.

Figure 2.8 The influence of r21 in the gain-bandwidth variation

In other words, wol variation with respect to α may be expressed as:

( )21

ln

rf

no

ol

w

w

=

αα

(2.13)

with: ( ) 15.0 21 << rf ; and,

( )

( ) 1lim

5.0lim

21

210

21

21

=

=

∞→

→

rf

rf

r

r

log (f )[Hz]

log (f )[Hz]

w1 w2 w3

fp3fp2

fz1

|H(jw)|[ dB ]

sqrt(r21) → 1

fp3fp2

fz1

|H(jw)|[ dB ]

w1 w2 w3

sqrt(r21) >> 1α1 < α2 < α3 αi ↔ wi


A formal solution for f(r21) would require solving 3rd and 4th order polynomial equations.Using polynomial interpolation in numerical examples, we find a simpler form for f(r21), whichis quite accurate around the central point, wol/woln = 1.

21

211

1)(

rrf

+≅ (2.14)

The interpolation error is evaluated for PhM variations with respect to the central PhM value.For gain values implying a phase margin variation ≤ 20°, the bandwidth ratio is estimated with amaximum 5% error.We consider the error acceptable, and expression (2.14) is used to evaluate the following issuesconcerning the maximum supported gain variation and the filter recentering with respect to thepost-filter.We start evaluating the gain range corresponding to wol variations between wz1 and wp2 , for the2nd order filter.Table 2.1 shows some PhM values for r21 values commonly found in tuner applications.v

The PhM values are calculated at:- w = woln ;- w = wz1 , or w = wp2 , (with no post-filter we find the same PhM for both points).

maxPhM [°] PhM [°] (αn/ αmin)2

with wol=woln wol=wz1 or wol=wp2 αn =>wol=wolnr21

w/o post-filter w/o post filter αmin =>wol=wz1

f (r21)

10 54.90 39.29 20.71 0.760

15 61.04 41.19 30.18 0.795

20 64.79 42.14 39.08 0.817

25 67.38 42.71 47.59 0.833

Table 2-1 2nd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ]

The last column gives the gain range values corresponding to the open loop bandwidth variation:

( )21

1

oln

2

minmin

max

max2

min1 rfoln

pol

zol

w

w

ww

ww

=

=

⇔=

⇔=

αα

αα

α

α

The ratio αn / αmin is evaluated according to the f (r21) approximation ( equation (2.14) ).In fact for this α variation corresponding to wol=wz1 or wol=wp2, the bandwidth variation is afunction of a unique variable: r21 . It follows that:

v PhM values are calculated using expression (2.10) .


( )

21

21 1121

1

z1

2

min

max r

rfp r

w

w +=

=

αα (2.15)

For restricted domains of r21 ,we may use a linear estimation of equation (2.15), with anormalized error smaller than 5%:

[ ]

[ ]31,12;95.1

25,4;2

21

21

21

1121

21

∈=

∈=⋅≈+

rK

rK

rKr r LL

(2.16)

The r21 range between 4 and 25 covers quite well the values used in our tuner applications.

We consider that the minimum acceptable PhM value is 30°.So, combining the results of table 2-1 and expressions (2.15) and (2.16), shows that normalizedgain variations of (2.r21) can be accommodated within suitable PhM values.We are implying that r21 is chosen in relation to: the maximum PhM required, and, the gainvariation ratio.

We continue our analysis including the post-filter for the 3rd order loop filter.Table 2-2 brings some PhM values for sets of r21 and r31 parameters.The PhM values are calculated at:- w = woln with and without post-filter;- w = wz1 , and w = wp2 , with post-filter (different PhM values for the 2 points).

max PhM [°] PhM [°] PhM [°] PhM [°]

with wol=woln with wol=woln with wol=wz1 with wol=wp2

r21 r31

w/o post-filter w/ post-filter w/ post filter w/ post filter

r31 / r21

15 25 61.04 52.24 38.90 10.22 ♣ 1.67

15 40 61.04 55.51 39.75 20.63 2.67

25 30 67.38 57.92 40.80 2.90 ♣ 1.20

25 50 67.38 61.67 41.56 16.14 ♣ 2.00

(♣) : unacceptably low PhM values.

Table 2-2 3rd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ]

Phase margin differences for zero cross frequencies at wz1 and wp2 ,with post-filter, show theinfluence of wp3 in the PhM for gain values α > αn .A certain minimum r31/r21 ratio is necessary to keep a PhM ≥ 30° for a α range with αmax / αmin ≈ (2.r21) .

Actually, the effect of wp3 is already visible in the PhM of the centered bandwidth, woln, asshown in figure 2.7 and table 2-2 .


So, we wish to find a correction factor to recenter the open loop bandwidth around the maximumPhM for a given set of r21 and r31 parameters.Using a 1st order limited development for equation (2.10), enables us to find a simplepolynomial correction factor, rpf (post-filter factor). The estimated centered bandwidth is namedwolnpf , and the related gain value αnpf .

−=

31

2131

r

rrrpf

10 ≤≤ pfrKK (2.17)

pfr

ww olnpf

oln = olnpfoln ww ≥KK (2.18)

( )

+

⋅=

⋅=

2

111 21

21

11r

pfnpf

rf

pf

npfn rrααα npfn αα ≥KK (2.19)

Table 2-3 shows numerical examples of the post-filter recentering. The same values for r21 andr31 used in table 2-2 are recalculated after re-positioning the central open bandwidth around wolnpf

.

PhM [°]

for αnpf

PhM [°]

for αmin

PhM [°]

for αmax

∆ (PhM)

r21 r31 (rpf)0,5

wol = wolnpf wol=wolnpf /(r21)0,5 wol=wolnpf .(r21)

0,5

r31/r21

PhM(wz1) - PhM(wp2)

15 25 0.632 52.92 28.45 30.89 1.67 -2.44

15 40 0.791 56.00 34.18 30.34 2.67 3.84

25 30 0.408 55.34 20.49 43.41 1.20 -22.92 ♣25 50 0.707 62.11 32.83 32.03 2.00 0.81

(♣) : recentering approach fails.

Table 2-3 3rd order filter : Open Loop Bandwidth recentering

The recentering approximation is quite effective for (r31 / r21 ) > 1.6 ; but it cannot be used forsmaller ratios, since the accuracy is quickly degraded. vi

The bandwidth ratio (wolmax /wolmin), used in table 2-3 , is also equal to r21 ; so, the correspondinggain variation is approximately (2.r21) .Hence, we observe that recentered 3rd order filters can also cope with the normalized gainvariation, equal to (2.r21) , as far as the minimum ratio, [(r31 / r21)>1,6 ], is respected.In practice for (r31 / r21)< 1.6 , it is not possible to accommodate the normalized gain variationwith PhM ≥ 30° .

The limit (r31 / r21) ratio imposes a condition for the post-filter placement. vi

As a matter of fact for small (r31 / r21) ratios we also loose the accuracy of the filter transfer function, as discussedin section 2.1.2, and quantified in 4.1.1.


In fact, placing the post-filter pole is a compromise between PhM loss and spurious suppressionrequirement. The latter would ask to place it as close as possible to fp2 , but a minimum PhM, ina given α range, has to be preserved.

Once the post-filter pole position is chosen, R3 and C3 values may be directly calculated.There is a limitation concerning the R3 /R1 ratio, that is discussed further in section 4.1. For themoment let us keep in mind a practical boundary suggesting : R3 ≥ R1 .

In some applications we can also see an influence of the C3 value with respect to the resonanttank circuit of the oscillator. In these cases C3 , which appears as a parallel, parasitic capacitance,should be chosen to be as small as possible.So far so good, since these two practical boundaries tend to the same direction; for a given Tp3,we should choose a large R3 and a small C3. However as usual, there is an additional factorimposing a compromise.C3 and a series resistor connecting the loop filter to the tank resonator, form an LPF, whosefunction is to block the VCO signal leaking towards Vtune . Thus, we should keep a certainminimum C3 to assure the necessary RF attenuation.

2.2.3 Summary of steps and numerical example

The points discussed up to now suggest sequential steps for the loop filter calculation followingthe maximum phase margin approach, and the recentering correction:

(a) Evaluate the system open loop gain range, corresponding to the functioning conditions.Calculate the geometrical average (αn ) and the variation ratio, αmax / αmin .

: usually lower part of frequency range;

: higher part of frequency range.

If gain variations are too large, αmax / αmin ≥ 100 , look for possible compensations choosing aspecific Icp value for extreme cases.

(b) Choose parameters r21 and r31 taking into account PhM requirements and α ratio.

6.1;2

1

21

31

min

max21 ≥⋅≥

r

rr

αα

(c) Choose wolnpf with respect to the following parameters: switching time, spurious attenuationand adequacy to the noise performance of the VCO.

(d) Recenter αn with respect to (r31/ r21) ratio, for gain and cross frequency variation around αnpf

and wolnpf .

Forminmax ααα ⋅=npf

and

−=

31

2131

r

rrrpf

α

α

α

= ⋅

=⋅

=⋅

Icp Kvco

Ndiv

Icp Kvco

Ndiv

Icp Kvco

Ndiv

maxmax max

m in

minmin min

m ax


pfr

ww olnpf

oln = and

+

⋅=

2

1121

1r

pfnpfn r

αα

(e) Evaluate filter components using recentered woln , αn and expressions (2.12) .

In the case of a 2nd order loop filter, the same algorithm can be used ignoring the recenteringcorrection. So after choosing the central open loop bandwidth , woln in this case (item (c) ), weskip item (d) and calculate the filter components directly with expressions (2.12) .

The open loop bandwidth choice is the remaining compromise that is not completely discussed.As we mentioned in section 2.1.2. it depends on many parameters including circuit and systemrequirements. In chapter 3 we discuss a significant parameter, the phase jitter, concerning thetotal phase noise power in the carrier.

Finally we present a numerical example to illustrate the recentering plus the normalized gainvariation. In figure 2.9 the graphs use the same r21 and r31 values as in figure 2.7. :

r21 =25 ; r31 =50; and, 21

min

max 2 r⋅=αα .

Some other parameters are also indicated:

• wz1 ( o ) ; wolnpf ( * ) ; woln ( ) ; wp2 ( x ) ; wp3 ( x ) ;

• wpeak: frequency corresponding to the maximum value of closed loopmagnitude;

• w3dB: frequency corresponding to the DC value –3dB in closed loop magnitude;• peak: maximum value –DC value for the closed loop magnitude;

• dPhB(jw)/Foct : ( )[ ]

w

jwBphase

∆∆

with ∆w an octave frequency delta around wpeak .

Analogous to the 2nd order example in annex II-A, a steep phase change corresponds to a bigger overshoot.


Figure 2.9 Numerical example of robust filter design

We verify that the centering compensation is effective and that the normalized (2.r21) gainvariation is conveniently fitted.Therefore the polynomial approximations used in the development are accurate enough for ourapplications.The filter algorithm and the associated notation, through frequency ratios, proved to be quiteadequate to design and compare loop applications in a systematic and simple manner.They are continuously applied in the following chapters.

The numerical examples of figures 2.7 and 2.9 are calculated with a mathematical simulationsoftware, Matlab. The graphs are the output of executable files that are programmed withparametric inputs, being a flexible calculation tool.The tables are also an interesting design tool easily implemented in any spreadsheet software.

fig. 2.9.a Open Loop fig.2.9.b Closed Loop

Chapter 3 / Application Related Constraints 43

Contents:

3. Application Related Constraints 43

3.1. Reference Breakthrough ......................................................................................................................... 44

3.2. VCO Noise Representation and Phase Noise Units ................................................................................ 46

3.3. Optimum Closed Loop Bandwidth .......................................................................................................... 50

3.4. PLL Closed Loop Bandwidth .................................................................................................................. 523.4.1. w3dB derivation from BRL(s)........................................................................................................... 533.4.2. w3dB derivation from was ................................................................................................................ 59

3.5. Maximum Phase Jitter ............................................................................................................................ 61

3.6. Gain Stability Boundary.......................................................................................................................... 65

Figures:

Figure 3.1 BB noise representation of the VCO ........................................................................................... 47Figure 3.2 Free running VCO power spectrum density ............................................................................... 49Figure 3.3 PSD of a VCO locked by a PLL .................................................................................................. 49Figure 3.4 Peaking X Optimum Closed Loop bandwidth............................................................................ 50Figure 3.5 Combined Spectrum: PLL + VCO noise contributions ............................................................. 52Figure 3.6 Rootlocus for w3dB location.......................................................................................................... 58Figure 3.7 Rootlocus for was location............................................................................................................ 60Figure 3.8 Optimizing Total Phase Deviation .............................................................................................. 63Figure 3.9 Maximum SSB noise requirement .............................................................................................. 64

Tables:

Table 3-1 Comparing the denominators of B(s) and BRL(s) ....................................................................... 54Table 3-2 Rootlocus approach for wcl : parameters of BRL(s) ..................................................................... 58Table 3-3 Gain Stability Boundary .............................................................................................................. 65Table 3-4 Maximum Normalized Gain Variation ...................................................................................... 67

3 Application Related Constraints

So far we discussed the PLL system quite separate from its application. In this chapter we studyparameters concerning the spectral purity of a VCO locked by a PLL. The parameters concernthe adequacy of the closed loop bandwidth to the noise performance of the VCO, and thesuppression of deterministic interference at fcp .The filter calculation method is extended to discuss the maximum phase deviation in thesynthesized carrier, and an example of a satellite application is developed.


This chapter starts to analyze the phase noise contents of the carrier output of the PLLsynthesizer. At this point, it is a system level analysis, that considers two single noisecontributions: one for the VCO and another for the ensemble of the PLL blocks.The sources of noise, that can be either deterministic or random, are progressively presented inchapters 4 and 6. Later in chapter 7, these noise specifications are translated to a circuit leveldescription.In order to minimize the phase noise in the spectrum of the synthesized carrier, we should beable to choose the closed loop bandwidth with respect to the noise performances of the PLL andthe VCO. The calculation algorithm for the loop filter is then extended to take into account thespecification of a closed loop bandwidth.The total phase deviation is introduced as a figure of merit for the noise contents in the carrierspectrum. A numerical example for a satellite frontend exemplifies the calculation method. Inthis example, we calculate a loop filter that guarantees a total phase deviation lower than 2° forthe entire range of normalized gain variation (2.r21).

3.1 Reference Breakthrough

Reference breakthrough, or spurious raysi, is a FM interference found in the VCO output atfrequency offsets of ±fcp. The value of H(jw)w = 2π.fcp represents the rejection by the loop filterof the fundamental component of the input current pulses. The fcp component of the loop filteroutput generates the FM modulation of the VCO. The spurious requirement should be met byproviding the necessary attenuation of the fcp component.

A first cause of the reference breakthrough is leakage currents. The leakage currents causevariations in the value of Vtune . These variations are compensated by the feedback action of thePLL, which provides every Tcp the average lost charge. Practical examples of leakage currentsare: the reverse current of the varicap (from the oscillator resonant circuit); in the case of active loop filters, the amplifier input current; an unwanted current of the charge pump in the off state; a discharge current in the loop filter impedance, proportional to the residual transient current.

This effect is relevant for large bandwidth (bw) filters.ii

A second cause is the transient mismatch of the sinking and sourcing pulses of the charge pump.When in lock both sources are switched on during the reset interval. This is donein order to avoid dead-zone problems (see chapter 1). The sinking and sourcing pulses havedifferent rise and fall times so the combined current output is not null, and it presentscomponents at fcp and its harmonics.

i Sometimes the name spurious rays is also used for other deterministic interference found in the VCO output. These

interferences are originated by the operation of different integrated blocks, and they contaminated Vtune by parasiticcoupling.ii

For a charge pump output and resonant circuit input with high impedance, the loop filter discharge is proportionalto the time constant Tp2 . In large bw filters this discharge causes significant changes in Vtune during a Tcp interval.The time response of the filter is further discussed in chapter 5.


Once we evaluate the total leakage current and mismatch we can calculate the correspondingspurious level. The spurious level is proportional to the current that compensates these effects.For the calculation we do two approximations. First we assume that the frequency content of thecompensation current is concentrated at fcp. Second we use the narrow band FM approximationas the phase deviations are small.Let us suppose a single tone modulating signal m(t), and an FM modulated carrier s(t):

[ ]

⋅⋅⋅+⋅⋅=⋅+⋅⋅=

⋅⋅=

∫cp

cpmcccc

cpm

f

twAKvcotwAdttmKvcotwAts

twAtm

)sin(cos)(2cos)(

)cos()(

π

We define the peak phase deviation β: cp

m

f

AKvco ⋅=β ;

and apply the FM narrow band approximation for β << 1 rad , which gives:

( ) ( ) ( ) ( )[ ]

+−−⋅+⋅⋅= twwtwwtwAts cpccpccc coscos

2cos

β(3.1)

The leakage current component at fcp represents a voltage amplitude in the VCO input of:

cpwwfilterleakagem jwZIA

=⋅= )(

The resulting SSB spurious rays measured with respect to the carrier amplitude becomes:

⋅=

⋅=

2log20

amplitudecarrier

componentfmodulatedFMSSBlog20 cp β

As

or

⋅

⋅⋅⋅=

cp

vcocpfilterleakage

f

KwZIAs

2

)(log20 (3.2)

Equation (3.2) is a 1st order evaluation of the sidebands at the reference frequency. It is anoverestimation because we assumed all the power of the compensation current concentrated at fcp

. In practice, the accuracy of the calculation of the spurious rays is limited by the evaluation ofthe Ileakage value.

The leakage currents that depend only on the Vtune value are easier to evaluate, (in locked modeVtune is practically constant). It is the case of the varicap reverse current (componentspecification), the amplifier input current, and the charge pump off current.The residual transient current depends on the circuit design, and it is easier and more accurate touse a mixed circuit and behavioural simulation. For instance the mismatch between sinking andsourcing may be evaluated with a PLL behavioural model including a circuit level description of


the charge pump.iii The resulting spurious rays may be calculated with the value of Ileakage andequation (3.2), or directly applying an FFT (fast Fourier transform) at the simulated Vtune signal.

The PLL behavioural model for time domain simulations is discussed in chapter 7. In this modelwe may add other causes of spurious rays, such as supply contamination and substrate coupling.In chapter 4 we discuss the role of the loop amplifier in the transmission of supply perturbations.

The narrow band treatment used above is valid for any phase deviation that respects themaximum peak deviation boundary, ∆ϕmax << 1rad. For perturbations exceeding this modulationindex, or when a better accuracy is required, a more complete description should be used,including other harmonic components.For the moment we use the narrow band approach to discuss rather small phase disturbances,such as random noise sources. We start with a global approach that considers the optimization ofthe VCO spectrum for given VCO and PLL noise performances. Later in chapter 6, themechanisms of phase noise generation are described, and in chapter 7 the simulation tools thatrelate noise and design are discussed.The following section introduces the units used to characterize the oscillator phase noise, and weproceed with the choice of the PLL bandwidth optimizing the phase deviation content.

3.2 VCO Noise Representation and Phase Noise Units

The spectrum of a VCO locked by a PLL is composed of two zones. One is called in-loop andthe other out-of-loop. These names refer to the zones of the VCO output which are dominated bythe PLL input noise or by the VCO intrinsic (free-running) noise.Roughly the flat part of |B(jw)| corresponds to the PLL determined, in-loop zone. The–60dB/dec region of |B(jw)| , where the intrinsic VCO noise (with –20dB/dec) takes over, is theout-of-loop zone.

In reality all input signals, noise or deterministic, have finite power and have a band limitedpower spectrum density (PSD). However, in a first approach let us consider two white noisesources representing the VCO and PLL noise contributions. The total noise contribution fromthe different PLL blocks is concentrated at the phase detector input, and we name it NPLL .

In the base-band (BB) phase representation adopted in chapter 2, the VCO is represented by anintegrator with sensitivity Kvco. The BB representation makes a frequency conversion of theBPF behaviour of the VCO in an LPF behaviour. In this context the VCO spectrum may bemodeled by a white noise voltage source at the integrator input.

iii

Another method of direct evaluation is rather lengthy, since we need first to find the correct phase differencebetween the phase detector inputs that corresponds to an average constant charge, at Vtune. After that, the currentdifference, Tcp periodic signal, is compared to a square or triangular pulse, and the power fraction at fcp is calculated.


Figure 3.1 BB noise representation of the VCO

⋅

⋅=⋅

⋅=

Hz

Vrms

Kvco

ffL

Kvco

f

bw

v offsetfdBLoffsetoffset

offsetnvco2

10

222)(

102)(2 (3.3)

The part of the VCO spectrum with a –20dB/dec slope is correctly represented by a whitevoltage noise source. Near the carrier, a free running oscillator presents a phase noise with higherroll-off, due to the presence of 1/f (flicker) noise sources. In figure 3.1 this is indicated by thecorner frequency frecover , which points to the intersection of the white and flicker noisecontributions. So a more complete description, which would be valid for offset frequenciesbelow frecover , needs to include poles and zeros in the vnvco expression, to represent the differentslopes in the output spectrum.

In the case of a large bandwidth PLL, the voltage noise source, vnvco, does not need to befrequency shaped. The part of the spectrum with the -30dB/dec roll-off is hidden by the PLLnoise.In equation (3.3) the factor 2 relates this base band representation to a single-side band (SSB)measurement, L(f). L(f) is SSB phase noise defined by:

curve under the area total

fat bw Hz 1in area

power signal total

n fluctuatio phase to duepower SSB)( offset==offsetfL

or

=≈

+=

∫∞ HzCNRP

fP

dffPP

fPfL

carrier

offsetnoise

noisecarrier

offsetnoiseoffset

11)(

)(

)()(

0

(3.4)

when expressed in dB it equals

[ ]

=

Hz

dBcfLfLdB )(log10)( ; dBc ⇒ dB with respect to carrier power.

ϕosc

VCO output spectrum

vnvco2

[Vrms2/Hz]

s

Ko

~ frecover

VCOPSD

[W/Hz]

fosc

log (foffset)

-20dB/dec

-30dB/dec


At this point we take a filtered portion of vnvco , and analyze it as a deterministic signal thatmodulates the VCO. Using equation (3.1), and an ideal filter with a bandwidth of 1Hz around fm

, we obtain:

( ) [ ]Vtwvtm mmnvco ϕ+⋅⋅= cos2)( ;

with a peak phase deviation:m

nvcovco

f

vK ⋅⋅=

2 β ;

and an oscillator phase: ( ) [ ]radtwtwt mmcosc ϕβϕ +⋅+= sin)(

The base-band representation of the oscillator phase is given by:

∫⋅⋅=⋅− dttmKtw vcocosc )(2πϕ

which corresponds directly to the block diagram in figure 3.1. We may represent the phasedeviation caused by m(t) as two sidebands at offset frequencies of ±fm , with an amplitude valueequal to Ac.β /2 , or:

⋅⋅

⋅=

⋅==

⋅

⋅

=m

nvcovcomdB

c

c

mf

vKfL

A

A

fL2

log202

log20)(4

2

21

2)(

2

2

2

βββ

K

Sϕ(f) is the double side band (DSB) phase noise, or the mean square phase fluctuations power. Itmay be seen as the BB equivalent of L(f) :

[ ] dBfLrad

SfSHz

radfLfS dBdBoffset 3)(1

log10)(;)(2)(2

2+=

⋅=⋅= ϕ

ϕϕ

(3.5)

Expression (3.5) holds when the sideband amplitudes are evaluated by the narrow bandapproach. Otherwise a significant amount of the BB power is scattered in higher harmonics of fm

around the carrier.For decreasing values of fm , the phase deviation increases and the narrow band approximation isno longer valid. This condition indicates the minimum frequency offset for which the VCO canbe represented by a linear phase model. Once more, this limitation is hidden by the PLL in-loopregion, since the PLL noise contribution appears as a phase and not as a frequency modulatingsignal of ϕosc.

iv

Figure 3.2 illustrates the phase noise units in the side band and base band representations of thefree running VCO spectrum.

iv

A more detailed discussion of the spectrum differences between PM and FM appears in chapter 6 .


( v )

Figure 3.2 Free running VCO power spectrum density

The PLL noise contribution, NPLL , is a phase jitter in rad/sqrt(Hz). Figure (3.3) shows BB andDSB representations of the spectrum of a VCO locked by a PLL. The noise contributions fromNPLL and vnvco are indicated separately. The level of the sidebands corresponds to a unitarynormalized carrier level, or to the phase deviation values.

The closed loop transfer function, B(s), analyzed in chapter 2, determines the transfer of NPLL tothe output spectrum. In a similar manner we may define Bvco(s) as the closed loop transferfunction of ϕosc / vnvco . Since the feedback path is the same for B(s) and Bvco(s), they have equaldenominators.

( ) ( )( ) ( ) ( )1321

2

321

111

11

)(

)()(

zpp

ppovco

sTsTsTCs

sTsTCsK

sFK

sBsB

+⋅++⋅+⋅⋅+⋅+⋅⋅⋅

=⋅

=αϕ

(3.6)

Figure 3.3 PSD of a VCO locked by a PLL

v The DSB graphs abscissas need to be split in two regions if we want to keep the logarithm scale with respect tofoffset .

4

2β

1

|Sϕ(f)|[rad2/Hz]

BB representation

2 . L(foff1) = Sϕ(foff1)

foff1

foffset

log(f-fc)

L(foffset)

foffset

8

2 β⋅cA

2

2cA

|Posc(f)|[W/Hz]

fosc f

DSB representation

log(f-fc)

Npll+3dB

20log(N)

|Sϕ(f)|[rad2/Hz]

BB representation

log(f)

free-running VCO_Sφ(f)

from Vnvco

from Npll

1(Npll)2 . |B(f)|2

-60dB/dec

-20dB/dec

log(f-fc)log(f-fc)

|Posc(f)|[W/Hz]

fosc

DSB representation

(vnvco)2/2.|Bvco(f)|2


Bvco(s) has an overall band pass filtering behaviour. This can be represented by an approximatetransfer function Bvco_BPF . It is a simplified function resembling B3LPF(s) (equation (2.8) ), thesimplified LPF description of B(s).

αξ⋅

+⋅+

⋅⋅=

12

)(

2

2

1_

sww

s

CsKsB

nn

oBPFvco

(3.7)

Comparing Bvco_BPF and B3LPF , we notice that they both have a second order polynomial in thedenominator, written in a standard ξ and wn form. We choose this common notation to indicatesimilar roots in the two functions. In numerical examples, we verify that the wn in Bvco_BPF isslightly larger than the one in B3LPF .

The interest of these simplified forms appears when we are minimizing the noise content of theoutput spectrum. Figure 3.3 shows an ideally smooth intersection between the two zones of thespectrum, the in-loop one and the out-of-loop one. Nevertheless, the dominant noise in each ofthese zones originates from independent noise sources, and in practice the feedback bandwidthand gain determine whether the intersection is smooth or bumpy.

3.3 Optimum Closed Loop Bandwidth

In order to minimize the noise of the output spectrum, we need to match the PLL closed loopbandwidth (fcl) with the intersection frequency, where the noise contributions from Npll and vnvco

cross each other. Mismatches result in additional peaking or excessive PLL noise, as drafted infigure 3.4.We use again the term peaking to refer to the spectral overshoot. This mismatch peaking adds tothe low phase margin peaking seen in chapter 2. In the measurements, an overall peaking isobserved, and it is due to both causes.Thus, we need to know the PLL and VCO noise performances in order to choose an adequatefeedback bandwidth, and afterwards center a stable filter around this bandwidth.

Figure 3.4 Peaking X Optimum Closed Loop bandwidth

additionalpeaking

Ideal closedloop bw

fosc

from Vnvco.

from Npll

excessivePLL noise

Ideal closedloop bw

foscfrom Vnvco.

from Npll


The ideal feedback bandwidth is indicated in the figure above. The spectrum has a minimumjitter content when we center a loop filter around this bandwidth. Unfortunately this bandwidthwill correspond only to the central gain value, and we know that synthesizers work with a largerange of gain variation. The choice of the bandwidth should take into account the optimization ofthe phase jitter over the entire range of gain.

We start with a numerical example showing the spectrum of a VCO locked by a PLL, and theseparated PLL and VCO noise contributions for a set of different gain values. The figure isdivided into four parts:• fig. 3.5.a : shows the total output spectrum plus isolated PLL and VCO noise

contributions, for the centered gain value αnpf . Three asymptotes areadded in dotted lines. They correspond to the VCO free-runningbehaviour, the Npll DC transfer value (20.log[N]), and 3dB below the DCvalue.vi

• fig 3.5.b: total output spectrum for gain values varying within a range of (2.r21)around αnpf .

• fig 3.5.c and d: detailed contributions of PLL and VCO noise for the curves in part b.

The same symbols from figure 2.9 are used to indicate wz1 ( o ), wolnpf ( * ), woln ( Zp2 ( x),wp3 ( x ). NPLL , also called synthesizer noise floor, is indicated in figure 3.5.d by a dotted line.

The numerical values used for these graphs correspond to the performance of low noise satellitePLL and VCO:

HzdBcKHzL

GHzFN

MHzHzdBcN

vco

vco

pll

/100)100(

5.11500

1Ffor /154 cp

−=

=

=

=−= K

Let us define fi as being the intersection frequency for PLL and VCO noise asymptotes, asindicated in figure 3.5.a:

)log(20log20)( NNf

ffL pll

i

offsetoffsetvco ⋅+=

⋅+

−⋅+−

⋅= 20

)()log(20

10offsetvcopll fLNN

offseti ff (3.8)

In order to optimize the output spectrum we want to center the closed bandwidth fcl around fi .But so far we only specified the open loop bandwidth fol, used in the loop filter calculation.Hence, we seek now a relationship between the open and closed loop bandwidths for a gainrange around the centered value αnpf .

vi

The asymptotes are repeated in the other subplots (3.5.b/c/d) to simplify the comparison among the curves, whichare plotted in different scales.


Figure 3.5 Combined Spectrum: PLL + VCO noise contributions

3.4 PLL Closed Loop Bandwidth

The simplified transfer functions B3LPF and Bvco_BPF , showed that the PLL and the VCO noisecontributions have a similar closed loop bandwidth, depending on wn and ξ . This bandwidthcorresponds to the LPF cut-off frequency for NPLL, and to the central frequency of a BPF forvnvco.

Later on, we assume that both transfer functions have an identical closed loop bandwidth, whichis determined by the zero and poles of the loop filter, and by the loop gain α . Therefore, we needto relate the open and closed loop PLL bandwidths. The closed bandwidth must approach fi , butit is the open loop bandwidth that is used for the filter calculation.

Let us consider w3dB as the closed loop bandwidth. First we do a quantitative approach of theratio w3dB/wol , with numerical evaluations. After that, two analytic methods are discussed.

a b c d e

fig. 3.5.a fig. 3.5.b

fig. 3.5.c fig. 3.5.d


Numerical evaluations of the ratio w3dB/wol , for a centered gain variation of (2.r21) aroundwolnpf, show that this ratio is contained in a limited range, when we assume that the r21 and r31

values belong to the ranges indicated below. The limiting ranges include the typical valuesencountered in synthesizer applications. The results and conditions are:

[ ][ ] 28.063.1

6.1

,16

50,103

31

21

31

21

±=⇒

≥∧

∞∈∈

ol

dB

w

w

r

r

r

r

In chapter 2 we saw that the open loop bandwidth wol varies around wolnpf . Thus it is likely thatw3dB, which is proportional to wol , and slightly larger, varies around a value close to woln .The difficulty to evaluate w3dB (more precisely) comes from the fact that the denominator of theclosed loop transfer function DB(s), has complex roots with a variable damping. This implies avariable peaking and a variable w3dB/wn .

The rootlocus representation of B(s) may be used to derive two formal expressions for w3dB .These expressions are derived in sections 3.4.1 and 3.4.2 using some algebra puzzles.The overall result is already announced in the paragraph above.Closed loop bandwidth varies as much as open loop bandwidth and we need some applicationcriteria to define how to accommodate this variation. An example of an application criterion fordigital phase modulations is presented in section 3.5 .

3.4.1 w3dB derivation from BRL(s)

This first method compares the closed loop transfer B(s), with a polynomial that arises from therootlocus representation. Subsequently, it deduces the minimum and maximum boundaries forwn and ξ, and relates these parameters to w3dB . Numerical evaluations are used to validate themethod.

The polynomial BRL(s) is equivalent to B(s). BRL(s) has 4 roots agreeing with the branches of therootlocus presented in figure 2.6.

( )( ) ( ) ( )[ ]1321

21

111

1)(

zpp

z

sTsTsTCs

sT

N

sB

+⋅++⋅+⋅+⋅

=α

α

(3.9)( )

( ) ( ) αξα

⋅

++⋅+⋅+

+⋅=

12

11

1)(

2

2’1

’3

1

nn

zp

zRL

w

s

w

ssTsT

sT

N

sB

By inspection we verify that B3LPF (eq. (2.8) ) is a simplified version of BRL , with the followingapproximations: Tz1’ → Tz1 and Tp3’ → Tp3 .

N

sB

N

sB RL )()( =


The transfer function BRL states that for any given α, at least two roots are real. The two othersare either real or complex depending on the value of ξ . The assumption of two real roots agreeswith the rootlocus diagram of figure 2.6.Furthermore the diagram shows that the position of the real roots may be specified within limitedfrequency ranges. In our notation, the real roots correspond to the time constants Tz1’ and Tp3’.We define γ and β, as the ratios between the time constants, with:

103

’3 ≤≤= ββ KK

p

p

T

T and 10

1

’1 ≤≤= γγ KK

z

z

T

T .

We expand the denominators of B(s) and BRL(s), and compare the coefficients of the 4th and 1st

order terms of s, finding the following equalities:

term DB(s)/α DBRL(s)/α

4th

s42oln

231

214oln31

21

wwr

r

wr

r

n

n

⋅⋅⋅⋅

=⋅

⋅γβ

αα

1st

s1

nww

r

w

r ξγ 2

oln

21

oln

21 +⋅

=

Table 3-1 Comparing the denominators of B(s) and BRL(s)

from 4th order terms:2

1

21oln

⋅⋅⋅⋅= rww

nn γβ

αα (3.10)

from 1st order terms:( )γξ

−⋅⋅=

1

2

21

olnr

ww n(3.11)

We may use the last two expressions to derive the minimum and maximum boundaries of wn .Expression (3.10) contains variables that belong to closed and known ranges. We use it to derivethe maximum limit of wn.

[ ]

[ ] [ ]

→→→

↔∈∧∈

=

⋅⋅

⋅∈

1

1maxwith

1,0 1,0

,2,2

max

maxmin21

21

γβ

αα

γβ

αααα

α

n

npfnpf

w

rr


so: ( ) 41

21

21

oln

21

21oln

11

max

limmax rwrwwnn

n

⋅=

⋅⋅⋅⋅<

→→→ α

αγβαα

γβ

αα

but since 21max 2 rnnpfn ⋅⋅<⇒≥ αααα

the maximum of wn becomesvii: ( ) ( ) ( )19,12max 24

12

1

21oln ⋅=⋅⋅< pn wrww

(3.12)

In order to find the minimum of wn with expression (3.11) we need to find the minimumoccurring value of ξ.viii

After the recentering procedure outlined in chapter 2, we observed that a gain variation of 2.r21

can be covered with a minimum phase margin of 30°, for r31 ≥ 1.6 . r21 .So we may look for a relationship between ξ and the phase margin parameters to specify theboundary of the variation of ξ.

Observing BRL(s) and the rootlocus, we may suppose that the phase margin is mostly influencedby the pair of complex roots which are represented by the 2nd order polynomial in ξ and wn.Therefore we may rely on the analysis of the 2nd order LPF to derive the relationship between thedamping factor ξ, and the open loop phase margin PhM. It holds that

++−=

142

2

42 ξξ

ξarctgPhM (3.13)

Using equation (3.13) we evaluate the minimum value of ξ corresponding to a 30° PhM.

( )°==⇒°= 6.15sin269.030 ξPhM (3.14)

Finally the minimum boundary for wn is calculated substituting (3.14) in equation (3.11):

[ ]

[ ] ( ) 1

21

oln

21

oln

269,00

54.054.01

2limmin

1,0

1,269.0

zn wr

w

rww ⋅=⋅=

−⋅⋅>

∈

∈

→→ γ

ξ

γ

ξ

ξγ

(3.15)

The next step concerns the relationships between ξ, wn and w3dB . We continue to work with thehypothesis that the two complex roots are largely determining B(jw) around wn . Hence, we mayuse the following expression deduced from the standard 2nd LPF:

vii

A more rigorous treatment should take into account the ratio αn/αnpf , related to the recentering procedure, seen inchapter 2. Later in this section a numerical example illustrates the difference.

viii The maximum ξ value is 1, corresponding to α values with 4 real roots.


( )[ ] 21

23 221 +−+−= ξξξn

dB

w

w (3.16)

Combining (3.16) with our restricted domain of ξ , we find:

[ ] [ ]1,404.11,269.0 3 ∈⇒∈n

dB

w

wξ (3.17)

The extreme values of wn , occurring for αmax and αmin , both correspond to cases where the PhMequals 30°, or ξ equals 0.269 , or:

404.1

3 =n

dB

w

w

The combination of the minimum and maximum boundaries of wn and this ratio gives the desiredrange of w3dB:

[ ] 23121maxmin 67.175,02.154,0, pdBzpnz wwwwww ⋅<<⋅⋅<<⋅∈ KKααα

The geometrical mean of the range of w3dB equals: ( ) oln3 w1.12 mean geom. ⋅=dBw

The maximum value of wn was overestimated in equation (3.12) because we neglected the ratioαn / αnpf

ix. A numerical application correcting this maximum boundary for given values of r21

and r31 is presented below:

for:

[ ]

⋅<<⋅

↓

⋅<<⋅

⇒

⋅=∈

=

⇒

==

231

21

21min

maxmaxmin

2

1

npf31

21

36.175.0

97.054.0

2 with ,

23.150

25

pdBz

pnzn

www

www

r

r

r

ααααα

αα

Here, the geometrical mean of the range of w3dB is: ( ) oln3 w1.01 mean geom. ⋅=dBw

Thus the range of w3dB centers approximately around wol . With this result we combine the openand closed loop specifications for the spectrum optimization.Another possibility to relate the close loop transfer with the values of ξ is found in phase Bodeplots. This relationship was presented numerically in figure 2.9, by dPhB, the phase variation fora frequency delta of one octave around wn .

[ ] [ ] [ ]2

))((2

2))(())(()( nnnoctave

wjwBph

dw

dwwjwBph

dw

dwjwBphase

dw

djwdPhB ⋅=

−⋅=∆⋅=

(3.18)

ix

In order to introduce αn / αnpf factor, we need to know the ratio r31/r21 . Expression (3.12) is a rougher boundaryestimation not depending on r31 value.


For our faithful 2nd order LPF, dPhB becomes:

[ ] [ ]

octave/149)(max269.0for

40rad

2

1

2

1)(

min °−=⇒==

°−=⋅

−=⋅⋅−=

jwdPhB

w

wjwdPhB n

n

ξξ

ξξξ

In this case, the analogy to the 2nd order LPF is accurate for 3rd order loops, but not for 4th orderloops, where the post-filter has a significant influence in the phase variation around wn .Hence we stick to the rootlocus criterion to center the closed loop bandwidth .

Figure 3.6 illustrates the rootlocus for different values of r21 and r31.The grid indicates natural frequencies and damping arches (ϕ = arcsin ξ ). A set of gain valueswithin the usual (2.r21) interval is chosen, and the roots corresponding to these gain values areindicated by delta signs (∆) .

The plot is magnified around the origin of the s-plane, so that the damping of the complex rootscan be easily visualized. We verify that all the roots signaled by a ∆, are effectively contained inthe area corresponding to arcsin(ξ)>15° , or ξ >0.26 .

Grid:[ ]

[ ]

°°°°°=

∗=

15,30,45,60,75arcsin

8,4,2,1olnpf

ξ

wwn

Gain values signaled by a delta (∆): ( ) ( )

⋅⋅⋅= − 5.0

215.0

21 2,,1,2 rrnpf

nnpf α

ααα .

In figure 3.6.b we observe that a small value of r21 limits the maximum value of ξ . This resultagrees with expression (2.10), concerning the maximum phase margin.The 4th branch follows the real axis from –wp3 towards -∞ .The values of β, γ, ξ, and wn , from the expression of BRL(s), are evaluated for the left rootlocusdiagram with: r21=25 and r31=50 .In table 3-2 the columns coloured gray correspond to the α values indicated by a ∆ signal infigure 3.15.a .


Figure 3.6 Rootlocus for w3dB location

α( ) 2

1

21

npf

2 r⋅

α( ) 4

1

21

npf

2 r⋅

α αnpf αn ( ) 41

21npf 2 r⋅⋅α ( ) 41

21npf 2 r⋅⋅α

’3

3

3

’3

p

p

p

p

w

w

T

T==β 0.991 0.978 0.948 0.927 0.890 0.802

’1

1

1

’1

z

z

z

z

w

w

T

T ==γ 0.0415 0.0442 0.0547 0.756 0.879 0.958

olnpfw

w n x 0.196 0.328 0.585 2.65 3.71 5.99

min (ξ) 0.325 0.542 0.958 1.00 0.676 0.275

arcsin [min (ξ) ] 19.0° 32.8° 73.3° 90.0° 42.5° 15.9°

Table 3-2 Rootlocus approach for wcl : parameters of BRL(s)

x wn for the pair of complex roots. For α values where all roots are real, we take an average of the two roots which

are the closest to the complex branches.

Figure 3.6.a Figure 3.6.b


3.4.2 w3dB derivation from was

This second method gives some further insight into the rootlocus representation. However it islimited to a single gain value.The asymptotes of the rootlocus for increasing gain values are given by radial lines, which havea known phase and origin, φl and was .

0

1

1

1)(

)(10

)(

)(1)(1

lim

lim=

+

+=

+⋅

⋅+ →=⋅

⋅+=+ −−

∞→

∞→ mn

as

mn

asF

F

wandF

F

w

s

w

ssN

sN

sDs

sNsH

ααα α

(3.19) (3.20)

where n : order of the denominator of H(s);m : order of the numerator of H(s).xi

Expressing the asymptotes in the polar form ( ljo eRs Φ⋅= ) and solving the phase condition for

(3.20), gives:

( )( )[ ]1,0

;360180

3601801

−−∈∧∈

−°⋅+°=Φ

Φ⋅−=°⋅+°=

−

∞→=

−

mnlZl

mn

l

mnlws

phasel

l

wss

mn

as o

For n > m+1 , we can apply the following expression, that is derived from(3.19) and (3.20),comparing the coefficients of order sn-1 . It follows that:

LHP in the zerosfor z with _ H(s) of sz:

(LHP) plane-S theof sideleft in the

polesfor p with _ H(s) of poles:

i

i

ii

ii

iias

zeroz

pp

mn

zpw

=

=

∴−−

= ∑ ∑

In our case (n-m) = 3 , φl = 60° ; 180° ; 300° , and

[ ]

+⋅ →−+⋅=

−+⋅

=>>

>>21

3121oln

1r and1rfor 3121

21

oln2121

3121oln

r31

r33

1

31

21

rrwrr

wrrrrw

was

xi

There are (n-m) centrifugal asymptotes because m root branches tend to the m zeros of the open loop transferfunction. In fact for an increasing gain there are two possibilities of satisfying the closed loop characteristic equation(3.19):

( ) −∞→⋅→sN

sDssN

F

FF

)(,0)( . The second case supposes n > m and w → ∞ .


We use was to define a LPF transfer function, Bas(s), with three real poles at was .A rough estimate of the closed loop bandwidth for α ≈ αn is the frequency of 3dB attenuationfor |Bas(jw)|, named w3dB-as :

( ) ( )

( )

2321

31

2321

31

21

3121oln3

23

2

3

3

3

4.06,1r

5.02r

for examples numerical r6

51,0

2

1

1

1

1

1

pasdB

pasdB

asasdB

as

asdB

asdBas

as

as

wwr

wwr

rrwww

ww

N

jwB

wsN

sB

⋅==

⋅==

⋅+

⋅≈⋅=

=

+

=

+=

−

−

−

−

−

K

K

KK

The figure below shows a rootlocus in full scale, with the asymptotes for large gain and was . Theroots corresponding to αmax and αmin are indicated with ∆ signals.

Figure 3.7 Rootlocus for was location


We would like to compare the results of the two methods for the estimation of w3dB .In the 2nd method w3dB was estimated for a gain of αn , and in the 1st method the centered valuecorresponds to αnpf . So before the comparison we need to choose values for r21 and r31 andrecenter w3dB_as with respect to αn/αnpf .

olnoln_3oln2_331

21 8,15,25,25,050

25

npf

wwrwwwwr

rpfasdBpasdB

n

⋅=⋅⋅=⋅=⋅=⇒==

ααK

The 2nd method results in a larger value of w3dB than the 1st one. Using this larger value thespectrum will present a smaller variation of the peaking value αmin and αmax .

xii

In practice we often choose w3dB in the range: oln3oln 2 www dB ⋅≤≤ ;

or inversely, when we have a given fi (intersection frequency), we choose :

idB fw ⋅= π23 and3dBoln

3dB

2ww

w≤≤

In a larger scope, including the specifications of the demodulator block, the optimization of theLO spectrum is bound to the type of data modulation. The following section discusses the totalphase deviation, which is a determinant parameter for phase modulated data.

3.5 Maximum Phase Jitter

The specification of the spectral purity of the local oscillator depends on the input signal that hasto be frequency-converted. For some types of digital phase modulation, such as BPSK, QPSKand GMSK, the total phase deviation is a meaningful parameter.The total phase deviation is defined as:

( )∫= max

min

f

fdffSϕϕσ [rad] (3.21)

where fmin and fmax are related to the channel bandwidth , and/or to the symbol rate.The characteristics of other blocks of the receiver, such as filter stages and the carrier recoveryloop are also relevant to the sensibility to phase noise. So the achievable BER performance maynot be directly derived from σϕ .In chapter 7 we discuss a behavioural model including the carrier recovery loop of a QPSKdecoder. This model is used to evaluate the amount of phase deviation that appears in thedemodulator, and the implementation loss caused by this signal degradation.

The LO spectrum is a combination of the contributions of Npll and vnvco, transferred by B(s) andBvco(s) respectively. We know that these two transfer functions have similar bandwidths, close town in B3LPF(s) and BVCO-BPF(s), and that wn varies with α, in a range closely proportional to thevariation of wol.

xii

Figure 3.5 is traced for a w3dB chosen by the 1st method (2π.fi = w3dB = woln), and we see that small α valuespresent a quite higher peaking than large α values.


Using σϕ as a spectral quality parameter, we search for the value of wolnpf with respect to (2π.fi

), which optimizes σϕ over the gain range of (2.r21).The plot below shows an example of the placement of wolnpf with respect to fi and rpf

xiii, so asto obtain a minimum σϕ over the total gain range.

( ) olnolnpf4

1

olnpf 22 wwfrfw ipfi ⋅=⋅⇒⋅⋅= ππ (3.22)

The output spectrum is plotted with logarithmic and linear scales. The curves are calculated fordifferent gain values covering the normalized (2.r21) range.The linear scale is presented as a visual recall of the spectrum analyzer output, usually with alinear frequency scale around fvco . It also helps to visualize the idea of a similar integral (areaunder the curve), or σϕ for the extreme gain cases.The 3rd curve presents the total phase deviation observed in the plots of the spectrum. A largebandwidth is assumed for the evaluation of σϕ .

For a −∞→→>><< p3oln

)( and)(ffff

fScstfS ϕϕ

we may enlarge the integration limits of (3.21) without changing σϕ significantly.

∫∫∫⋅

≈≈+∞ 340

5001

max

min 0

pf

zf

dfSdfSdfSf

f

ϕϕϕ (3.23)

The integration boundaries of the right most term of (3.23), are used in the calculation of σϕ .The integer values of the abscissa correspond to the geometrically distributed values of α .These α values are the same used in the other plots of Fig. 3.8 : xiv

( ) ( ) ( ) ( )[ ]5.021

25.021

25.021

5.021 2,2,1,2,2 rrrrnpf ⋅⋅⋅⋅⋅= −−αα .

The characteristics of the PLL and the VCO are identical to the ones used in the Bode plot ofFig. 3.5 . They are: Npll = -154 dBc/Hz @ Fcp = 1 MHz ; N = 1500 ; Lvco(100KHz)=-100dBc/Hz ; r21 = 25 ; r31 = 50 .

xiii

Function of r21 and r31 , expression (2.17).

xiv In figure 3.8 there is an approximation due to the constant divider ratio N. The factor 20.log(N) modulates the

height of the PLL noise contribution. So a changing value of N modifies σϕ . In our example, with a ratioNmax/Nmin =2, the change would not be significant. For other cases with a larger range of dividing ratios, we mayexpect that:• N → Nmax ⇒ α → αmin : an increase in σϕ with respect to the evaluation with a constant N;• N → Nmin ⇒ α → αmax : a decrease in σϕ with respect to the evaluation with a constant N.Therefore we may choose to center wolnpf in a frequency larger than the one indicated in equation (3.22), or in otherwords closer to fi .A numerical simulation tool is always indicated to verify the total phase deviation, with respect to N and α values.We present two options of simulation tools. The graph below is calculated with a programmed Matlab routine. Inchapter 7 we discuss another simulation model easily implemented in software for analog circuitry simulation.


Figure 3.8 Optimizing Total Phase Deviation

Fig. 3.8 shows that this set of noise performances of the PLL and VCO can accommodate a gainvariation (αmax/αmin) of factor 50, with a total phase deviation under 1.8° .This optimum σϕ performance is an important practical result for synthesizers generating low-noise carriers.

The curves from leftto right correspond tothe gain values:

a) αnpf . (2.r21)-0.5

b) αnpf . (2.r21)-0.25

c) αnpf

d) αnpf . (2.r21)+0.25

e) αnpf . (2.r21)+0.5


Other applications will demand different spectral purity parameters, for example a maximumpeak or a minimum |L(f)| (absolute single side band phase noise) within a certain frequencyoffset range.

In this case, we may use a very largefeedback bandwidth ,wolnpf >> (2π.fi) in order to have thePLL behaviour determining most ofthe spectrum around wn in all thegain range.

However, in the case of a largebandwidth we must pay attention tokeep: wn / wcp < 0.5 ; mainly withα=αmax .

Figure 3.9 Maximum SSB noise requirement

The limitation of a maximum bandwidth appears when the PLL model includes the sampling ofthe phase detector. This issue is treated in chapter 5.The boundary we propose for the moment, is a rough estimation, which is similar to a Nyquistbandwidth for a discrete system with a sampling frequency fcp .

In the numerical example treated above, it would not be possible to increase wolnpf as much asneeded for an equilibrated minimum |L(f)| throughout the whole range of α, as the maxwn isalready near to wcp . In other cases with a much worse PLL phase noise performance, it would bepossible to apply this minimum |L(f)| criterion.

The criterion of minimal |L(f)| is also called maximum flat spectrum optimization.In the scope of the rootlocus representation, we may deduce this maximum flat condition as themaximum ξ condition. Therefore maximum flat spectra are obtained for values of αcorresponding to 4 real roots (ξ=1), and a closed bandwidth well matched with fi .

The formal solution of the maximum flat point is found minimizing |B(jw)|. Reference[Wong96] discusses this problem for 4th and 5th order PLLs, comparing the algorithms ofmaximum PhM and maximum flat spectrum. But the discussion is limited to a single gain value,and is not therefore very useful in our application, where we need to accommodate rather largegain variations.

fosc

Locked VCO output Spectrum

min |L (f) |

αmin

αmax


3.6 Gain Stability Boundary

We end this chapter deriving one last practical feature that is emphasized by the rootlocus. It isthe limiting gain value that implies system instability.

In the rootlocus representation, we observe a pair of complex roots crossing the imaginary axisfor increasing gain values. Routh’s stability criterion may be used to evaluate this gain stabilityboundary. xv

B(s) is rewritten as a function of αn, , woln , r21 , r31 :

( )

1ss1

ss

1

oln

212oln

212

31

31213oln

3

314oln

214

oln

21

+

⋅+

⋅⋅+

+⋅⋅⋅+

⋅⋅⋅

⋅+

=

w

r

w

r

r

rr

wrw

r

w

rs

N

sB

nnn

αα

αα

αα

For α , αn, , woln , r21 , r31 ∈ R+ all the coefficients of the denominator are positive, but we needalso to check the first column of the Routh array, depicted in the table below:

s4 1 1

s3

oln

21

3121 wr

rr ⋅+ a1

s2

( )

+⋅−⋅⋅

3121

2131

2oln 1

rr

rrw

nαα b1

s1

( )( )

⋅−+⋅⋅

+−⋅⋅⋅2131213121

23121

313oln 1

rrrrr

rrrw

n

nα

ααα

c1

s0 = 1

nr

rw

αα⋅⋅

21

314oln

d1

Table 3-3 Gain Stability Boundary

xv

The criterion observes the coefficients of the system characteristics equation (expressed as a monic polynomial,i.e. the coefficient of the higher order term equals 1) to compose two statements: having all coefficients positive, it is a necessary condition for all the roots to have negative real parts; having all elements of the 1st column of Routh array positive, it is a necessary and sufficient condition for all

roots to have negative real parts.


Terms b1 and c1 may become negative for an increasing nα

α factor.

lim11lim

lim13121

3121

21

31211

lim1

21

31211

with

10

0

bc

crr

rr

r

rrc

br

rrb

n

n

<

=

⋅+−⋅+<⇒>

=+<⇒>

αα

αα

The difference between c1lim and b1lim is rather small when r21 and r31 are much larger than 1; sowe may work with b1lim for simplicity.

Thus for lim1bn

>αα , we have two signal changes in the column vector indicating two roots in

the RHP.Next we combine b1lim with the gain recentering expression (2.19), to determine the maximumα/αnpf ratio.

2

11

2131

31

21

31212

11

21

3121

2121

1rr

pfnpf

n

nnpf rr

r

r

rr

rr

rr

++

−

⋅+

=

⋅

+<⋅=

αα

αα

αα

We search to eliminate r31 in the expression above, by using the minimum ratio r31/r21 indicatedin chapter 2.

3

81min6,1min

1min

21

31 =

∴=

⇒

pfpf rr

r

r

In this manner the maximum gain boundary is a function of a single parameter r21 , so that:

( )

=⋅⋅<

+

npf

r

npf

rα

αα

αmax67.26.2 2

11

21

21

A couple of numerical examples for given r21 values are listed in the table below.

r21

npfαα

max

10 2.1524.3 21 =⋅⋅ r

25 3.2323.3 21 =⋅⋅ r

→ ∞ ∞→⋅⋅ 2120.3 r


Table 3-4 Maximum Normalized Gain Variation

In the table, the maximum stability values, max (α/αnpf ), are compared to the normalized

maximum value αmax = ( )npfr α⋅⋅ 212 .

The comparison shows that the stability boundary is achieved for α approaching 3.αmax , whichemphasizes the importance of choosing r21 in adequacy to the gain variation.

In this chapter we developed practical tools to evaluate the spurious rays, and to optimize thephase jitter in the ensemble VCO+PLL.We introduced the units to quantify the phase noise, and examined the closed loop transfer of theinherent noise of the VCO.The closed and open loop bandwidths of the PLL were related to adjust the filter calculation tothe requirement of a minimum phase jitter.The PLL analysis tools from chapter 2 were largely employed, and we continued to discussrobust approaches taking in account the whole range of gain variation.Finally, we calculated the theoretical limits of the gain variation to give a practical numericalboundary for people facing the constraints of a synthesizer implementation.

Chapter 4 / Active Loop Filters: AC & disturbances issues 69

Contents:

4. Active Loop Filters: AC & disturbances issues 69

4.1. Non-ideal Filter Impedance .................................................................................................................... 704.1.1. Fully 3rd order passive filter........................................................................................................... 714.1.2. Amplifier AC characteristics ......................................................................................................... 724.1.3. Amplifier with single dominant pole............................................................................................. 744.1.4. Numerical example........................................................................................................................ 764.1.5. Input impedance: Zin...................................................................................................................... 794.1.6. Summary of AC boundaries for filter design................................................................................. 80

4.2. Disturbances and Noise Propagation ..................................................................................................... 804.2.1. Random Electrical Noise ............................................................................................................... 814.2.2. Supply Disturbances ...................................................................................................................... 824.2.3. Amplifier Noise ............................................................................................................................. 824.2.4. Filter Component Noises ............................................................................................................... 834.2.5. Transfer functions table ................................................................................................................. 844.2.6. Simulation Example ...................................................................................................................... 85

Figures:

Figure 4.1 Active Loop Filter ........................................................................................................................ 70Figure 4.2 Fully 3rd order passive filter impedance...................................................................................... 72Figure 4.3 Active Filter AC model ................................................................................................................ 73Figure 4.4 Loop rootlocus with active filter.................................................................................................. 75Figure 4.5 gm Influence in Open Loop Transfers........................................................................................ 77Figure 4.6 Amplifier Input Impedance X Filter Impedance ........................................................................ 79Figure 4.7 Supply disturbances ...................................................................................................................... 82Figure 4.8 Amplifier noise.............................................................................................................................. 83Figure 4.9 Filter components noise .............................................................................................................. 83Figure 4.10 Noise simulation scheme ............................................................................................................. 85Figure 4.11 Noise simulation results .............................................................................................................. 86

Tables:

Table 4-1 Fully 3rd order passive filter: ∆PhM and ∆GM .......................................................................... 72Table 4-2 Active Filter example: Phase Margin degradation..................................................................... 78Table 4-3 Disturbances transfer functions .................................................................................................. 84Table 4-4 Noise sources voltage spectrum density ...................................................................................... 87

4 Active Loop Filters: AC & disturbances issues

Quite often PLL synthesizers drive VCOs with a tuning range higher than the PLL supplyvoltage. In these cases the filter impedance is associated with a transconductance amplifiersupporting the desired DC range at its output.In order to preserve the AC and noise specifications of the locked VCO, we must include theamplifier AC characteristics in the loop transfer functions, and examine the propagation of itsintrinsic noise sources.


This chapter introduces the first non-ideal aspects of the AC model of the PLL, which waspresented in chapter 2.Here, we look at the changes in the filtering function, that are caused by a non-ideal loopamplifier. Later in chapter 5, we study the limitations of the linear model with respect to themaximum feedback bandwidth and the maximum comparison frequency for the PLL.

In this chapter we also continue the analysis of the noise in the VCO spectrum, starting todescend from the system approach to the level of circuit implementation.The study of the active filter gives us an appropriate example to look at noise sources in the levelof circuit description. The example of deterministic sources (that are transmitted by parasiticcoupling) and the example of electrical random noise sources (shot, thermal and flicker) arediscussed in both theoretical and practical approaches.

4.1 Non-ideal Filter Impedance

Let us consider the active inverting loop filter represented in figure 4.1. The passive elements arestill responsible for the lead-lag and post-filter of ZF(s) , as represented in figure 2.4.

Figure 4.1 Active Loop Filter

The filter configuration above is quite classical in tuner applications. The amplifier is atransconductor with a high input impedance and a current output transformed in voltage by thepull-up resistor, Rpu .Ideally for a very high input impedance, transconductance gain (gm), and pull-up resistor, theamplifier characteristics are invisible in the AC transfer: Vtune/Icp , and the input node connectedto the charge pump output is held around the DC value Vref .

In a less ideal context, mainly for large bandwidth filters, the AC characteristics of the amplifierare relevant, and need to be checked and included in the loop transfer.

Z3

Icp

Vref

Vdc_high

Vtune

C2

C1

R1Zs Rpu

R3

C3


In addition, the input node voltage may vary significantly during acquisition intervals. So theamplifier input should be sensitive within the whole DC functioning range of the charge pumpoutput, to assure loop stability.

Sometimes active filters are also used in loops with an equal tuning range and supply voltage.i

In these cases the amplifier is implemented to reduce DC constraints on the charge pump output(that can work in a reduced range, being optimized for matching and noise properties), whilekeeping the tuning range close to the maximum: from ground to supply voltage. Nevertheless,choosing an active or passive filter configuration is a compromise between the reduced DCconstraints and the AC issues related to the amplifier, such as modifications in the filter transferand transmission or addition of disturbances and noise sources.

In this chapter we study these AC issues, starting with non-ideal effects in the filter impedance.In order to keep a comparative insight between the passive and active configurations, we startwith the non-ideal fully 3rd order transfer for the passive configuration, which was simplified inchapter 2 by the approximation: fp3 >> fp2 .Next we discuss the AC model of the amplifier, including first the transconductance and Rpu

effects, with a first order (single dominant pole for gm) analytical and numerical example.Secondly the influence of the input impedance is analyzed and the suggested ensemble ofboundaries is summarized.

4.1.1 Fully 3rd order passive filter

Before we start introducing the parameters that are specific to the active filter, we re-examine thetransfer of the equivalent passive filter without the approximation: Z3>>Zs.

This fully 3rd order filter transfer has a denominator which is not completely factorable asequation (2.5). So we may identify the necessary assumptions to approach the simplifiedfactorable denominator.

( )( ) ( ) ( ) )(

111

1)(

31

32113321

13 sZ

RR

CCCTsCsTsTsCs

Ts

I

VsZ F

zpp

z

cp

tuneF ≈ →

<<>>>>⋅+⋅⋅+⋅+⋅⋅+⋅⋅

⋅+==

(4.1)

For r21>>1 and r31 ≥ (1,6).r21 , the two conditional statements above may be resumed by:R3 >> R1 .

A numerical example shows us the dependency of the non-zero poles position with respect to theR3/R1 ratio. Let us call wp2n and wp3n , the non-zero poles of the equation (4.1), and k the ratioR3/R1 . Generally, a decreasing k causes wp2n to approach wz1 and wp3n to move away from wp2 .

i In the sketch above Vdc-high would then be equal to Vcc for the PLL circuit biasing.


Figure 4.2 Fully 3rd order passive filter impedance

Looking at the open loop Bode plot, the magnitude plot is rather insensitive to k changes, but thephase curve will change causing a decrease in PhM, and an increase in the frequencycorresponding to the gain margin, wCG . A larger wCG with an unchanged monotonouslydecreasing |H(jw)| implies an increase in the gain margin, Gm. Some numerical values for r=25and r31=50 are listed in the table below.

k = R3/R1 ∆PhM (°) ∆Gm (dB) wp2n / wp2 wp3n / wp3

¼ -11,8 +7,36 0,32 3,34

1 -3,46 +2,50 0,60 1,70

4 -0,903 +0,70 0,83 1,21

Table 4-1 Fully 3rd order passive filter: ∆PhM and ∆GM

Bode plots of B(jw) show that only for high gain values, with α approaching αmax , a slightincrease in peaking and decrease of wpeak is noticed, as the ratio k decreases.As a practical conclusion we can keep in mind that passive filters should work withR3 ≥ R1 , as a condition to correctly estimate the full 3rd order transfer by its factored version.

These considerations set us a 1st AC boundary to be taken into account during the calculation ofthe loop filter components, discussed in chapter 2.In the next sections the amplifier AC characteristics are included, setting additional boundarieswith respect to Rpu , gm and the amplifier poles and input impedance (Zin).

4.1.2 Amplifier AC characteristics

The AC equivalent circuit for the active filter, with the amplifier represented by its inputimpedance Zin , transconductance gm and output parallel impedance Zo , is pictured in figure 4.3.We consider Zo >> Rpu , which is usually true for our application context, but if needed we mayeasily replace Rpu by the parallel impedance Zopu in the expressions derived below. ii

ii The amplifier output as a current source may be seen as the Norton equivalent of a voltage gain amplifier, with

gain gv=-gm.Rpu , and a series output impedance Rpu . The representation as a voltage controlled amplifier may beuseful in certain simulation software containing amplifier models with Thevenin equivalent outputs.

log( f ) [Hz]

fp3fp2

fz1

∠H(jw)[ ° ]

-90°

-180°

-270°

with ZF3(s)

with ZF(s)


Figure 4.3 Active Filter AC model

For the sake of clarity, we present first the transfer of an active filter with an ideal infinite Zin ,and look at the influence of gm and Rpu . The active filter transfer, ZFa(s), becomes:

( )( ) ( )

+

+⋅⋅⋅+

+

⋅

−

=⋅+

⋅⋅+⋅−⋅=

33

3

333

11

11

)(1

1

1

)(1

)(1)()(

RR

R

gmCs

Rgm

sZgm

TssZgm

sZgmsZsZ

pupu

s

pu

suFa

(4.2)

( )( ) ( )

3’

3

’3

33’3

3333

’3

33u and

1

1

; 1

1Zwith pp

ppup

pp

p

ppu ww

wRRCT

wRCT

Ts

TsR<

=+⋅=

=⋅=

⋅+⋅+⋅

=

General conditions may be imposed over gm to approach ZFa(s) to ZF(s).

)(

)(Z

1gm

with

1

)(1

1

1

with

)(

s

3

3

sZ

s

Ts

sZgm

R

Rgm

Rgm

sZ Fp

s

pu

pu

Fa −≈ →

>>

⋅+

−

≈ →

>>⋅

>>⋅

The first conditions just affect the post-filter pole with respect to the amplifier voltage gain,gv=Rpu.gm . The second condition is more hermetic since the poles of gm and the zeros of Zs

will be mixed in the numerator polynomial.

We will now include frequency dependent aspects in the amplifier transconductance.Simple and usual loop amplifiers are composed of a high impedance voltage follower and DC-level shifter, plus a transconductor amplifying stage. We suppose that the overalltransconductance has an LPF behaviour, with a low frequency value Gmo, and poles representedby the polynomial DG(s) . The dominant poles are either from the follower or thetransconductance stage.

R3

Zs

Icp

gm.vin

Vtune

ZinC3

Z3u

Rpuvin vMZo


The lead-lag filter part is also split in numerator and denominator polynoms, Ns(s) and Ds(s).Finally, ZFa(s) can be rewritten using:

;with

)(

)(

)(

;)(

)()(;

)( ss

gG

ss

ss

s

ss

G

mn

nsDorder

nsDorder

msNorder

sD

sNsZ

sD

Gmogm >

===

== L

( ) ( )

⋅++⋅+⋅⋅

⋅

⋅−−

=

3’3 11

)()(

)()()(

)(

pppu

Gs

sGs

Fa

TsTsRGmo

sDsD

Gmo

sDsDsN

sZ (4.3)

We can preview the order of the ZFa(s) numerator and denominator with respect to ms , ns and ng

, and compare to the passive filter ZF(s).

cstkw

kwZjws

n

msZorder

cstkw

kwZjws

nn

nnsZorder

ss mnFaw

s

sF

Faw

sg

sgFa

==⇒=∴+

=

==⇒=∴++

+=

−+∞→

∞→

’1

’

for)(limfor1

)(

for)(limfor1

)(

ZFa(s) order indicates that the gm poles are reducing the filter attenuation for high frequencies,which affects for example, the suppression of the comparison frequency component.Besides, equation (4.3) suggests that at least one zero will appear in the RHP. There will also beadditional poles in the LHP. Both the RHP zero and LHP poles will contribute to decreasestability margins.

In order to have some qualitative understanding to better analyze the simulation results, wedevelop a first order analytical case, for a gm with a single dominant pole.

4.1.3 Amplifier with single dominant pole

An example is presented below for a simple amplifier model with a single dominant pole at wa.The transconductance and voltage gain become:

aa

pu

a ws

Gvo

ws

RGmogv

ws

Gmogm

+=

+

⋅=

+=

11and

1

Replacing this 1st order gm in equation (4.3) for ZFa , we verify the following changes in thedenominator:

an extra-pole is added at

+⋅⋅≈

pua R

RGvoww 31 ;

the position of the post-filter pole is a bit changed.


For wa and Gvo kept within reasonable bounds (wa≥wp3 and Gvo≥10) the influence in thedenominator is rather small.On the other hand, the numerator receives two extra-zeros, one of which is in the RHP. Inaddition, the zero from the lead-lag impedance (Zs) is quite sensitive to the product R1.Gmo.The numerator of equation (4.3) is detailed below for the single pole gm. The correspondingrootlocus is sketched in figure 4.4 . iii

( )( )

( ) ( )

+⋅⋅+⋅⋅−⋅+=⋅−=

+=

⋅+⋅⋅=⋅+=

apz

sGsFa

aG

ps

zs

wsTs

Gmo

CsTs

Gmo

sDsDsNsZnum

wssD

TsCssD

TssN

111)()(

)()(

1)(

1)(

1)(

21

1

21

1

(4.4)

Figure 4.4 Loop rootlocus with active filter

This rootlocus present an asymptotic branch running towards +∞, which is normally found inpositive feedback cases, with a characteristic equation like: 1-H(s) . In our example, this branchappears because of the RHP zero, which causes an inversion in the H(s) signal for large gainvalues.As we commented previously, most of the changes in the frequency behaviour of the activetransfer are due to the additional zeros. In the rootlocus sketch we may verify that the two zerosat low frequencies are specially relevant to system stability.

iii

The scale of this rootlocus is not linear. Distances are compacted as they run away from the origin, in order tovisualize both: close-in zeros and poles from the passive elements; and, farther ones introduced by the active device.

fz2

High frequencyadditionalzero and pole

f’z1

Res

Root Locus Ims

fz1

fp3 fp2


In order to better understand the changes in the ZFa numerator ( with respect to Ns ), we searchsimplified expressions for the zeros indicated in the rootlocus.We can consider two frequency intervals to derive approximate values for the two lowestmagnitude zeros: w’

z1 and wz2 . The first (w’z1) is close to the lead-lag zero from Ns , but its

position depends on the Gmo value. The second (wz2) is the zero added in the RHP.

−⋅

⋅⋅=

−⋅⋅+=

+≈

⇒<<∧<<<<•

<<∴

+⋅

−⋅

+≈

1 and

111)(

10for

;111)(

1

11

’111’

1

21

32’1

32’1

RGmo

RGmoww

GmoRCs

wssZnum

wwwww

wwwws

ws

wssZnum

zzz

Fa

apz

zzzzzz

Fa

( )1:for and

C

s- 111)(

10for

1222’1

21211

2’1

22

−⋅⋅=<<

⋅⋅

−⋅+=

−⋅

+≈

⇒<<∧<<<<•

RGmowwww

Gmo

T

Gmo

CTsw

sw

ssZnum

wwwww

pzzz

pz

zzFa

apap

(4.5)

We notice that the two zeros are related to the product Gmo.R1 . However, we should rememberthat R1 is chosen with respect to the PLL bandwidth and gain (woln and αn ).

iv Therefore keepinga large enough Gmo.R1 , may imply changing woln .However the choice of woln is limited by many other criteria (spurious suppression, optimizednoise transfer, limitation with respect to discrete system nature,…), and it is better to keep somedesign flexibility by assuring a high Gmo value.

4.1.4 Numerical example

We may visualize the influence of the new zeros of ZFa(s) and the accuracy of the w’z1 and wz2

estimates through a numerical example.

A reference case is calculated for an ideal amplifier (with Zin , Gmo and wa tending to infinite).The reference case is equivalent to –ZF(s) .A typical tuner application value is assumed for Rpu , equal to 22 kΩ.Figure 4.5 is calculated for a narrow band filter with the following parameters: folnpf=10 kHz; r21=25; r31=50;for: Fcp=1 MHz; Icp=200 µA; Fvco=1.5 GHz; Kvco=100 MHz/V.The resulting R1 value is 4.4 kΩ, and R3 is chosen to be equal to Rpu .

iv

Equation (2.12) repeated here for convenience: n

oln1 α

wR = .


Curve a) corresponds to the ideal factorable transfer ZF(s) .Curve b) and c) are ZFa(s) with wa=wp3 and two different values of Gmo.Curve d) is an estimation of case c) using expressions (4.5) for w’

z1 and wz2 .

Figure 4.5 gm Influence in Open Loop Transfers

A phase margin loss and a decrease in reference suppressionv is visible in cases b and c,becoming quite restrictive in c) where we may no longer work with a (2.r21) gain variation.

v Normally the reference suppression is calculated with the closed loop frequency response, B(s) , but since the open

loop magnitude is significantly smaller than 1 for f=fcp : ( ) ( )N

wBwH

cp

cp ≈ .

So we call reference attenuation ( )cpwHN ⋅ , which represents the transfer of a phase disturbance at fcp injected at

the reference input, or equivalently, the transfer of a charge pump current disturbance divided by Kϕ .

d

c

a

b

c

d

a

b


We can define ’1

2’21

z

p

w

wr = , which compared to r21 gives an overall idea of the PhM loss.

The estimation of ZFa(s), which is represented by curve d), is calculated replacing wz1 by w’z1 and

adding wz2 over an ideal transfer ZF(s). The zero frequencies, w’z and wz2 are evaluated by

equations (4.5).The approximation is fairly accurate up to wp2 , but for higher frequencies the absence of theadditional zero-pole pair deviates the estimate from the real ZFa(s) curve. Nevertheless, the w’

z1

estimation is correct enough to evaluate the parameter r’21 .

The table below brings PhM and reference transfer values for the above curves. We remark thatin cases b) and c) the reference injection is no longer attenuated. The reference injection wasevaluated in terms of phase disturbance.vi

case a) ZF(s) b) ZFa(s)with Gmo=25/Rpu

c) ZFa(s)with Gmo=10/Rpu

Gmo*R1 → ∞ 5 2

[ ]dBi

oθ

θ -16.8 +8.05 +12.2

PhM(folnpf)[°]

62.2 55.6 39.5

PhM(folnpf*r21)[°]

33.4 17.9 -9.72

r21 or r’21 25 20.4 13.8

Table 4-2 Active Filter example: Phase Margin degradation

In this narrow band filter example, we notice that low values for the product Gmo.R1, maydegrade significantly the filter transfer.If we take the same parameters in the above example, but re-calculate it for a larger bandwidthfilter with folnpf=50 kHz, we get a bigger R1 value, equal to 22 kΩ. In this case, even for low gmvalues, like in case c), the product Gmo.R1 is still large, and no important degradation isobserved in the filter transimpedance. The parameter r’

21 equals 23 for this large bandwidthexample, with Gmo=10/Rpu .Thus the requirements for the amplifier transconductance depend on the R1 value, or in otherwords, on the loop bandwidth and gain. Once more we repeat that a flexible amplifier designshould assure an important Gmo value, to avoid additional constraints on the bandwidth choice.

It is important to remember that the Gmo value varies along the output DC range. So we need toidentify the worst case situation and verify the stability boundaries for this case.Since the PhM loss becomes worse for wol close to wp2 , we must avoid having the lowest Gmovalues for α tending to αmax .

vii

vi

( ) ( ) ( ) NwHwB

KwIw dBcpcpcpChP

o

cpi

o log20)(

⋅+≈==ϕ

θθ

θ

vii The high gain situation, αmax , happens for large Kvco , and small N, which corresponds to the beginning of the

frequency band, with low Vtune values and high current output in the amplifier. For cases where the overall


Finally we may identify a practical boundary for the transconductance pole, wa .The pole wa is very determining for the position of the additional high frequency zero and pole.It also slightly affects the RHP zero, wz2 , but it has almost no drift over w’

z1 . Thus, for wa largerthan wp3 , its position concerns mainly the spurious attenuation, having a minor role for the PhMloss.

4.1.5 Input impedance: Zin

We will mention one last AC characteristics of the amplifier: its input impedance, Zin .The filtertransfer including Zin is named ZFai(s) and can be compared to the first form of ZFa(s) in (4.2).

( )

( ) ( )33

3

3 1

1

1

1)(

pu

in

us

suFai Ts

ZgmZ

ZZ

ZgmZsZ

⋅+⋅

⋅++

+⋅−⋅= (4.6)

The indication of frequency dependency (F(s)=F) for Zs , Z3u , Zin and gm is implied.In order to approach ZFai to ZFa we impose a boundary for Zin : Zin >> Zs + Z3u .

Often we search for a Zin with an infinite DC-impedance, which may be approached by a MOSgate input. In this case Zin can be represented as an equivalent input capacitor Cin .The sketch below represents the impedance magnitudes: Zs , Z3u and Zin .

In this figure we supposeR3≈ Rpu andR1 < Rpu , but we mayanalyze Cin constraint for ageneral unknownR3 , R1 and Rpu .

Let us define wi1 and wi2 asthe intersection frequenciesof Rpu and Zin , and R1 andZin respectively.

Figure 4.6 Amplifier Input Impedance X Filter Impedance

( ) 33’

333

11 for 1

if ;1

puinppu

iinpu

i wwZZwRRC

wCR

w ≤>⇒=+⋅

>⋅

=

transconductance is directly proportional to the output stage current, this αmax situation corresponds to a high Gmovalue. Nevertheless, AC simulations are necessary to check the gm for the whole amplifier (with the input stage) indifferent points of the DC working range.

w’p3

wi1 wi2

R1

|Zin(w)|

|Z3u(w)|Rpu

|Zs(w)|

|Z(jw)|

w[rad/sec]

wp3

wp2wz1


Hence keeping Zin >> Z3u for a maximum frequency higher than wp3 , and for an unknown R3,implies: Cin << C3

wZZCR

wwCR

w sinpiin

i ∀>⇒⋅

=>⋅

= for 1

if ;1

2122

12

So for Zin >> Zs we must choose Cin << C2 .It was already suggested, during the calculation of ZF3(s) , to work with C2>>C3 ; which allowsus to reduce the Zin restriction to: Cin<<C3 .

4.1.6 Summary of AC boundaries for filter design

An outline of all the boundaries proposed in this section :

amplifier)filter activefor impedanceinput negligible(

)()(for

andion)approximat factored with comparedr denominatoorder 3 (full

)()(for 3

31

321

sZsZ

sZsZ

RR

CCCC

FaFai

rd

FF

in

→

→

<<

>>>>>>

one) passive with comparednsfer filter tra (active

)()(for

5

10

1

3sZsZ

RGmo

RGmo

wwFFa

pu

pa →

>⋅

≥⋅

≥

4.2 Disturbances and Noise Propagation

The amplifier noise is sometimes visible in the out-of-loop zone of the locked spectrum,worsening the expected phase noise performance.viii

Another degradation caused by active filters is the transmission of disturbances injected in the ICinternal supply nodes.

We may quantify these effects seeking the AC transfer of noise and disturbance sources presentin the active filter model.The supply disturbance is shown as a deterministic AC signal source, vd(t), with an equivalentLaplace form, Vd(s) .

A simplified representation, analogue to an AC model, is applied for the noise sources. The noisesources are replaced by independent AC sources, and uncorrelated noise sources are added in

viii

L(foffset ) for frequencies out of the PLL bandwidth is ideally equivalent to the free-running VCO behaviour; butin practice, filter passive elements are already bringing some extra base-band noise that is frequency modulated bythe VCO.


power magnitude. The statistical theory allowing such a treatment is shortly discussed in chapter6.

The same notation used for AC sources is adopted for the noise sources, and we define smallsignal sources ini and vni representing component i noise in a current or voltage form.The frequency domain representations for (ini )

2 and (vni )2 are the classical power densities for

electrical noise (thermal, shot, flicker,…).

We take the freedom to define the noise transfers in Laplace transform, but we must rememberthat noise transfers are just defined for power magnitudes. Hence a transfer F(s) for a noisesource replaces the power transfer of the noise PSD, which is actually represented by |F(jw)|2 .A short revision on electrical noise sources and notations follows below.

4.2.1 Random Electrical Noise

We consider restrictively the most common types of electrical noise: thermal, shot and flickernoise.The notation adopted is in the form of unitary impedance power densities, expressed in current orvoltage terms:

fjwV

fjwI

∆∆22 )(,)( .

The thermal noise is associated to resistors, and has the following current or voltagerepresentation:

2

22

2222

4;4

R

VIHz

VRTkf

VHz

AR

Tk

f

I nn

rmsnrmsn =

⋅⋅⋅=

∆

⋅⋅=

∆K

T is the absolute temperature, in Kelvin, and k is the Boltzmann constant: 1.38.10-23 V.C/K .

Shot noise is encountered in any conducting junction, and flicker noise is associated to activedevices.The shot noise associated with ID , the current of a diode or bipolar transistor (base or collector),is:

⋅⋅=

∆ HzAIq

f

Irms

Dn

22

2

with q the charge of the electron in coulombs: 1.60.10-19 C .

The flicker noise associated with IB , base current in a bipolar transistor, is:

⋅=

∆ HzA

f

IK

f

IrmsB

fn

22

β

α;

where, Kf , α and β are process dependent parameters, commonly determined throughmeasurements. Typically, α and β have values around one. Kf reflects the quality of theinterfaces between diffusion layers, and a low Kf is associated with mature, and well controlledprocesses.


4.2.2 Supply Disturbances

The voltage source vd represents thedisturbances found in the IC internalsupply and ground nodes.

Figure 4.7 Supply disturbances

These disturbances can be RF current pulses either injected in the substrate or simply drainedfrom the external supply causing a voltage drop difference (ddp) as they go through theconnection path impedance. The disturbance vd often arises as deterministic modulating tones atthe oscillator input.

Switching blocks working with very steep voltage slopes and clipped signals are a typicalexample of vd generating circuitry, since they may inject quite some current in the substratethrough the collector-substrate capacitors. The crystal oscillator for low noise PLLs, workingwith large and steep swings is a good example.

The source vd is almost directly transmitted to Vtune , being only filtered by the first orderattenuation of the post-filter.

The transfer function shown in table 4-3 is calculated for Zo and Zin→ ∞. . An infinite Zo meansthat the output current variation due to vd is neglected: vd/Zo<< gm.vd .

In passive filters, such disturbances are better attenuated. First vd is transformed into a currenterror by the charge pump output impedance, which is typically high. Afterwards this currenterror is filtered by the whole ZF(s), which roughly represents a 2nd order LPF with a lower cutfrequency than wp3 .

Eventually in the active filter design we may interchange wp2 and wp3, placing the lower poleafter the amplifier in order to improve vd rejection. This exchange should be checked in anumerical application to verify gm influence in wp2 placement, and the real PhM in ZF3(s)compared to the factored ZF(s) .

4.2.3 Amplifier Noise

It is opportune to evaluate and represent the amplifier noise by a current noise source at itsoutput (ina in figure 4.8).The usual noisy twoport representation with noise sources at the quadripole input is convenientfor settings with a well known source and input impedance, but it is not adapted to a variable

vM

Zo

Zs

vd

R3Icp

gm.vin

Vtune

Zin

C3

Z3u

Rpu

vin


source impedance (charge pump on or off) and a very large input impedance (approachinginfinity, approximation of the amplifier input impedance). Furthermore the amplifier noise varieswith respect to its output current, and this is more clearly depicted by a noise source in parallel tothe output port.

The amplifier noise appears in Vtune attenuated by the transconductance gm, and filtered by thewp3 pole. The gm poles also introduce an equal number of extra zeros and poles in the Vtune /Ina

ratio . The transfer function in table 4-3 is detailed for a gm with a single dominant pole.

The post-filter components are not explicitlydrawn in figure 4.8 but as long as wecalculate VM with a load impedance equal toZ3u , Vtune it is easily derived as:

31

1

pM

tune

TsV

V

⋅+=

Figure 4.8 Amplifier noise

The thermal noise of the pull-up resistor, Rpu , may be symbolized by a current source inpu ,placed in parallel to ina ; thus the transfer Vtune /Inpu is identical to the function Vtune /Ina..

4.2.4 Filter Component Noises

In figure 4.9 we add the noise sources from the filter resistors R1 and R3 . They are the onlynoise sources common to both active and passive loop filters .

Figure 4.9 Filter components noise

Resistors thermal noise is depicted either in current or voltage form, following the convenienceof the transfer calculation.

R1 noise (In1.) is associated to the parallel R1//C2 impedance and transformed in its Theveninequivalent, Vn12 , whose transfer to Vtune is quite similar to Vtune /Vd .R3 noise in its voltage form (vn3 ) is only filtered by the post-filter before emerging directly inVtune .

vin Z3uvMZo

Zs

ina

Icp

gm.vinZin

Zs

in1

C2

C1

Rpu vM

R1 R3 vn3Icp

gm.vin

Vtune

Zin

C3

vin

Zs vn12

2

1112 1

)()(p

nn Ts

RsIsV

⋅+=


4.2.5 Transfer functions table

The following transfer functions were evaluated for the AC models in figures 4.7 through 4.9,with the approximation: Zin → ∞ and Zo >> Rpu .

The general expressions using variables gm and Z3u are further specified for the particular gmcase with a single dominant pole. These simplified expressions are also bounded by otherconditions that are indicated in table 4-3 . The expressions of Z3u and the 1st order gm arerecalled below.

( )( ) 3

’3’

3

33 :with

1

1;

1pp

p

ppuu

a

wwTs

TsRZ

ws

Gmogm <

⋅+⋅+⋅

=

+=

Signal Transfer to Vtune Specific pratical approachfor a 1st order gm

Internal supplydisturbances:vd(t) ↔ Vd(s) ( ) ( )33

3

1

1

1 pu

u

d

tune

TsZgm

Zgm

V

V

⋅+⋅

⋅+⋅

=3

3

1

1

for

pd

tune

ua

TsV

V

ZGmoww

⋅+≈

⋅⋅<<

Amplifier noise:ina ↔ Ina(s)

Pull up resistor,Rpu noise:

inpu ↔ Inpu(s)

( ) ( )

npu

tune

na

tune

up

u

na

tune

I

V

I

V

ZgmTs

Z

I

V

=

⋅+⋅⋅+=

33

3

11

( )

⋅⋅

+

+

⋅⋅+

≈

>>⋅

au

a

pna

tune

u

wZGmo

s

w

s

TsGmo

I

V

ZGmo

3

3

3

1

1

1

1

1for

Filter componentsnoise (R1):

in1 ↔ In1(s)( ) ( ) ( )32

1

3

3

1 111 ppu

u

n

tune

TsTs

R

Zgm

Zgm

I

V

⋅+⋅⋅+⋅

⋅+⋅=

( ) ( )32

1

1

3

11

for

ppn

tune

ua

TsTs

R

I

V

ZGmoww

⋅+⋅⋅+≈

⋅⋅<<

Filter componentsnoise (R3):

vn3 ↔ Vn3(s)( ) ( )3

3

333 1 ;

1

1

pn

t

pn

tune

Ts

R

I

V

TsV

V

⋅+=

⋅+=

Table 4-3 Disturbances transfer functions

The above transfer functions are better illustrated by a simulation example developed in thefollowing section.


4.2.6 Simulation Example

Figures 4.10 and 4.11 present the scheme and results of an AC noise simulation for an activefilter, with an integrated amplifier and external passive components for Rpu , Zs and the post-filter.Rd thermal noise symbolizes an AC disturbance between the internal and external grounds. Asmall resistor value was chosen to avoid significant DC disturbances. The transfer for thethermal noise of Rd is equivalent to the transfer of Vd (a supply disturbance). However we shouldremember that this thermal noise is a broadband source with a rather small amplitude in ournumerical application.

The DC-operating point is fixed by a voltage source with a high series impedance, Rbias-in .A large source impedance is necessary to avoid interfering in the filter AC transfer within thefrequency range containing the zeros and poles of interest. Besides, Rbias-in noise contribution atVtune appears as a current source filtered by Zs and Z3u ; and the larger the resistor the smaller theequivalent current noise generator. For a 10MΩ resistor, Rbias-in has a negligible effect on thetotal output noise for the plotted frequency range (10Hz to 1GHz).

The passive components are chosen for the following zero, poles and open gain values: fz1 = 1.9kHz; fp2 = 48kHz; fp3 = 106kHz ;

with: foln = 9.5kHz; αn = 6; r21 = 25 .

These numerical values are close to a satellite application, like the one shown in the Bode plotsof figure 3.5.

Figure 4.10 Noise simulation scheme

Idc1.24mA

gnd

vcc

Rd1ΩIC internal ground

30 V

Vdc_high

Vtune

330pF

8.2nF

10kΩ

Rbias-in10MΩ

22kΩ

22kΩ

68pF

IC blocks

InputStage

Zin

GmStage

gm.vin

Loop Amplifier

Biasblock

Vbias-in1.7 V

5 V


The analog simulator models thermal, shot and flicker noise sources, in the form of unitaryimpedance power densities (

fjwV

fjwI

∆∆22 )(,)( ).

The resistors have intrinsic thermal noise and the current in the transistors of the amplifiercontribute with shot and flicker noise components.

Figure 4.11 shows the voltage noise density at the Vtune output, total Vn, and the separatedcontributions of the noise sources whose transfer we identified in table 4-3 .The notation Vni stands for the noise voltage contribution of element i, in dBV/Hz units.Vna is for the amplifier noise, and Vnd, Vnpu, Vn1 and Vn3 for the resistors Rd , Rpu , R1 andR3 respectively.

The amplifier noise in our example (Vna1_total) is dominated by the gm stage, which is quiteoften a common-emiter, open collector output transistor. In the plot below this transistor basecurrent shot and flicker contributions are explained, (Vna1_ib and Vna1_fn respectively).

Figure 4.11 Noise simulation results

The simulation shows an overall filter noise dominated by the post-filter resistor, R3 , except forlow frequencies, where the gm-transistor flicker noise becomes important.

Vnvco

[Hz]


In section 3.2 we saw the representation of the oscillator free-running intrinsic behaviour as avoltage noise source, vnvco , at the VCO input (eq. (3.3) ). The overall filter noise appears as wellat the VCO input, and is added (in power magnitude) to vnvco .Let us call the overall filter noise contribution, vnfilter , and the total voltage noise at the oscillatorinput, vna :

222nfilternvcona vvv +=

The closed loop transfer of vnvco to the output spectrum was named Bvco(s) , and figure 3.12sketched the output spectra for a flat (white) noise input. Basically, a voltage noise appearing atthe VCO input is band-pass filtered, with a central frequency close to the PLL closed loopbandwidth.After the addition of the filter noise contribution, we need to verify that the vna components arestill sufficiently supressed in the in-loop range, and how much or how far the out-of-loopbehaviour deteriorated. ix

We may compare vnfilter of figure 4.11 with the vnvco of a satellite VCO, with:

( )

Hz

dBV

f

v

Hz

Vn

f

v

Hz

V

f

v

VMHzKvco

HzdBckHzL

nvco

rmsnvcormsnvco

157log10 or

14 ; 102

/100

/100100

2

216

2

−=

∆

⋅

=∆

⋅=∆

⇒

=

−= −

The value of vnvco is indicated in figure 4.11 by a dashed line. We verify that the filter noise isdominant for frequencies below 100kHz, or with respect to the filter poles, below fp3 . Since thePLL closed loop bandwidth will usually vary between fz1 and fp2 frequencies, it is most likelythat some extra out-of-loop noise will be visible up to an octave after fp3. Hence the value of R3

may be changed to improve this out-of-loop performance, still keeping in mind the boundariesdiscussed in section 4.1.6.

The marker trace, M1, highlights the fp2 pole position, which is visible as a filtering corner onthe R1 noise contribution.In fact the different noise contributions correspond quite accurately to the simplified transferexpressions in table 4-3. The numerical values below for the resistor noise sources help to verifythis result.

R [ ]Hz

Vnvco

rmsfv ∆ ( ) [ ]HzdBV

nvco fv ∆⋅ 2log10

Rd : 1Ω 0.129n -197

Rpu , R3 : 22kΩ 19.1n -154

R1 : 10kΩ 12.9n -158

Table 4-4 Noise sources voltage spectrum density

ix

It is convenient to simulate such effects with a base band PLL model. In chapter 7 a system level model ispresented, including the filter noise effects, and also an empirical approach for the phase detector discrete behaviourinfluence in the PLL noise.


The thermal noise sources are evaluated for a 300K temperature, or a 4kT=1.66.10-20 VC .The difference in Rpu and R3 noise contributions at the Vtune output, shows quite clearly theamplifier feedback rejection of Inpu and Ina (as discussed in 4.2.3). Actually, for low frequencies,a Rpu noise represented as a voltage source is attenuated by the amplifier gain:

Gvo=Gmo.Rpu .

The amplifier design used in this simulation has effectively a capacitive input impedance, withan equivalent Cin much smaller than C3 in the post-filter. This situation well suits theapproximation of Zin → ∞ , as assumed in the expressions in table 4-3.

For cases with a lower Zin the transfers are modified and part of Vd and Vn12 appear as currentdisturbances filtered by Zs . A similar effect is observed for a decreasing source impedance (Rbias-

in). In a complete PLL, this source impedance is the charge pump output impedance, which has avariable value depending on whether it is conducting (on) or not (off). For a PLL in lockedmode, the charge pump is mostly off, and it does present a rather high impedance.

Thus the transfers from table 4-3 are a valuable reference to understand and explore simulationresults for the loop amplifier design.

This chapter developed analytical and practical approaches to deal with AC characteristics ofactive loop filters. The practical boundaries and simplified transfer expressions provide themeans to evaluate and specify the design of the loop amplifier.Furthermore for cases with an equal tuning and biasing range, these evaluations indicate thetradeoff between passive and active filtering solutions.

In addition we introduced noise considerations that start to relate system specifications to acircuit implementation. Specifically, the noise of the loop filter is mostly influent in the out-of-loop zone of the VCO spectrum, thus its noise level is compared to the inherent noise sources ofthe VCO.

Chapter 5 / Limitations of the LTI Phase Model 89

Contents:

5. Limitations of the LTI Phase Model 89

5.1. Three-state comparator: frequency and phase detector ......................................................................... 915.1.1. Minimum phase deviation range ................................................................................................... 92

5.2. DC range limitations............................................................................................................................... 945.2.1. Loop filter time domain response .................................................................................................. 945.2.2. Numerical examples and design considerations ............................................................................ 96

5.3. Lock convergence approaches ................................................................................................................ 995.3.1. Frequency approach..................................................................................................................... 1005.3.2. Phase approach ............................................................................................................................ 1035.3.3. Comparing the frequency and phase approaches......................................................................... 105

5.4. Discrete transfers for the PLL Phase Model......................................................................................... 1095.4.1. The sampler ................................................................................................................................. 1095.4.2. The holder.................................................................................................................................... 1115.4.3. Continuous equivalent with transmission delay .......................................................................... 114

Figures:

Figure 5.1 Phase-detector & Charge Pump transfer.................................................................................... 91Figure 5.2 Maximum Phase Detection Range & Cycle slips ....................................................................... 92Figure 5.3 Condition for unlimited frequency tracking range..................................................................... 93Figure 5.4 Loop Filter: time response for current pulses ............................................................................ 94Figure 5.5 Time response through normalized functions ............................................................................ 96Figure 5.6 Convergence towards lock: phase deviation sequence ............................................................... 99Figure 5.7 Frequency approach convergence criterion ............................................................................. 103Figure 5.8 Phase approach convergence criterion ..................................................................................... 104Figure 5.9 Comparing frequency and phase approaches........................................................................... 105Figure 5.10 Convergence approaches X lead-lag spacing r21 .................................................................... 107Figure 5.11 Convergence approaches X gain variation ............................................................................. 108Figure 5.12 Discrete model for digital blocks ............................................................................................... 110Figure 5.13 Discrete phase detector input: ∆ϕn............................................................................................ 111Figure 5.14 Charge Pump DAC output ......................................................................................................... 112Figure 5.15 Continuous equivalent with transmission delay ....................................................................... 114Figure 5.16 Frequency and Time response for the continuous + delay model ........................................... 115

5 Limitations of the LTI Phase Model

Phase noise constraints, and even more integrated oscillator architectures, demand increasingbandwidths in PLL synthesizers. As the PLL bandwidth increases the comparison frequencyneeds to increase as well to keep the system stable.

In fact, design and stability constraints will appear to limit the values of both fol and fcp .These limitations are not contained in the LTI model discussed so far, but they can be evaluatedand/or added with additional considerations.


The limit for maximum feedback bandwidth, fcl/fcp , was already mentioned in chapter 3, makingan analogy to Nyquist bandwidths for sampled systems.The sampled nature of the PLL is connected to the digital blocks, phase detector and dividers,that we modeled so far, as linear continuous elements. Therefore the stability boundary, forfcl/fcp, can only appear by including discrete characteristics in the loop model.

The threshold bandwidth determines a limit for single loop configurations, associated to poornoise performance oscillators. We also saw (section 3.5) that spectrum optimization in the basisof a minimum |L(f)| criteria may encounter limitations bound to the maximum feedbackbandwidth.

In this chapter we develop two approaches to evaluate maximum bandwidth stability conditions.The first comes from a time domain model, examining the loop convergence from acquisition tolock mode. The second introduces time delay compensations into the frequency domain phasemodel.The time domain expressions are also used to consider problems related to reduced DC tuningranges. They are mostly encountered for fully integrated oscillators working with largebandwidth PLLs and a tuning range equal to the circuit supply voltage.

Multi-loop configurations are an architectural solution to the limitations of the feedbackbandwidth. However, multi-loop configurations tend to work with at least one wide band loop athigh comparison frequency; and in this case, we may see design constraints reducing the linearportion of the phase detector/charge pump transfer.

In frequency synthesizers we are concerned about the minimum linear range necessary toguarantee an unlimited frequency tracking behaviour. In other words, the limit for the three-statecomparator as a frequency and phase detector.

The ensemble of limitations above have non-linear characteristics that can either be included inthe LTI model, through compensations, or evaluated to mark its validity boundaries.

The first three sections deal with the PLL acquisition mode, which is not a steady mode wherethe PLL can be used as a frequency synthesizer.Nevertheless, after every change in the PLL programming the loop passes through an out-of-lockinterval, and we need to verify how the loop parameters influence the acquisition, i.e., theconvergence towards a locked mode.

The acquisition or tracking mode is formally treated in the de/modulators and in the clock/carrierrecovery contexts. A nice discussion of pulling time and pulling range may be found in reference[Wola91] for different types of phase detectors.Here we limit our scope to a qualitative understanding of the three-state phase detector in itsfrequency detector range, and to two quantitative approaches for lock convergence in the phasedetection range.

A couple of characteristics of the acquisition mode, such as locking time and maximum phasechange for a certain step (closely related to the rising time), may be specified by constraints thatare related to the functioning of the demodulator, and to the timing for the programming of thedifferent circuits in a receiver. Nevertheless these characteristics may also be derived from thelinear model, as far as the validity bounds of this representation are known.


5.1 Three-state comparator: frequency and phase detector

As mentioned in section 1.5.3 the tri-state phase detector has an unlimited tracking range. Thisbehaviour is assured by a monotonously increasing or decreasing average charge injected in theloop filter, for input signals with a positive or negative frequency difference.The figure below helps us to understand the idea of this average charge.

Let us suppose a passive filter PLL, and a lagging oscillator. In this case, the divider is late withrespect to the reference and the charge pump is sourcing, i.e. injecting current in the loop filterimpedance.If the two input signals are not at the same frequency, the phase difference will periodicallyexceed 2π and the phase detector will slip to a new linear part of the transfer curve starting at(n.2π), with n ∈ N.The phase detector slips are periodical with a rate corresponding to the frequency difference. Thephase detector works as a frequency deviation detector.

Figure 5.1 Phase-detector & Charge Pump transfer

After some time, when the oscillator frequency approaches the programmed value, the phasedifferences, minus (n.2π), will oscillate between positive and negative values.The oscillator approaches lock, and we will call this functioning mode, with low frequencydifference: the phase detection trapping zone. In figure 5.1 this is represented by the greydotted line.i

Hence, we realize that our transfer function, Iaverage/∆ϕ, is representing the average current overone comparison period; and, for input signals with different frequencies the average current overseveral periods is proportional to the frequency difference.

However, in the PLL, the oscillator frequency is changing continuously with respect to Vtune ,i.e., proportionally to the charges stored in the loop capacitors. Therefore it is difficult to talkabout a frequency difference, or an average current, over several periods, and it is easier to talkabout an accumulated charge over several periods.

i The dotted curve is slightly shifted to the right of 2π just for a better visualisation.

-Icp

Iaverage [A]

Icp

∆ϕ[rad]

-4π -2π 0 2π 4π


For the phase detector transfer sketched above, as far as the oscillator frequency is not equal to(N.fcp), the average charge derivative has the same sign as the frequency difference.Thus, the loop is capable of tracking any frequency difference inside the oscillator tunable range.Once we recognize that the frequency correction depends on the average charge, we mayconsider which limitations occur in the transfer, Iaverage/∆ϕ, that would still enable us to guaranteea monotonously changing charge, with the same signal as the input frequency delta. Theselimitations are related to the width of the reset interval, and they define a maximum comparisonfrequency for our tri-state comparator.

5.1.1 Minimum phase deviation range

A subsequent question arises for loops working with high comparison frequencies, where thecharge pump reset delay (τrst) becomes comparable to Tcp, and significantly reduces the phasedeviation input range.

As discussed in section 1.5.3, the reset delay is introduced to avoid the dead-zone problem, andits width is related to the charge pump, current sources, switching on time.

Figure 5.2 sketches possible inputs and outputs of a phase-detector/charge-pump block, for aPLL in acquisition interval. In this example the reset delay (τrst) is almost half of the comparisonperiod (Tcp).The drawing is simplified, showing only a limited slew rate for the charge pump outputs. Thereset command and the divider outputs are assumed as faster logic stages with a much higherslew rate.

Figure 5.2 Maximum Phase Detection Range & Cycle slips

Ref.div.output

Main div.output

ChargePump

And +

delay

Tcp In thePh.Detector

Ref. input

Var.input

Sourcing&

Sinkingcurrents

asynchr.reset

τrst


Figure 5.2 shows a VCO varying towards lock. The VCO is initially at a good frequency but ithas a phase advance of ∆ϕ1 . The reset delay is large enough to hide the following front of thevariable input, and consequently the next phase deviation is measured with respect to thereference input. The phase detector has slipped one cycle.

The current output after this cycle slip, increases Vtune and further accelerates the VCO. Aftersome cycles the VCO is again in advance and the charge pump current starts sinking out chargesfrom the loop filter.These cycle slips, due to the finite reset window, may be represented in the transfer functionIaverage/∆ϕin . They appear as a decrease in the linear portion; in reality, the transfer is not linearup to ± 2π, but only up to ± 2π.(1−τrst/Τcp).

The resulting transfer is shown in figure 5.3 for 2

1=cp

rst

T

τ.

Figure 5.3 Condition for unlimited frequency tracking range

We observe that τrst equals Tcp/2, is the limiting value for which the accumulated charge has thesame sign as the derivative of the phase difference.Therefore to guarantee an unlimited frequency tracking range, fcp is limited to:

rstcpf

τ⋅<

2

1(5.1)

Another way to derive the minimum range of the linear portion, is to seek a convergencecondition for the phase deviation values.Let us consider a discrete variable ∆ϕn , representing the phase deviation of the nth comparisonperiod. Close to lock the phase deviation sequence should decrease towards zero:

nn ϕϕ ∆<∆ +1 (5.2)

This degressive sequence can only be obtained, over a cycle slip, if the linear portion of thetransfer covers the range [-π , +π ]. Otherwise the module of the phase deviation would increaseafter each cycle slip, avoiding the convergence towards the lock condition.Thus we confirm the boundary proposed by the average charge approach.

-3π -π

-Icp/2

-Icp

Iaverage [A]

Icp

Icp/2

∆ϕ[rad]

-4π -2π 0 2π 4π

∆Q = 0

2ππ

0

∆Q > 0

2π

∆ϕ > π

0


Next, we continue to analyze other limitations of the linear model, related to the limited DCtuning range.The minimum phase deviation range stated above will be used in the convergence analysis tolimit the phase detection zone, and in the numerical examples of Vtune deviations due to cycleslips.

5.2 DC range limitations

In figure 5.2 we saw that reducing the linear portion of the phase detector transfer causes someextra “frequency bouncing”, before the oscillators attain a locked condition. In fact the cycle slipcauses the inversion of the charge pump current with respect to the previous comparison interval.

This effect may be quantified as a Vtune deviation, and compared to the VCO tunable range.The comparison inform us about limiting bandwidth values to avoid bouncing up and down withVtune deviations as big as the VCO tuning range.

A 2nd order filter is chosen, because it already contains the lead-lag characteristics of the 3rd

order filter, but the resulting expressions are shorter and the physical meaning is more easilyunderstood. Comments about 1st and 3rd order filters are made to extend the present results tothese other cases.

5.2.1 Loop filter time domain response

We use the Laplace inverse transform to evaluate the loop filter response for a current pulseinput, with amplitude Icp and width Td .

Figure 5.4 Loop Filter: time response for current pulses

Icp

0 Td Tcp

vM(0)

t (s)

i(t)

vM(t)

i(t)

Zs

R1

C1

C2

vM(t)


⋅

−+⋅⋅+=

⋅+=≤≤

−+⋅⋅+=≤≤

−−−−−

−

222

2

)(

11

)(

21

11

1)0()()()(:

1)0()(:0

p

d

p

d

p

d

p

TTt

TT

z

dcpM

TTt

dCdCMcpd

Tt

zcpMMd

eeT

TRIveTvTvtvTtT

eT

tRIvtvTt

(5.3)where

212111 ; CRTCRT pz ⋅=⋅= .

The expression for vM(t) in the discharging interval, [Td , Tcp], is written in two forms. Thesecond form assumes a C2 almost discharged at t=0:

⇒ )0()0(1 MC vv ≈ .

Roughly, when the charge pump is active, the filter impedance is charged or discharged in a rateproportional to Icp, and when the charge pump is off a portion of Vtune discharges through theparallel R1-C2 branch. The charge pump output impedance and the VCO input impedance areconsidered very high, though C1 discharge is not visible within Tcp .A 1st order filter (single R-C series branch) would present a stepwise variation in Vtune when Icpis turned off, with an amplitude equal to: (Icp . R) . ii

A 3rd order filter (like in figure 2.4) would have an extra time constant appearing in the chargeand discharge intervals; for instance, C1 discharge would have to be considered, and it woulddepend on the ddp difference between vM and vout at t = Td .

The maximum Vtune variation happens during ±Icp injection. We choose Td = Tcp/2 as theinjection interval, and equivalent Vtune deviation, to be compared to the tunable range.This interval of Tcp/2 is equivalent to phase deviations of ±π. So for a loop working with a largefcp, this interval is equivalent to the worst phase deviation that can occur after a cycle slip. On theother hand, for a loop working with a low fcp, this interval equals an average deviation within thephase trapping zone.

So Vtune deviation is evaluated as ∆vM(Tcp/2) :

[ ] ( )

( )

−+

⋅⋅⋅=

∆

−

=

∆=∧∈

⋅−

22

11 1

22

022

:2

,0

p

cpT

T

z

cpcp

cpM

Mcp

Mcp

Mcp

dd

eT

TRI

Tv

vT

vT

vT

TTt

Since we look for maximum bandwidth boundaries, ∆vM(Tcp/2) should be expressed as afunction of foln and fcp . Let us define the bandwidth ratio, x, and rewrite the Vtune deviation as afunction of x and r21.

ii

This variation term, named phase detector ripple in reference [Gard80], has to be inferior to the VCO input range.Reference [Gard80] discuss an approach of maximum PLL bandwidth, through the analysis of discrete transferfunctions.


[ ] ;1,0with oln ∈= xf

fx

cp

and remembering: 2oln

z1oln21

1 T

pTwwr

⋅=⋅=

( ) [ ]),(exp12 21121

21

1 rxgRIxrxr

RIT

v cpcpcp

M ⋅⋅=

⋅⋅−−+⋅⋅⋅=

∆ ππ

(5.4)

or for a Icp value corresponding to αn , and Kvco an average frequency sensitivity:

[ ] [ ]),(2),(2

2 2121 rxgxf

fVrxgx

K

fTv

osc

osctune

vco

osccpM ⋅⋅

∆⋅∆⋅=⋅⋅⋅=

∆ ππ

(5.5)

The functions g(x, r21) and x.g(x, r21) are plotted for a constant r21 in figure 5.5.a and 5.5.brespectively. For a given r21 , g(x, r21) varies between two linear functions, and x.g(x, r21)between two quadratic functions of x, corresponding to the limiting values, 0 and 1, of theexponential term.

Expression (5.4) , with Icp and R1 variables, is useful in the analysis of a given synthesizer withfixed parameters and application components. Still, R1 and Icp are related to the loop bandwidthand gain, so for a system under definition (5.5) is better suited.

Figure 5.5 Time response through normalized functions

5.2.2 Numerical examples and design considerations

fig. 5.5.a fig. 5.5.b


Expressions (5.4) and (5.5) are better perceived through numerical examples. Let us considerthree different situations with common values for the following parameters:

These values are again comparable to a band-L, satellite synthesizer application. The comparisonfrequency is not especially high, and our phase detector transfer should be linear up to ±(1,996)π.Therefore ∆vM(Tcp/2) is an average Vtune deviation.

• Example I: What are the values of the bandwidth ratio and ∆vM(Tcp/2) for a loop filter withR1 = 10kΩ and r21 =25 ?

( ) VgVT

v

xxkHzf

wR

cpM 47,125;0398,03

2

1,251

;0398,0;8,39olnn

oln1

=⋅=

∆

===→=α

This narrow band filter situation may be compared to two specific oscillator contexts withdifferent tuning ranges.In both cases a PLL bandwidth is evaluated for an average Vtune deviation equal to the tuningrange. The resulting foln is named DC-threshold bandwidth.

• Example II: What is the DC-threshold bandwidth for a LC oscillator with 28 V of tuningrange?

[ ] kHzfx

xxgxK

fV

vco

osc 312;21,31

;312,0)25,(2

28 oln ===⋅⋅⋅

=π

For a satellite band LC oscillator, a sensitivity of 125 MHz/V corresponds to a maximum Kvco

value, rather than an average one. Hence the ∆vM(Tcp/2) value is somewhat exaggerated and theDC-threshold bandwidth is a pessimistic estimation.However practical experience shows that a bandwidth of 312 kHz for a loop with a 1MHzcomparison frequency is rather unfeasible. So for loops with a large DC range, we may expectthat another limiting characteristic will determine the maximum foln .Sections 5.3 and 5.4 discuss maximum bandwidth ratios through stability approaches.

αn = 25 A.Hz/V

(1−τrst/Τcp) = 0,998

N = 1,5 k

• Kvco = 125 MHz/V

• Icp = 300 µA

• fvco =1.5 GHz

• fcp = 1 MHz

• τrst = 2 ns

• r21 = 25


• Example III: What is the DC-threshold bandwidth for an RC fully integrated oscillator with3.4 V of tuning range?

[ ] kHzfx

xxgxK

fV

vco

osc 66;2.151

;066.0)25,(2

4.3 oln ===⋅⋅⋅

=π

In this example the resulting bandwidth is rather narrow, and it shows a drawback for enlargingthe PLL bandwidth under restrained tuning ranges.

Nevertheless, RC integrated oscillators often have a degraded phase noise performance and tooptimize the overall spectrum, it is necessary to work with low noise, large bandwidth PLLs.

The resulting behaviour of loops larger than the DC-threshold bandwidth is also a “bouncingbehaviour” during acquisition. It appears as a Vtune transition that jumps up and down, and oftenblocks some time in the limiting values, before it attains lock.Thus the acquisition period may be longer than for a slower filter that would not block so oftenin the tuning range limits.

So far we treated the DC tuning range only as a given interval related to the VCO frequencyrange and sensibility. Once we recognize the need to work with “bouncing” loops, we shouldverify the design limitations connected to the tuning range, and the behaviour of input and outputblocks around Vtune , for the extreme values of the reachable range.

LC-oscillators are usually limited by the varicap sensitivity curve, presenting a degressive Kvco

for an increasing Vtune. RC-oscillators will depend on the control parameter, and the interfaceblock between Vtune and the control parameter.

In a passive filter, Vtune is also the charge pump output voltage, thus restricting the DCfunctioning range because of the output transistor saturation. In an active filter the charge pumplimitation is replaced by the loop amplifier limitation. Generally, for amplifiers with an opencollector output, there is only a minimum Vtune , corresponding to the output transistor saturation.

The combination of the VCO and the charge pump (or the amplifier) DC functioning rangesmust be examined to avoid unstable situations.For Vtune values where the VCO input is no longer sensible (Kvco =0), the oscillator will stayclipped to the maximum or minimum achieved frequency, but its spectrum is no longer lockedby the PLL, since the open loop gain is null.On the other hand, for Vtune values where the charge pump may no longer deliver current but theVCO is still sensitive, we may see an oscillating behaviour. For instance if Vtune varies aroundthis charge pump limit value, the output current varies in consequence and we may produce asustainable oscillation. This problem should be avoided by defining suitable DC functioningranges for the charge pump output and the VCO input.

For the moment let us suppose that all Vtune reachable values do not imply in an oscillatingbehaviour, but for Vtune out of the working range the oscillator stays clipped to a maximum orminimum limit frequency.


So, with more or less “bouncing” the oscillator is dragged towards lock, and now we need toverify the influence of the PLL bandwidth inside the phase detection trapping zone.

5.3 Lock convergence approaches

In the previous section, time domain expressions for Vtune sweep were derived, and compared tothe tunable range. In this section we use these expressions to verify the convergence of the phasedeviation sequence as the VCO reaches the programmed frequency.

The phase deviation sequence, as introduced in equation (5.2), represents the discrete values ofthe phase difference for each comparison period.

( ) [ ]limlim , ; :1 ϕϕϕϕ +−∈∆∆⋅+<≤⋅ nncpcp TntTn

(5.6) with πϕπ 2lim <<

Let us consider the time diagram below showing the phase detector inputs and the charge pumpoutputs for a VCO in acquisition mode.

Figure 5.6 Convergence towards lock: phase deviation sequence

0 Td1 Tcp

(Tcp–Td2)

t (s)

I cp

In thePh.Detector

Ref. input

Var.input

Charge Pumpoutput current

Vtune

∆ϕ1 ∆ϕ2

vM(0)


The oscillator initially with a phase lag, ∆ϕ1, is accelerated through the interval Tcp , and in thefollowing interval presents an advance of ∆ϕ2 .The loop reaction is very abrupt; thus the situation concerns a fast, large bandwidth filter.

We fix an arbitrary time origin to simplify the time function expressions, and we represent onlythe net current output for the charge pump.

The condition for a ∆ϕn sequence converging to 0, or a PLL tending to lock, may be applied tothe phase deviations above, imposing: 12 ϕϕ ∆<∆

We define a stability limit for the PLL bandwidth as the maximum bandwidth for which thiscondition is fulfilled.The following subsections develop expressions for this maximum bandwidth in terms of theVCO frequency and phase variations.

An initial condition is assumed for the VCO frequency in order to end up with an expression thatis an independent of this variable. The VCO is assumed at the programmed frequency, N.fcp att=0. Hence our phase deviation convergence is analyzed within a phase detector trapping zone.

Section 5.1 showed that phase detectors with a minimum linear range of ±π, are able to track anyfrequency differences inside the tunable range. Furthermore, section 5.2 showed that fast filtershave a high Vtune average deviation, which increases the probability of crossing the frequencyprogrammed value several times.Therefore the initial condition proposed above is coherent with any synthesizer loop (with anunlimited tracking range) close to lock or crossing the target frequency during Vtune variationsaround the target value.

5.3.1 Frequency approach

Referring to figure 5.6, the stability limit is reached for a PLL bandwidth that implies:

12 ϕϕ ∆=∆which means that the main divider counted N cycles of the oscillator signal between Td1 and (Tcp

–Td2).

Let us rename the limit delay, in phase and time, and relate it to the oscillator frequency, fosc :

⋅=∆

==

∆=∆=∆

cp

d

ddd

T

T

TTT

πϕϕϕϕ

2

21

12

and

( ) ( )doscdcp Tf

NTT =⋅− 2 (5.7)

Expression (5.7) supposes that the oscillator frequency does not vary within the interval( )[ ]dcpd TTT −, , or in other words, that Vtune is constant during the same interval.


We call this approximation the frequency stability approach. Its inaccuracy depends on the loopfilter discharge during the interval where the charge pump is off.The discharge would decrease Vtune , decrease fosc , and consequently increase the maximumstable PLL bandwidth. Hence, the frequency approach is pessimistic about the maximumbandwidth.

The amplitude of C2 discharge increases accordingly to the PLL bandwidth, so a maximumbandwidth boundary is quite concerned about the discharging influence.It is easier to watch the oscillator changing frequency through its integral. So, a second approachin phase cycles is discussed in section 5.3.2. The phase stability criteria is expressed in terms ofthe oscillator phase, θosc :

( ) ( ) πθθ 2⋅=−− NTTT doscdcposc (5.8)

Our initial condition for the VCO is expressed as: ( ) cposc fNf ⋅=0 (5.9)

It may be combined with expressions (5.3), for the filter pulse response, to obtain a time functionfor the oscillator frequency:

( ) ( ) [ ] ( ) [ ]

( )

( )

−≤≤

⋅

−+⋅⋅⋅+⋅

≤≤

−+⋅⋅⋅+⋅

=

∆⋅+=−⋅+=

−−−

−

dcpdT

TtT

T

z

dcpvcocp

dT

t

zcpvcocp

osc

MvcooscMMvcooscosc

TTtTeeT

TRIKfN

TteT

tRIKfN

tf

tvKfvtvKftf

p

d

p

d

p

:1

0: 1

)(0)0()(0

22

2

)(

11

11

(5.10) iii

As a result the frequency stability criterion becomes:

( ) ( )

−+⋅⋅⋅+⋅==

⋅−

−21

2 11

p

dT

T

z

dcpvcocpdosc

dcp

eT

TRIKfNTf

TT

N

It is convenient to define a time deviation, p, and make some substitutions to express thecriterion in terms of x, r21 , α and p:

iii

Once again the expression of the discharging interval assumes a C2 almost discharged at t=0; and in fact weapproach this condition in two cases:• for fast filters with wp2 comparable to 2π.fcp ;• and for close to lock condition, with Td tending to zero.The phase deviation sequence towards lock is examined for large bandwidth filters, and for ∆ϕn tending to zero, socompletely in accord with the supposition of a discharged C2.


5.00 ; 2

<<∆=⋅== pTfT

Tp dcp

cp

d

πϕ

( ) ( )

⋅⋅−−+

⋅⋅⋅⋅⋅

+=

⋅−pxrpx

rx

p n21

21

2exp12

2121

1 πππαα

or expressing this boundary as a function gfrap , we find:

( ) 02exp12

212

2g 21

21

frap =

⋅⋅−−+

⋅⋅⋅⋅⋅

+

−= pxrpx

rx

p

p

n

πππαα

(5.11)

remembering:

[ ]1,0 ; f

)gain value (average R

gain) loop(open I

; 1

T

cp

oln

nn

oln1

cp

2olnz1oln21

∈=

=

⋅=

⋅=⋅=

xf

x

w

N

K

Twwr vco

p

αα

α

The value of x solving equation (5.11), is the limit bandwidth ratio for a given set of r21 , p and αvalues. We know that the loop is considered in lock for p close to 0. Hence we need to verify thatx tends to a finite, non-zero value for the limit p→0.

First we look for some physical understanding of gfrap (limit function for the frequencyapproach), reducing it to a two variable function, and plotting it in the space (p, x, z).Figure 5.7 illustrates gfrap for constant values of r21 and α, and zooms around the valid ranges ofp and x:

[ ] [ ]5,0;0;1;0;;2521 ∈∈== pxr nαα

The surface gfrap(p, x) is cut by the plane z=0, and we may observe that x tends to a finite value(around 0.1) for p tending to 0. The influence of the other two variables, r21 and α, is examinedin section 5.3.3, including a comparison of the frequency and phase approaches.


Figure 5.7 Frequency approach convergence criterion

5.3.2 Phase approach

The phase criterion as presented in equation (5.8) may also be expressed as a function of p, x, r21

and α. The calculation steps for the phase approach limit function, gphap , are indicated below.We obtain a time function for the oscillator phase, integrating equation (5.10), and evaluate thephase change during the spotted interval: [ Td , (Tcp –Td) ].

( ) ( ) ( )( )

∆⋅+⋅−⋅⋅⋅+=− ∫− dcp

d

TT

T

Mvcodcpcpdoscdcposc dttvKTTfNTTT )(22πθθ (5.12)

Comparing (5.12) and (5.8) , gives the function below:

( ) ( )( )

−

−−−+−=

−−

−

112222 22

2

21

1p

dcp

p

d

T

TT

T

T

pdcpz

dcpvcodcpcp eeTTT

T

TRIKTTfNN ππ


Dividing by 2π.N , and using the same substitutions as for gfrap , gphap becomes:

( ) ( ) ( )[ ] ( )( )[ ] 0212exp12exp12121

2g 21212

21

phap =−⋅−−⋅⋅−−+−⋅

+−= xprpxrppx

rp

n

πππαα

(5.13)

A general idea of gphap(p, x, r21, α) is given by figure 5.8, showing gphap for fixed values of r21

and α, and restricted ranges of x and p:

[ ] [ ]5.0;0;1;0;;2521 ∈∈== pxr nαα

The intersection with the plane, z=0, shows a finite valued x (around 0.25) as p tends to 0.

Figure 5.8 Phase approach convergence criterion

As expected, the limit bandwidth ratio for the phase approach is higher than for the frequencyapproach. The difference accounts for the filter discharge during the interval where the chargepump is off.Hence, effectively the frequency approach is pessimistic, but the phase approach is a finalstability boundary. And in order to guarantee loop stability, including several variableparameters, it is necessary to have a safety margin.The following section contains comparative graphs between the two approaches, and graphsshowing the influence of the two variables fixed in figures 5.7 and 5.8, r21 and α .


5.3.3 Comparing the frequency and phase approaches

A better graphical insight of the stability boundary, shown in the tri-dimensional plots, is givenby figure 5.9. It illustrates the intersection lines between gfrap , gphap and z=0.

We choose to inverse the bandwidth ratio and plot 1/x (fcp/foln) values with respect to p(normalized delay). Therefore the frequency approach indicates a maximum PLL open loopbandwidth of approximately fcp/10 , and the phase approach of approximately fcp/4 .

Although the lock condition is achieved for p tending to zero, the limit of maximum bandwidthhas to satisfy all values of the p range to guarantee a converging phase deviation sequence. Forour case, this condition is naturally fulfilled since the stability curves present a minimum valueof x, or a maximum value of 1/x, as p tends to zero.

Figure 5.9 Comparing frequency and phase approaches

Before introducing the two missing variables, r21 and α/αn , we may compare the expressionsgfrap(p, x) and gphap(p, x) to get some insight into their differences.We observe that gphap has a higher order than gfrap , with respect to p, because of the timeintegration. A reduced form, as a limited development, may be helpful to homogenize bothequations and simplify the comparison.The first order limited developments with respect to p, around p=0 (lock point), is evaluated forgphap and gfrap .


( )44 844 76 fA

np

rr

pxp

+⋅⋅

+−≈

→ 21

21

2

0frap

122g π

αα

(5.14)

( ) ( )[ ]444444 3444444 21

pA

np x

rx

rpxp

−−+⋅⋅

+−≈

→ ππ

παα

2

2exp1122g 21

21

2

0phap (5.15)

In this form we verify that both functions are very similar, and the only differing term would beequivalent to an approximation, in gphap , of the exponential by its first order series around x=0.However for large bandwidth filters, x is not close to 0, and the difference between the linear andthe exponential terms is representing the filter discharge, whose time constant depends on x andr21 .The sum terms, Af and Ap, correspond to the voltage variations of C1 and C2 for current injectionintervals (Td) tending to zero. Capacitor C1 variation is equally considered in both approaches,and capacitor C2 discharge is neglected in gfrap. It is important to notice in (5.14), that for theusual r21 values (r21>>1), C2 voltage variation is the dominant effect in ∆vM.

5.3.3.1 Zero-Pole spacing ( r21 )

Next we verify the influence of the filter zero-pole spacing parameter, r21 .Figure 5.10 plots the limit bandwidth values (1/x) for a variable zero-pole spacing and p equalsto and ε close to 0 (p=ε , ε = 10-12).

We notice that for decreasing values of r21 , the two limiting values (gfrap =0 and gphap =0)approach each other. This result is in accordance with equations (5.14) and (5.15), since thediffering term decreases as r21 is reduced.

The limiting bandwidth variation with respect to r21 , may be intuitively understood for thefrequency approach. In fact, reducing r21 implies nearing fz1 and fp2 to foln ,i.e., for the samebandwidth (foln) and the gain value (α) C1 is reduced and C2 is increased.Hence, for the same charge injection (Icp.Td), the voltage variation in Vtune is decreased,iv andthe bandwidth limit value (foln ) increased.

In the phase approach it is harder to foresee a general idea of the sensibility to r21 . This happensbecause ∆vM is a function of both r21 and x.

iv

Remembering that C2 variation is dominant as p tends to zero.


Figure 5.10 Convergence approaches X lead-lag spacing r21

5.3.3.2 Gain variation

Finally the gain variation influence is shown in figure 5.11. It is a plot of the limit bandwidthwith respect to a normalized gain variation (α/αn ), for fixed p and r21 values.

The plot is reproduced on two scales, log-linear, and log-log. In the first we can easily read thelimit 1/x values for typical gain variations.For instance, the satellite tuner example discussed in section 3.5, has a gain range, αmax/αmin,equal to 50 (normalized variation for r21 = 25) ; centering this variation around αn in figure 5.11.aimplies a maximum bandwidth value around fcp/19 .

The plot on the log-log scale is superposed by two asymptotes in the form:

( ) 1210loglog 21kk xykxky ⋅=+⋅= L

The asymptotes are indicated by the lines in ◊ and V\PEROV

The limit bandwidth for the frequency approach may be very accurately represented by such anasymptote, with k1=0,5 . In fact k1 and k2 values could be directly estimated from equation(5.14), making gfrap equal to zero, and isolating 1/x as a function of α/αn and r21 .


In expression (5.15) it is not easy to isolate x. However figure 5.11.b, for the phase approach,shows that the graph can be approximated by two asymptotes. One around α/αn equal to one,with k1=0.75, and another for high gains, in parallel to the frequency approach asymptote.v

Figure 5.11 Convergence approaches X gain variation

Summarizing, this section (5.3) describes a lock convergence analysis to evaluate stabilityboundaries for the maximum bandwidth ratio (foln/fcp ). The influence of the zero-pole spacing,and the gain variation are also examined.The limiting bandwidth is discussed directly in terms of the center open loop bandwidth, foln ,used in the loop filter calculations. Thus we should keep in mind that α variations are an implicitmanner of discussing open and closed loop variations around the center value.

In the case of oscillators that work with small tuning ranges (fmax / fmin < 2), the oscillatorfrequency can not vary as much as presented in figure 5.6.In fact, the oscillator will mostly stay blocked at the limit Vtune values, bouncing between thelow and high boundaries. It will only converge if there is a sequence of ∆ϕn values small enoughto cause ∆vM inferior to the tuning range. So as the bandwidth approaches the limits discussedabove, such a small range oscillator will pass most of its acquisition period blocked in the lowand high Vtune boundaries.

v The second asymptote shows that very high gain ratios correspond to such a large ∆vM during injection, that the

discharge voltage delta is less and less significant.

fig. 5.11.a fig. 5.11.b


The convergence criterion is issued from the acquisition mode as a condition to attain the lockmode. In the previous chapters we discussed filter centering algorithms to optimize the outputspectrum in lock mode.In order to combine these two treatments we need to include the effects of the bandwidthlimitation in the small signal model that is described in the frequency domain.

5.4 Discrete transfers for the PLL Phase Model

The PLL synthesizer is typically a hybrid system containing both analog and digital blocks. Sofar we have replaced the digital blocks by their average behaviour with respect to the phase ofthe input and output signals.The accuracy of average behaviour models hold for loops with a control bandwidth largelyinferior to the sample frequency, i.e., the filtering is effective enough for all passing componentsin order to smooth out the input power and show an output with changing rates proportional tothe control bandwidth, and not to the sample frequency.

The average model for the digital blocks, is a linear time invariable approximation, of theirdiscrete, time variable, functioning.The linear representation of the analog blocks is also approximate because of the limited linearfunctioning range. These linear range limitations were discussed in section 5.1.So, this section continues our analysis of the LTI model limitations, examining the discrete, timevariable nature of the digital blocks.

5.4.1 The sampler

As the system bandwidth increases it is necessary to consider the limitations associated with afinite sampling frequency. A first approach, pseudo-continuous, includes extra poles or delays inthe continuous linear model, representing the stability constraints of the discrete system.vi Adirect discrete approach, developing discrete time equations and the associated z transformtransfers, is also conceivable, but mainly applied in the context of fully digital PLLs (seereference [Berg95]).

As a general rule, the following boundaries are suggested for the model choice, concerning thesystem with a closed loop bandwidth, wcl , and the sampling frequency, ws :• wcl < 20*ws : continuous model• 20*ws ≤ wcl < 10*ws : between the continuous and the pseudo-continuous model• 10*ws ≤ wcl < 2*ws : between the pseudo-continuous and the discrete model

This section develops a pseudo-continuous approach for the PLL phase model and compares it tothe stability boundaries found in section 5.3.

The basic architecture of the frequency synthesizer, as shown in figure 1.9, contains three digitalblocks: main divider, reference divider and phase detector. vi

Reference [Craw94] details the pseudo-continuous approach, developing compensated transfer function fordifferent phase detector types.


The charge pump is certainly driven by a digital input, but its output is a continuous current,better modeled as an analog signal.

The dividers are fully or partially programmable counters that transmit an overload signal everycounting cycle. The output of the dividers is in fact one input transition that is selected by thecount overload window and transmitted to the output. Therefore, the discrete model of thecounter is a sampler with a period equivalent to the output signal frequency.

The phase detector is another edge driven block, with two memory nodes registering two inputs,and a delayed asynchronous reset. It drives two switchable current sources, transforming the timedifference, Td , of the two inputs, in a current injection Td wide.

The complete discrete representation of the phase detector should include the discontinuouseffects of both edge driven inputs. However, this would imply a non-constant sampling periodand a rather complex modeling. A simplified representation takes the reference input as thesampling frequency, and the phase detector output becomes a sampled phase deviation sequenceas depicted in expression (5.6).vii

Figure 5.12 Discrete model for digital blocks

vii

The accuracy of the assumption of a synchronous resampling is limited to conditions close to lock, where theoutput of the main divider has a period approaching Tcp .A constant sensitivity, Kϕ , is also assumed for the phase detector, limiting our model to the phase detection zone.

θxtal (t)Xosc %R

θref (t)

∆ϕ(t)

θdiv (t) θosc (t)

Tcp

Tcp

Tcp

+

-

%N

Charge Pump

θdiv (n.Tcp)

∆ϕ (n.Tcp)θref (n.Tcp)

∆ϕ (n.Tcp)

θref (t)

∆ϕ(t)

θdiv (t)

Tcp+

-

Charge Pump


The divider outputs are connected to the phase detector input, therefore, our discreterepresentation would contain two samplers driving a third one, with all working at the same fcp

frequency. In other words the reference and main divider outputs are coherently resampled bythe phase detector latches.Coherent resampling does not modify a discrete variable, hence we may condense these threesamplers in the last one, within the phase detector block.

The discrete phase deviation ∆ϕ(n.Tcp) is designated as ∆ϕn , for short. The Laplace transform ofthe discrete and continuous phase deviations are related by:

( ) ( )∑∑∞

=

∞

=

⋅+∆⋅=

+∆⋅=∆

00

121

ncp

cpn cpcpn wns

TT

ns

Ts ϕπϕϕ (5.16)

for: ( ) ( ) tLs ϕϕ ∆=∆

and ( ) ( ) ( )∑∞

=

⋅−⋅∆=⋅∆0n

cpcpn TnttTn δϕϕ (5.17)

The alias terms due to the sampling will be analyzed in chapter 7. For the moment we considerthe ∆ϕ portion due to the feedback signal, with the alias terms well outside the loop bandwidth.In this case the sampled Laplace transform becomes:

( ) ( )sT

scp

n ϕϕ ∆⋅=∆ 1

5.4.2 The holder

The following step is to identify the DAC (digital to analog converter) nature of the chargepump. In reality the output current, i(t), is a sequence of current pulses, with width, sign anddelay related to the phase deviation sequence.

Figure 5.13 Discrete phase detector input: ∆ϕn

i(t)Icp

n.Tcp (n+1).Tcp

t (s)

IcpCharge Pumpoutput current

∆ϕn .(Tcp/2π) ∆ϕn+1 .(Tcp/2π)

For:

∆ϕn > 0

∆ϕn+1 < 0


For the frequency domain model we search I(s), the Laplace transform of i(t).An exact representation of I(s) is quite difficult because the frequency content (amplitude, phaseand number of significant fcp harmonics needed to represent a period) depends on the pulsewidth, i.e., the non-linearity is a function of |∆ϕn| .

In section 3.1, during the analysis of spurious rays, in the lock condition, we made a firstapproximation about the leakage current frequency content. We supposed that it was mostlyconcentrated in the 1st or fundamental harmonic.This supposition allows a worst case evaluation of the reference breakthrough. Furthermore,ignoring the higher fcp harmonics is justified by the fact that they are strongly attenuated in theloop filter.However this approximation contains no DC component, and thus is not suited to represent theband-base contents of i(t).viii

Consequently, we looked for a second approximation that preserves the DC component andsimplifies the frequency content, to a fixed known envelope. In a periodic , locked context, thisenvelope shapes a series of fcp harmonics.

Representing the charge pump as a ZOH (zero order holder) converter is equivalent to shapingthe pulse frequency content by a sinc envelope, with the first lobe node at fcp . Figure 5.14 showsa truncated portion, over one period, of i(t), iZOH(t), and the associated Fourier transform,IZOH(w).

Figure 5.14 Charge Pump DAC output

with:

( )

−⋅

⋅⋅∆⋅=

2exp

2sinc cpcp

cpnZOH

Tjw

wTTKwI ϕϕ (5.18)

viii

The base-band contents are present for every ∆ϕn different to zero.

t (s)

Icp .(∆ϕn /2π) = Kϕ . ∆ϕn

Icp. (∆ϕn .Tcp/2π )

n.Tcp (n+1).Tcp

FourierTransform

t (s)

∆ϕ

Icp

Icp. (∆ϕn .Tcp/2π)

n.Tcp ( 1) T

∆ϕ

Icp

Icp. (∆ϕn .Tcp/2π )

n.Tcp (n+1).Tcp

i(t) i ZOH(t)

| I ZOH(w) |Kϕ .∆ϕn .Tcp

-3wcp -2.wcp -wcp wcp 2wcp 3wcp

w(rad/s)


The charge pump transfer, for the ZOH equivalent output, is deduced from equations (5.17) and(5.18):

with u(t) a step function defined as:

<=≥=

0;0)(

0;1)(

ttu

ttu

and Gsh(s), the sample and hold transfer in the Laplace transform.ix

We notice that GChP-ZOH is independent of ∆ϕn , which is not the case for the transfer function ofthe actual i(t), pulse width modulated by ∆ϕn .

x

The pseudo-continuous model is an extension of the band-base, linear time invariable phasemodel. It includes some characteristics of the loop discrete functioning, but it intends to stay as aLTI system.GChP-ZOH is a linear transfer, but the only time invariable component is the DC one. xi

In a periodic locked case, this reduction can be seen as the loop filter action, attenuating thespectrum rays at fcp harmonics, and keeping only the DC ray.

Hence, the sinc shaped charge pump transfer is reduced to its DC term plus the delay:

( ) 2cpTs

cpZOHChP eTKsG⋅−

− ⋅⋅≅ ϕ (5.19)

Equation (5.19) corresponds to a first order approximation of the ZOH. The delay term appearsin a Bode plot as a constant unitary magnitude, and a linear decreasing phase. Thus it mostlyaffects the phase margin parameter. For example at f equals fcp/10 it reduces the phase margin ofπ/10 radians, or 18° .

ix

We may verify the correspondence of GChP-ZOH (s) and IZOH(w), replacing s by jw in the Gsh(s):

( )

⋅⋅⋅=

⋅

⋅⋅ → =−⋅=

⋅−

⋅−

⋅−

⋅+

⋅−

2sinc

2sin

2 2222

2 cp

cp

Tjw

cpT

jw

Ts

TsT

s

sh

TwTe

w

Tw

ejwss

eeesG

cpcp

cpcp

cp

x For i(t) output in the form: ( )∑

∞

=

⋅∆−−−−⋅=

0 2)(

n

cpn

cpcpcp

TTntunTtuIti

πϕ

the associated transfer GChP is: ( )

−⋅

∆=

⋅∆⋅−

s

eIsG

cpn Ts

n

cpChP

πϕ

ϕ

21

xi Later on, in section 6.3, a more complete transfer, time variable, is discussed for small signal analysis.

( ) ( )∑∞

=

∆⋅−=∆0n

cpn tnTt ϕδϕ

( ) ( )sGKs

eKsG sh

Ts

ZOHChP

cp

⋅=

−⋅=⋅−

− ϕϕ1

ChargePump

( ) ( ) ( )( )[ ]cpcpnZOH TntunTtuKti 1+−−−⋅⋅∆= ϕϕ


5.4.3 Continuous equivalent with transmission delay

We may recognize that other pulse approximations for i(t) would present similar LTI transfers.In figure 5.15 we name ipw(t) a generic pulse function of width Tw and same DC content as i(t).The related Fourier transform, Ipw(w), and charge pump transfer, GChP-pw(s), are also indicated.

Figure 5.15 Continuous equivalent with transmission delay

( ) 2wTs

ww

cppwChP eT

T

TKsG

⋅−

− ⋅⋅⋅≅ ϕ

Among the possible pulse approximations, the ZOH presents the largest delay. And since thetime delay is the limiting stability constraint introduced by the pseudo-continuous model, wecontinue this analysis with the ZOH approach.

Next we search convenient polynomial representations for the time delay. Two simplepossibilities are:

• real pole at f=fcp/2 (similar to first order filtering around the Nyquist frequency, fc/2):easy implementation, but not accurate in magnitude and phase, mainly for frequenciesnearing fcp/2. At fcp/2 it represents a phase decrease of 45°, comparable to a time delay ofTcp/4. This time delay is associated to a charge pump transfer with width Tw equals to Tcp/2.

• Pade polynomials: composed of pairs of zero and poles, symmetrically placed around theimaginary axis of the S-plane. The order, n, indicates the order of the numerator anddenominator polynomials. The magnitude frequency response is unitary everywhere, and thephase decreases up to n*(-180°) .The phase decreases almost linearly up to n*(-90°) . Therefore the order of the polynomialmust be chosen comparing the maximum loop bandwidth to(w*Tdelay) .

A numerical example is presented below. We examine the open and closed loop transfers for afilter with r21 equals to 25, and a normalized gain variation range (2.r21).

∆ϕn . Kϕ . Tcp/Tw1

Τw1

Kϕ .∆ϕn .Tcp

-3wcp -2wcp -wcp wcp 2wcp 3wcp

w(rad/s)

i pw(t) | I pw(w) |

t (s)

Τw2

n.Tcp ( 1) T

n.Tcp (n+1).Tcp


The zero-pole spacing parameter (r21) is equal to the evaluation of figure 5.11, so that we cancompare the results of the delay approach and the ∆ϕn convergence approach.

Figure 5.16 shows the open loop phase plot, and the closed loop step response for a continuousmodel with a transmission delay of Tcp/2 , modeled by a 2nd order Pade polynomial.The continuous nominal loop is a 3rd order one, with a 2nd order loop filter. The numericalparameters used in the graphs, are listed below:

r21 = 25; woln = 10 rad/s (symbolical value, not related to applications) wcp = 21.1 * woln = 211 rad/s

Figure 5.16 Frequency and Time response for the continuous + delay model

The phase response pictures three curves corresponding to the pure time delay, the nominalcontinuous transfer and the continuous plus delay model.Dashed-dotted lines indicate the open loop crossing frequencies (fol) for the normalized gainvariation. Over the -180° line there are symbols marking: wz1 (o), woln ( Zp2 (x) andwcp (◊).

The sample frequency, wcp , was chosen as the limit value for which the phase margincorresponding to the maximum normalized gain (αmax ) equals zero. Therefore we may comparethe ratio wcp /woln to the limit 1/x values in figure 5.11.

fig. 5.16.a fig. 5.16.b

nominal + delay

c

b a


( ) ( ) ( ) ( )ln221max 507,72max

opolnn wPhMwPhMwPhMr ⋅==⋅=⋅⋅==αα

ααα K

1,21

19~1

lnln

Lxf

f

w

w

o

cp

o

cp ==

So in spite of all reductive approximations made in the delay analysis, it is still comparable to thetime convergence methods.

The step response is calculated for a frequency change equal to wosc/N, and the signal plotted isproportional to either the oscillator angular frequency or the filter voltage output.

( ) ( )2

1

1

or N

N

N

sBf

N

sB

N

wV

N

Kref

osctune

o ⋅∆⋅↔=⋅

The three curves correspond to the following gain values: a: α=αmin or wol = wz1 = 2 rad/s = 2π.(0.32 Hz) b: α=αn or wol = woln = 10 rad/s = 2π.(1.59 Hz) c: α≈αmax/2 or wol ≈ 3.woln = 30 rad/s = 2π.(4.7 Hz)

Curve c corresponds to the maximum gain value with a PhM≥30° for the continuous plus delaymodel. In the phase plot, the corresponding fol is also indicated through the dashed-dotted lines.

The continuous plus delay model is mostly an approximation for locked mode simulations, dueto its linear character. Nevertheless we should be aware of the limitations to know the tendencyof the inaccuracy present in the simulations results.

In fact, during the acquisition mode there is not really a constant sampling frequency, but fcp isthe slowest one possible, so the most critical.The phase deviation is also not constant during each comparison interval, and this may interferein the width of the current injection for cases where the oscillator is lagging the reference. Againwhen we use the maximum delay (Tcp/2) we are taking the worst case.

Therefore the continuous plus delay model, with a Tcp/2 delay, is a pessimistic estimate of thelock and acquisition mode, and it may be used to evaluate stability boundaries due to enlargingfeedback bandwidths. The pessimistic error is not so large, as we see through the comparisonwith the phase convergence method, and it constitutes a small addition to the safety margin.Another application of this delayed model appears in spectrum optimizations, where the phasemargin loss may affect the peaking. For this typical locked mode simulations, the Tcp/2 delay istoo pessimistic, and the results will not fit measured situations. A compromise fittingmeasurements is found for a delayed model with a Tcp/4 delay.

: for the phase convergence method

: for the continuous + worst delay method


This chapter dealt with non-linear aspects of the PLL functioning. These aspects are bounded tolarge bandwidth loops, and they impose maximum limits for fcp and fol .

The first issue (fcp) appears in multi-loop contexts and it was analyzed through the minimumphase detection range assuring an unlimited frequency tracking behaviour.

The second (fol) appears in general loop structures containing discrete behavioural elements.

Most of the PLL discrete models are issued from pure digital loops analysis, where descriptionsin Z transform are easily determined.In our mixed discrete-continuous context, two characteristics are especially difficult to include ina Z-transform representation: a DAC not strictly linear and a varying sampling frequency.Thus, we preferred to start with time domain models, and, later search for a simplified frequencydomain representation.The simplified frequency model is in fact a continuous one, with an additional time delay.

Both time and frequency models were evaluated and discussed with respect to the loopparameters presented in the previous chapters, (zero-pole spacing, gain variation, …)

Chapter 6 / Phase Noise: theoretical to practical approach 119

Contents:

6. Phase Noise: theoretical to practical approach 119

6.1. Electrical Noise: random source representation & measurements....................................................... 1206.1.1. Electrical noise as a random process ........................................................................................... 1216.1.2. Measuring Phase Noise ............................................................................................................... 123

6.2. Phase Noise Notations .......................................................................................................................... 1256.2.1. Interchanging Modulation Types................................................................................................. 125

6.2.1.1. Angular modulation ................................................................................................................ 1276.2.2. Phasor Notations.......................................................................................................................... 1286.2.3. Slope approach ............................................................................................................................ 133

6.3. Large Signal Linearization ................................................................................................................... 1356.3.1. Time and Frequency representation............................................................................................. 1356.3.2. Linear Time Variable transfer ..................................................................................................... 136

Figures:

Figure 6.1 Spectrum Analyzer Output ........................................................................................................ 124Figure 6.2 FM & PM carriers .................................................................................................................... 128Figure 6.3 SSB superposed noise: AM + PM decomposition (phasor)...................................................... 129Figure 6.4 Superposed Noise: AM + PM decomposition (spectrum)......................................................... 130Figure 6.5 Phase modulated carrier by DSB superposed noise ................................................................. 131Figure 6.6 Phase deviation from DSB sidebands ....................................................................................... 132Figure 6.7 Slope approach: voltage & time deviations............................................................................... 133Figure 6.8 Periodic transfer determined by a large signal ......................................................................... 136Figure 6.9 Large Signal Transfer: ideal and hyperbolic-tangent limitations............................................ 138

Tables:

Table 6-1 Phase Modulated Carrier .......................................................................................................... 126Table 6-2 L(foffset) from modulated and superposed noise ........................................................................ 132

6 Phase Noise: theoretical to practical approach

Phase noise is an important parameter in the performance of frequency synthesizers. Low noisedesign needs to consider the mechanisms originating phase deviations in the output carrier; andrelate them to the noise sources that are present in the circuit.

The analysis starts with basic aspects on random noise representation and measurement, and isfollowed by a discussion on different notations for phase noise. Finally, we consider the transferfunction of stages that work in a periodic, non-linear mode.


Phase Noise is a convenient parameter to quantify unwanted phase variation in a periodic signal.Phase variation can be caused by a linear phenomenon such as signal addition and also by non-linear phenomena such as angular modulation.In the PLL synthesizer we consider two sources of periodic signals, which are disturbed by phasenoise: the reference oscillator and the voltage controlled oscillator. The disturbances are eitherintrinsic to the periodic sources, or are accumulated as their outputs propagate through the PLLblocks.

The power that generates phase variations can come from random or deterministic sources. Therepresentation of electrical random noise is shortly discussed, introducing the notation in thefrequency domain, for stationary and cyclostationary sources. The deterministic sources are alsodescribed in the frequency domain, which allows us to develop a common treatment for bothtypes of disturbance.

Phase noise is represented in many different notations, which are chosen with respect to theorigin of the phase deviation, or to the measurement tools. We discuss some notations that arebased on: the equivalence amongst different types of modulation, the addition of signalsrepresented by phasors, and the time deviation in switching stages.The last one is very significant to describe the noise added by the logical blocks of the PLL(dividers and phase detector). This description is further developed to take into account thenon-linear and periodic behaviour of these blocks.

In chapter 7 we relate the notations for phase noise and the transfer functions of the precedingchapters. The noise performance of the synthesizer is investigated in a top-down approach, frombehavioural to circuit level descriptions.

6.1 Electrical Noise: random source representation & measurements

The denomination noise is given to any power signal disturbing the data signal (which containsthe transmitted data or information). Noise sources can be internal to the integrated circuit, orexternal, from the application environment.We consider two types of noise: interference and stochastic electrical noise.The first is associated to deterministic signals polluting the output carrier. They are generated bythe operation of different parts of the circuit and are transmitted by parasitic coupling.The second refers to the random movement of electrons, implying fluctuations in voltage andcurrent signals. They are thermal, shot, flicker and other types of random noise.

We mentioned two sources of interference in chapters 3 and 4: the reference breakthrough andthe deterministic disturbances found in the supplies of the loop-amplifier.On the other hand, NPLL and vnvco (defined in chapter 3), and the shot and thermal noise of theamplifier and the loop-filter components (discussed in chapter 4), are random noise sources.Furthermore we consider that they are stationary noise sources that can be described by theirpower spectrum density.


6.1.1 Electrical noise as a random process

Electrical noise arises from current and voltage fluctuations in the circuit. The mechanismsoriginating these fluctuations are related to thermal agitation, and to variations in the currentflow of electronic devices. These fluctuations vary randomly, and are described as stochastic orrandom processes.The random characteristic defines a variable or a process that is not predictable before itsoccurrence, but presents defined statistical properties.Random processes are defined as an ensemble of time functions whose statistical properties aredescribed by a common probability rule. Each time function is a sample of the random processsample space. The statistical description of the process is contained in the probability densityfunction. This function describes the probabilistic distribution of the values of the samplefunctions, when they are observed at a given time instant.When the probability density function is independent of the observation instant, the randomprocess is said to be stationary. An important property is derived from the stationary condition:ergodicity. This is attributed to processes where the statistical properties of the ensemble can beestimated by time averages of individual sample functions of the process.Ergodicity is a very important property for the measurement of stochastic processes, since thesemeasurements are based on the observation of a sample function during a time interval.

In practice, stochastic processes are not evaluated by a probability density function (which is notdirectly measurable) but more frequently by their first and second moments: mean value andautocorrelation, respectively. A stationary process X(t) presents the following mean andautocorrelation: mean: [ ])(tXmX Ε=

autocorrelation: ( ) ( ) ( )[ ]ττ −⋅Ε= tXtXXR

where E is the expectation operator, and τ is a time delay. The mean-square value equals theautocorrelation for a zero time delay:

mean-square: ( ) ( )[ ]tXX20R Ε=

A process that presents: a constant average, an autocorrelation which is independent of shifts inthe time origin, and a finite value for the autocorrelation at the time origin, is said to be wide-sense stationary (WSS). They do not present all the characteristics of a stationary process, butinclude the most significant, as described by the 1st and 2nd moments.Usually for the measurement intervals that we are interested ini, the electrical noise sources maybe modeled as WSS processes with a Gaussian distribution of amplitude.

The Gaussian distribution is nicely adapted to describe physical phenomena depending on manyindependent random variables. This is related to the central limit theorem, which affirms that thesum of many independent random variables with defined 1st and 2nd moments, tends to present aGaussian distribution as the number of variables increases without limit.Consider that the movement of each electron is described by an average component plus arandom one.ii The sum of the different paths of the electrons in a conductor approaches a

i Measurements in the time and frequency domain observe a signal during a time interval that is large enough to

average over several periods of the noise components being measured, but still small enough to consider the processas stationary.


Gaussian random variable. Thermal and shot noise present a Gaussian amplitude distribution anda zero mean value. The thermal noise of a resistor of R ohms has the following mean squarevalue expressed in volts:

( )[ ] 222 2 voltsfRkTtVV TNn ∆⋅=Ε= (6.1)

where ∆f indicates the bandwidth over which the noise voltage is measured. In equation (6.1) themultiplying factor 2 instead of 4 (as in equation (4.7) of chapter 4) refers to a double sidedfrequency representation, for a spectrum with positive and negative frequencies.

The Fourier transform of the autocorrelation function describes the random process in thefrequency domain. It is the power spectral density (PSD) of the process, defined as:

( ) ( ) ( ) ττπτ dfjRfS XX 2exp −⋅= ∫∞

∞−

or inversely

( ) ( ) ( ) dffjfSR XX τπτ 2exp∫∞

∞−

⋅=

We observe that the integral of the power spectral density over the whole frequency range,equals RX(0), which is the total power or the mean-square value. When considering a voltage orcurrent noise density, the integral equals the total power for a unitary impedance.The power spectrum density of a WSS random process has similar properties to the PSD ofdeterministic signals. The output of a block with a linear-time-invariable transfer function H(f)for a noise input described by SX(f) becomes:

( ) ( ) ( )fSfHfS XY ⋅= 2

A process that presents a constant power spectrum density for all frequencies is called white.White noise is a practical representation for band limited systems where the noise spectrum isconstant over the relevant part of the frequency range. White noise with unlimited bandwidthdoes not exist because it would represent an infinite power.Ideal white noise corresponds to an autocorrelation function which is an impulse at τ=0 , andequals zero everywhere else. It means that any two samples from different time instants arecompletely uncorrelated. Band-limited white noise presents an autocorrelation function shapedas a sinc curve. The width of the lobes of the sinc are inversely proportional to the filteringbandwidth.

Shot and thermal noise are approximated by white Gaussian noise. These approximations holdfor limiting bandwidths to the order of 1012 Hz, which is largely above the limit of our workingfrequencies.Flicker noise is commonly represented by a white Gaussian noise which is shaped by a 1/f filter.This representation is limited to a minimum value of frequency, to avoid an infinite powerdensity as f approaches 0.

Electrical noise contributions whose amplitude varies with respect to a periodic deterministicsignal, are called cyclostationary. They are represented by the product of a normalized stationary

ii

In the case of thermal noise the average component equals zero, and in the case of shot noise the averagecomponent equals the net current flowing in the device.


process with a periodic large signal; or in other words, by a random process which is amplitudemodulated. The shot noise of a transistor driven by a periodic input is a cyclostationary noise.The time average of the noise power of a cyclostationary noise is proportional to the rms value ofthe periodic signal which modulates the random process.For example let us consider the shot noise of a transistor driven by a sinousoidal input atfrequency fc :

( ) ( ) ( )tXtiqtIshot ⋅⋅= (6.2) iii

where X(t) is the normalized random process, with a white unitary PSD which is limited by aphysical bandwidth defined by the circuit. i(t) is the deterministic current signal that results fromthe sinusoidal input, for example:

( ) ( )[ ]Θ++⋅= tfI

ti ct π2cos1

2Θ is a random phase uniformly distributed in the range [0 , 2π]. It indicates that X(t) and i(t) arenot related to a common time origin.Part of the power of this shot noise is frequency translated around ±fc . Other examples offrequency translation of noise appear as we investigate time variable transfer functions. Thesetransfers are discussed in section 6.3.The representation of random noise by their PSD allows us to use a common small signaltreatment for both deterministic and random signals. The random signal is considered as thesuperposition of uncorrelated portions of narrow band signals. This supposition was firstmentioned in chapter 3 when we considered a single tone contribution of vnvco .We continue this introduction considering the measurement of noise in the time and frequencydomain.

6.1.2 Measuring Phase Noise

Phase noise is a magnitude measuring phase deviations in a carrier. Section 6.2 discussesdifferent mechanisms that convert noise power in amplitude and phase deviations. In the outputof the VCO we find mainly phase deviations. This is due to the frequency modulatingcharacteristic of the input of the VCO, and also due to amplitude limitations that occur in theintermediate and output stages of the VCO.Phase noise is measured by different methods which evaluate the performance of the carrier inthe time and frequency domains.In our context the spectrum analysis is the most current method.The spectrum analyzer measures the power present in a certain band of frequency, by sweepingan analysis window through a specified range of frequency. It is basically composed of afrequency conversion block, which is followed by a filter with a variable bandwidth and by apower meter. The analysis window corresponds to the filter bandwidth and is called resolutionbandwidth (RBW). Figure 6.1 represents an LO spectrum measured with two different resolutionbandwidths, RBW1 and RBW2.

iii

In equation (6.2) the amplitude of the shot noise also refers to a double sided spectrum with positive and negativefrequencies.


Figure 6.1 Spectrum Analyzer Output

In figure 6.1 the sideband rays at frequency offsets of ±fm are caused by a deterministic noisecomponent. This noise has a spectrum component at frequency fm which modulates the carrieroutput. The power of the modulated rays is concentrated in very narrow bandwidths around fosc±fm iv, which are considerably smaller than the values of the RBW. So the power of thesesidebands is not affected by the width of the RBW. The power ratio between these sidebands andthe carrier is expressed in dBc.The parts of the sidebands that are caused by random noise (in-loop contribution from NPLL andout-of-loop contribution from vnvco) have a power level that varies with the width of the RBW.This is due to the spread-out characteristic of the power spectrum density of these noisecontributions.Let us consider a white random noise in the output with a power spectral density No in W/Hz.The power due to this contribution as the analysis window sweeps the frequency range equals:No.RBW. The power ratio between the sidebands due to random noise and the carrier is oftenexpressed in dBc/Hz. This unit is used to normalize the power level to a 1Hz bandwidth. Theratio SSB noise / carrier when expressed in dBc/Hz, corresponds to LdB(foffset) which was definedin chapter 3 (equation (3.4) ).

The phase noise performance can also be measured by a time parameter: the time jitter. Thisexpresses the variations of the period of the carrier. There are two different methods. Onemeasures the variations of the period when compared to a reference oscillator. The result iscalled time-deviation jitter. The second calculates the dispersion of the value of the period withrespect to its own average. The result is called time-interval jitter. In both types of measurementthere are several parameters that strongly influence the value of the jitter measured. For instancethe time step and the measurement interval determine the maximum and minimum frequencies ofthe noise components that are taken into account.Reference [Nord97] discusses the techniques of time jitter measurement and the parameters thatinfluence the results. It also shows that time-deviation jitter is related to the phase deviation inthe carrier, and that time-interval jitter is related to the frequency deviation.The relationships amongst phase, frequency and time deviations are discussed in the followingsection.

iv

Ideally the modulating rays are represented by impulses at fosc ± fm . However the modulating signal is limited intime and its spectrum has a finite width.

Spuriousdeterministic signal

fosc-fm fosc fosc+fm

⋅

2

1log10RBW

RBW


6.2 Phase Noise Notations

The description of phase noise varies with respect to the functionality of the blocks to which itrefers. In oscillators the phase noise is often quantified by phase or frequency magnitudes, and inlogical blocks it is quantified by time magnitudes.In every node of the circuit there is some noise power being added to the data signal. Inparticular at the input node of the VCO, the voltage noise is converted into phase deviation byfrequency modulation. In other nodes of the circuit the added noise power causes both amplitudeand phase deviations of the signal. Phase noise can be caused by angular modulation of noisepower, or by addition of noise power to the signal.In this section we detail these two mechanisms of the generation of phase noise, that we callmodulated and superposed noise. We start with the angular modulation, looking at therelationships amongst phase, frequency and time modulations. We continue with the distinctionof phase and amplitude deviations caused by an added noise power. Finally we look at the effectof amplitude limitation on the transmission of signals corrupted by noise.

6.2.1 Interchanging Modulation Types

The phase deviation of a carrier may also be expressed as frequency and time deviations (seereference [Nord97]). Let us consider a sinousoidal carrier vc(t), and the time functions ∆ϕ(t),∆f(t) and ∆t(t) which modulate the carrier. It follows that:

unmodulated carrier: ( )v t A f tc c c( ) sin= ⋅ ⋅ ⋅2π

phase modulated carrier: ( )v t A f t tPMc c c( ) sin ( )= ⋅ ⋅ ⋅ +2π ∆ϕ

frequency modulated carrier: ( )[ ]v t A f f t tFMc c c( ) sin ( )= ⋅ ⋅ + ⋅ +2π µ∆ ∆ϕ

time modulated carrier: ( )[ ]v t A f t t tTMc c c( ) sin ( )= ⋅ ⋅ +2π ∆

The three modulated signals are equivalent to each other if:

∆ ∆ϕ ∆ ∆ϕ∆ϕf t

t

tt

t

tt t t

t

fc

( )( )

; ( )( )

; ( )( )= ⋅ = − ⋅ =1

2 2π∂∆ϕ

∂µ ∂∆ϕ

∂ π

We may also express vc(t) and the modulating functions ∆ϕ(t), ∆f(t) and ∆t(t) with respect totheir power spectrum densities. They become:

carrier: vc(t) …….. )( fSc

phase deviation: ∆ϕ(t) …….. )( fS ϕ∆


frequency deviation: ∆f(t) …….. )()(2

2)( 2

2

fSffSfj

fS f ϕϕππ

∆∆∆ ⋅−=⋅

=

time deviation: ∆t(t) …….. )(2

1)(

2

fSf

fSc

t ϕπ ∆∆ ⋅

=

Therefore the power of the total frequency or time deviations can be evaluated using the spectraldensity of the phase deviation. The power of the deviations is the integral of the PSD over adetermined frequency interval.Let us consider that ∆ϕ(t) is a random phase deviation, with a PSD which is a band-limited whitenoise. The spectra of the carrier and the modulating noise are sketched in the table below, usingsingle and double sided representations of the frequency axis.

SpectraSignal & PSD Single Sided

(only positive frequencies)Double Sided

(pos. and neg. frequencies)

carrier:

Sc(f) [V2/Hz]

[ ])()(4

)(2

ccc

c ffffA

fS ++−⋅= δδ

phase deviation:

S∆ϕ(f) [rad2/Hz]

=∧>

≤

=∆

0;0

;2

)(

fbwf

bwfN

fS

O

ϕ

phase modulated carrier:

Sosc(f) [V2/Hz]

( ) ( ) ccc

cosc

ffSffSA

fSfS

++−⋅+

+≈

∆∆ ϕϕ4...

...)()(2

Table 6-1 Phase Modulated Carrier

The spectra of the phase modulated signal was drawn considering that the peak phase deviationis small (max∆ϕ(t)<<1 rad). The following subsection details the expressions of the angularmodulation, and the FM narrow bandwidth approximation.

fc f

2

2cA

|Sc(f)|

-fc fc f

4

2cA

|Sc(f)|

No

bwn f

|S∆ϕ(f)|

No/2

-bwn bwn f

|Pϕ(f)|

8

2oc NA ⋅

-fc-bwn -fc fc

4

2cA

|Sosc(f)|

4

2oc NA ⋅

2

2cA

fc-bwn fc

|Sosc(f)|


6.2.1.1 Angular modulation

The output spectrum of the PLL synthesizer presents an in-loop zone that is phase modulated bythe PLL noise (NPLL), and an out-of-loop zone that is frequency modulated by the intrinsic noiseof the VCO and by the loop filter noise.PM and FM are two types of angular modulation. The example of a single tone modulation isdetailed below. Furthermore noise contributions that are represented by a power density, may beseen as a superposition of single tone modulations.Let us consider the same carrier vc(t) defined above, and a single modulating tone vm(t). Thephase modulated carrier is named vPM(t), and equals:

( )[ ]mmmpccPM tfAKtfAtv ϕππ +⋅⋅+⋅= 2sin2sin)( (6.3)

where( )mmmm tfAtv ϕπ +⋅⋅⋅= 2sin)(

and Kp is the phase deviation sensibility in rad/V. We may also define ∆ϕp the peak phasedeviation and rewrite vPM as:

( ) ( )[ ] ( ) ( )[ ] mmpcmmpccPM tftftftfAtv ϕπϕπϕπϕπ +⋅∆⋅++⋅∆⋅⋅= 2sinsin2cos2sincos2sin)(

and mpp AK ⋅=∆ϕ

or ( ) ( )[ ]mmcn

pncPM tfntfJAtv ϕπϕ ++⋅∆⋅= ∑+∞

−∞=

2sin)(

where the coefficients Jn(β) are the values of the Bessel function of the nth order with argumentβ. The value of these coefficients for β << 1 rad , approach:

( ) ( ) ( )J J J for n and n Nn0 112

0 1β β β β≈ ≈ ≈ > ∈; ; ,

In this case of small phase deviations vPM is simplified to:

( ) ( )[ ] ( )[ ]

−−⋅∆

−++⋅∆

+⋅= mmcp

mmcp

ccPM tfftfftfAtv ϕπϕ

ϕπϕ

π 2sin2

2sin2

2sin)(

(6.4)where the SSB ratio noise/carrier equals:

( )2

:2

log202

log20 prms

rmspmdB fL

ϕϕϕϕ ∆

=∆

∆

⋅=

∆⋅=

Next we consider a single tone frequency modulated carrier vFM(t) , in the form:

[ ] ( )

+⋅

⋅⋅⋅

+⋅=+⋅= ∫ mmm

mfccmfccFM tf

f

AKtfAdttvtfAtv ϕπ

ππ

πππ 2sin2

22sin)(22sin)(

(6.5)


wherev

( )mmmmf tfA(t)v ϕ+⋅⋅⋅= 2cos

and Kf is the frequency deviation sensibility in Hz/V. If we define the peak phase deviation as

m

p

m

mffp f

f

f

AK ∆=

⋅=∆ϕ

equation (6.5) becomes equivalent to equation (6.3) for the phase modulated carrier.

An important difference between frequency and phase modulation is that the phase deviationcaused by FM has an amplitude which depends on the frequency of the modulating signal. Figure6.2 shows these differences in the spectrum of a carrier that is modulated by a band-limited whitenoise.

Figure 6.2 FM & PM carriers

In the frequency modulated carrier the phase deviation is proportional to 1/fm. Therefore for fm

tending to zero, the approximation of small phase deviations is no longer valid. In figure 6.2 thislimit is indicated by the dotted lines and by the reduction of the power at ±fc ( J0(∆ϕp)<1).

6.2.2 Phasor Notations

In this section we consider the phase and amplitude deviations caused by a superposed noise. Westart looking at the deviations caused by a single tone noise at a certain frequency offset from thecarrier. This case is called the single side band superposed noise.The combination of two SSB noise contributions at opposite frequency offsets (±foffset) is alsoconsidered and compared to the sidebands produced by angular modulation.

v In the FM example the modulating tone is assumed as a cosinus function just to end with the same form as in the

PM example.

4

2c

c

AP ≤

for bwn < fc/2

PM

FM

No/2

-bwn -fm +fm bwn

|Sn(f)|Noise

-fc fc f

4

2cA

|Sc(f)|Carrier

-fc-bwn -fc fc f

4

2cA

|Sosc(f)|

-fc-bwn -fc fc f

|Sosc(f)|


The concepts developed in this section are based on references [Robi91] and [Boon89].Let us consider the addition of our sinousoidal carrier, vc(t), with some broadband noise.

( ) ( ) ( ) ( ) ( )[ ]ttftaAtntfAtv ncncccnc θππ +⋅+⋅=+⋅=+ 2sin)(12sin

(6.6)For values of: vc+n(t) ∈ [-Ac , Ac] we could model every deviation as a phase error, ϕn(t). However it would not be possible toinclude the values exceeding the envelope of the sinusoidal carrier. On the other hand anamplitude error, an(t), can model every value of: vc+n(t) ∈ [-[Ac+maxn(t)] , [Ac+maxn(t)] ]but it would not be able to represent the noise in the time instants that correspond to zerocrossings of the carrier. Therefore the added noise has to be decomposed into amplitude andphase deviations.

Figure 6.3 shows the phasor diagram of vc(t) plus a single tone noise vn(t). The superposed noiseis a narrow band portion of n(t), and equals:

( ) ( ) ( )[ ]nnocnnnnn tffAtfAtv ϕπϕπ ++=+= 2sin.2sin. (6.7)

where fno is the frequency offset between the noise contribution and the carrier. The phase of thecarrier is taken as a reference for the diagram.

Figure 6.3 SSB superposed noise: AM + PM decomposition (phasor)

The right side of Fig. 6.3 shows two pairs of sidebands that explain the amplitude and phasedeviations caused by the superposed noise.We may also express the amplitude and phase deviation, by substituting n(t) by vn(t) in equation(6.6), and developing the corresponding time functions an(t) and θn(t) that express the amplitudeand phase modulation. It follows:

ϕn

fno An

Ac

-An/2

+fno

An/2

Ac /2

-fno

PM

An/2

+fno

An/2

Ac /2

-fno

AM


( ) ( )[ ]

( ) ( )[ ] ( ) ( )[ ]nnoncnnoncc

nnocnccncnc

tfAtftfAAtf

tffAtfAtvtvtv

ϕππϕππ

ϕππ

+⋅⋅++⋅+⋅=

=++⋅+⋅=+=+

2sin2cos2cos2sin

2sin2sin)()()(

Then we compare it to the 2nd form of vc+n in equation (6.6):

( ) ( )[ ]

( ) ( ) ( )[ ][ ] ( ) ( ) ( )[ ][ ]ttaAtfttaAtf

ttftaAtv

nnccnncc

ncncnc

θπθπ

θπ

sin)(12coscos)(12sin

2sin)(1)(

⋅+⋅+⋅+⋅=

=+⋅+⋅=+

Finally assuming An<<Ac and An/Ac << 1 rad, we find:

( ) ( )nnoc

nn tf

A

At ϕπθ +⋅≈ 2sin and ( )nno

c

nn tf

A

Ata ϕπ +⋅≈ 2cos)(

(6.8) (6.9)

This result is represented in a spectrum diagram in figure 6.4. The plot showing the PMcontribution has sidebands with “negative” power. It is in fact a liberty of notation to indicate thesign of the voltage signals that are associated with these sidebands.

Figure 6.4 Superposed Noise: AM + PM decomposition (spectrum)

We may now consider a 2nd SSB noise contribution. When a broadband noise is added to a signalit is very likely that for certain offsets the noise density at both sides of the carrier has a similarlevel. We take two single tone components at frequency offsets of ±fno , that are named vnu(t) andvnl(t) for upper and lower sidebands respectively.

8

2nA

8

2nA

4

2nA

-fc-fno -fc +fc fc+fno f

4

2cA

|Sc(f)| + |Sn(f)|

PM AM


8

2cA


8

2cA


They represent DSB superposed noise: they have equal amplitudes, and opposite frequencyoffsets with respect to the carrier frequency,

( ) ( )[ ]nunocnnu tffAtv ϕπ ++= 2sin. and ( ) ( )[ ]nlnocnnl tffAtv ϕπ +−= 2sin.

(6.10)

The phases ϕnu and ϕnl are random variables uniformly distributed in the range: [0, 2π]Therefore the phase difference between the two sidebands for t=0, is also a random phase with asimilar flat distribution.Figure 6.3 shows us that sidebands that cause exclusively phase modulation, “cross” each otherin a phasor diagram in phases that are in quadrature to the carrier phase. Inversely the amplitudemodulating sidebands “cross” in positions that are in phase with the carrier.The two superposed sidebands , vnu and vnl, have an equal probability of “crossing” either inphase or in quadrature, because of the uniformly distributed phase difference ϕnu-ϕnl. Thereforestatistically, the combined power of these two sidebands is divided into two equal parts: onecausing phase modulation and the other causing amplitude modulation.We can represent this statistical result by two sidebands that “cross” each other at positions witha phase offset of ±(π/4 + π) with respect to the carrier. The peak phase deviation caused by these

two sidebands equals: ( ) c

nn A

At ⋅= 2max θ (6.11)

which corresponds to an increase of 3dB in the phase deviation when compared to the SSBsuperposed noise. We may also see this increase in 3dB as a power addition of the phasedisturbances caused by two independent or uncorrelated noise sidebands.The superposed DSB sidebands are called uncorrelated in reference to their random distributedphase difference; in opposition to the DSB sidebands caused by angular or phase modulation of abase band noise contribution.The modulated DSB sidebands have frequency offsets and phases that are equal in module andwith opposite signs. The type of modulation that causes the frequency translation of the noisepower determines whether this disturbance generates phase or amplitude deviations.In the case of the PLL synthesizer, we are particularly interested in the phase deviations causedby added noise and angular modulated noise. Actually, most of the added noise is propagatedthrough stages that work with strong amplitude limitation. This non-linear behaviour attenuatesmuch of the power of the sidebands that cause amplitude deviations. Therefore it is common torefer to the total sideband noise power as a phase noise power.

Figure 6.5 Phase modulated carrier by DSB superposed noise

( )24

2nA


4

2cA

|Sosc(f)| Two sidebandsSuperposed noise

+ideal limiter ⇒

carrier only phase modulated


Figure 6.5 shows the spectrum of a carrier plus a DSB superposed noise after it has beentransmitted by a stage that eliminates the amplitude modulating sidebands.The SSB phase noise in this case equals:

⋅⋅=

∆⋅=

c

mp

DSBnoA

AfL

2log20

2log20)(

-superposed

ϕ

where ∆ϕp is the peak phase deviation, or as defined in equation (6.11):

( ) c

nnp A

At ⋅==∆ 2max θϕ

Next we compare the phase deviations caused by two types of sideband: superposed and angularmodulated. In order to compare sidebands that have equal frequency offsets and amplitude, wesuppose that the angular modulated sidebands are due to a band base signal vbb(t) that equals:

( ) ( )[ ]nnocc

n

pbb tff

A

A

Ktv ϕπ ++⋅= 2sin.

2

where Kp is the phase deviation sensibility in rad/V.

Figure 6.6 Phase deviation from DSB sidebands

I) Superposed DSB sidebands II) Ang. modulated DSB sidebands

( ) ( )

⋅⋅=−=

⋅≈

⋅=∆

c

nnono

c

n

c

np

A

AfLfL

A

A

A

Aarctg

2log20

22ϕ

( ) ( )

⋅=−=

⋅≈

⋅=∆

c

nnono

c

n

c

np

A

AfLfL

A

A

A

Aarctg

log20

22ϕ

Table 6-2 L(foffset) from modulated and superposed noise

fc -fno

fc +fno

Am Am

Ac

fc

MaximumPhase

deviation

∆ϕp

An An

Ac

∆ϕp

An

Ac

An

Angular Modulated DSB Superposed DSB


The phase noise caused by two superposed sidebands is 3dB smaller than the one caused byangular modulated sidebands with the same amplitude. It is important to notice that thiscomparison has considered a DSB superposed noise with both AM and PM portions. In section6.3 we discuss the transfer of stages that cause amplitude limitation, and their action over theAM portion of the superposed noise.

6.2.3 Slope approach

The results of noise simulations in analog circuits is usually given as a voltage noise density at aspecific node. If this node is part of one of the PLL blocks this noise power may be propagated tothe VCO tuning input, and ultimately it will modulate the frequency of the VCO output.The phase detector and charge pump transform phase deviations in current, and this currentcharges the impedance of the loop filter, and determines the tuning voltage vtune. Therefore if weare able to express voltage noise densities as phase deviations, we may calculate the phase noisein the VCO output that is caused by a certain contribution of voltage noise.

Let us consider a logical or switching stage that has two output values, low and high. Thesestages may work with differential or single ended inputs and outputs. In figure 6.7 we consider adifferential stage, whose output is represented by a single ended output (with an amplitude that istwice the amplitude of each side of the differential output) and a threshold. The instants wherethe signal crosses the threshold are called zero-crossings. The interval between two successivezero-crossings is the period of the signal driving the stage. The variations of this period that aredue to additional voltage noise are called time jitter.

Figure 6.7 Slope approach: voltage & time deviations

The noise voltage Vn(t) is calculated by a small signal noise simulation around a zero-crossinginstant. The result is usually presented as a voltage noise density δvn-rms(f) in [ ]V Hz . The rms

amplitude equals the square root of the power spectral density for the unitary impedance. Thetime deviation is represented by similar functions in the time and frequency domain: ∆tn(t) andδtn-rms(f) in [ ]Hzs .The relationship between the voltage and time deviations is given by the voltage slope of thelarge signal driving the stage. We name vs(t) the output signal and tc the zero-crossing timeinstant; and we start looking at a single tone portion of Vn(t) that we call vn(t). This single toneportion is equal to the SSB superposed noise defined by equation (6.7), and it may also bewritten as a frequency function: ( ) ( )nrmsnn fvtv −↔ δ .

Ts

dvs/dt

∆tn(t)

Vn(t)

tc

2A

differential signal + treshold


The error caused by this superposed sideband at the zero-crossing instants is necessarily a phaseerror. Equation (6.8) shows us the value of the phase error caused by the SSB superposed noise,and it specifies that the phase deviation is a sinus with frequency equals to the offset frequencybetween the superposed sideband and the carrier.Furthermore in section 6.2.1 we saw that phase deviations can be expressed as equivalent timedeviations. Thus the time deviation that is caused by the single tone component δvn-rms(fn)becomes:

=− −

−Hz

s

dt

tdvfv

fftcs

nrmsncnrmsn )(

)()(

δδ

or remembering that cnon fff += ; it follows that:

dt

tdvffv

ftcs

cnormsnnormsn )(

)()(

+= −

−δδ (6.12)

This is the time deviation due to a SSB superposed noise at a frequency offset fno from thecarrier. If the voltage noise density δvn-rms(f) has the same amplitude for the frequencies fc+fno

and fc-fno the time deviation due to a DSB superposed noise becomes:

dt

tdvffv

dt

tdv

ffvffvft

cs

cnormsn

cs

cnormsncnormsnnormsn )(

)(2)(

)()()(

22 +⋅=

−++= −−−

−δδδ

δ (6.13)

Finally the phase deviation due to a time deviation is:

⋅= −−

Hz

radft

Tf offsetrmsn

soffsetrmsn )(

2)( δπδϕ (6.14)

where Ts is the period of the signal, and we indicate the independent parameter as the frequencyoffset to remember that the voltage noise that originates this time deviation is found at fc±foffset.The phase deviation relates the time jitter to the SSB phase noise of the output signal. It followsthat:

( ) ( ) ( )2

:2

log202

log20 prms

offsetrmsoffsetpoffsetdB

fffL

ϕϕ

ϕϕ ∆=∆

∆⋅=

∆⋅=

So for a rms phase deviation given by equation (6.14), it becomes:

( ) ( ) ( )

⋅⋅⋅=

⋅= −−

s

offsetrmsnoffsetrmsnoffsetdB T

ftffL

δπδϕ 2log20

2log20 (6.15)

Equation (6.15) shows the degradation of a periodic signal due to a time deviation. It also showsthat the phase noise is inversely proportional to the period of the signal.


6.3 Large Signal Linearization

The term large signal linearization refers to a transfer function that is calculated around aperiodic steady state of a block with a large signal input. The previous section started discussingthe phase noise induced by a voltage noise that is sampled at the zero crossing moments.Here we search the transfer function for a small signal that is transmitted by a block which isdriven by a large signal input. The large signal is considered as periodic, and the transfer causesamplitude limitations of the output, which appears as a time variable transfer function.vi

The resulting time variable transfer function may be used to explain the frequency translation ofthe noise contributions that are found around the harmonics of the frequency of the signal.

6.3.1 Time and Frequency representation

Let us consider the transfer function of a voltage amplifier that has an ideal limiting output. Itpresents a constant voltage gain for input voltages below a certain threshold and for amplitudesabove this threshold the voltage gain equals zero.Figure 6.8 shows the transfer of a sinusoidal input signal vsi(t) that overdrives the ideal limitingamplifier. The output signal vso(t) has a fundamental harmonic at the same frequency as theinput, but it also has higher harmonics that are generated by the non-linear clipping of the limiter.The transfer function vso(t) / vsi(t) is time variable, and it may be represented in both time andfrequency domains. We call it the periodic large signal (PLS) transfer.The transfer of a small signal that is added to vsi(t) may be calculated making a 1st orderdevelopment of the periodic transfer around the steady-state that is driven by vsi(t). If the smallsignal is represented by a noise component vn(t), it becomes:

( ) ( )[ ] ( )[ ] ( )( )

( ) ( ) ( ) ( )tvthtvtvdx

xdhtvhtvtvh nPLSson

tvxsinsi

si

⋅+=⋅+≈+=

(6.16)

where hPLS(t) is the transfer function for a small signal that is added to the large input signal. TheFourier transform of this time transfer is denoted as HPLS(f), and we use it to define the transferof the small signal when it is represented in the frequency domain;

for

( ) ( )

( ) ( )( ) ( ) ( ) ( )fHfvthtv

fHth

fvtv

PLSnrmsnPLSn

PLSPLS

nrmsnn

⊗↔⋅↔

↔

−

−

δδ

(6.17)

where the frequency domain transfer function is convoluted with the small signal input. Theperiodic transfer for a small signal that is defined by equation (6.17) is linear; since the output of

vi

These ideas are based on the convolution transfer discussed in reference [Boon89]. A similar discussion focusedon oscillators noise can be found in [Haji98].

h[vsi(t)+vn(t)]

vsi(t)

vn(t)h(x)


the sum of two small signals equals the sum of their separate outputs. The supposition of a lineartransfer holds for small signals whose amplitude does not disturb significantly the periodic largesignal transfer hPLS(t).It is important to notice that the time variable characteristic of this transfer causes frequencytranslation of the input signals. For broadband noise contributions the frequency translation alsocauses aliasing or folding. These effects are further discussed in chapter 7.

Figure 6.8 Periodic transfer determined by a large signal

6.3.2 Linear Time Variable transfer

Figure 6.9 shows the periodic transfer functions hPLS(t) and HPLS(f) that are calculated for twotypes of limiting amplifiers: an ideal limiter and a hyperbolic tangent (tanh) limiter. We choosethe hyperbolic tangent because it represents the transfer of a block that appears very often in ICs:the differential stage composed of bipolar transistors.The figure is divided in 6 parts:

A) The input and output signals have a unitary amplitude. The input signal vsi(t) is a sinus curvewith a frequency equal to 0.5 Hz. The output of the ideal limiter is called vso-ideal and theoutput of the hyperbolic tangent limiter is called vso-tanh . The gain at the zero crossing isequal for both limiters, Gc=2. The curves are indicated by the labels: si, ideal, tanh.

input largesignal:vsi(t)

( ) cin

out GdV

dV=

0

Τs/2 =2.fs

Τw =1/fw

t

Vin

Vout

t

Gc

t

Gc.Tw /Ts

-fw fw f(Hz)

Τs=1/fs

amplifier+

idealamplitude

limiter

output largesignal:vso(t)

Timevariabletransfer

function:

hPLS(s)

HPLS(f)


B) The time derivatives of the 3 signals are: dvsi/dt , dvso-ideal/dt and dvso-tanh/dt . The labels arethe same as used in part A).

C) The periodic transfer functions hPLS-ideal(t) and hPLS-tanh(t) are plotted. The functions are

calculated using the approximation: ( )( )

( )( )tdv

dt

dt

tdv

tdv

tdv

si

so

si

so ⋅≈

D) The periodic transfer functions HPLS-ideal(f) and HPLS-tanh(f) are presented. In this plot thefrequency axis is single sided (only positive frequencies).

E) The periodic transfer functions HPLS-ideal(f) and HPLS-tanh(f) are plotted in a larger range offrequencies. The y-axis is in dB, the amplitude value equals: 20.log( HPLS(f) )

F) The curve in solid line shows the difference between the two transfers: HPLS-ideal(f) and HPLS-

tanh(f) . It can be seen that it is the low-pass filtering behaviour that differentiates the ideal andthe tanh limiters. The y-axis is also in dB. The dark gray dashed curve shows anapproximation of the black curve, it is a LPF to the order of 24; and it correctly fits thedifference curve for frequencies above 5Hz. The light gray dashed curve shows a first orderLPF that fits the difference curve for frequencies below 2Hz.

The amplitude limitation of the tanh transfer is smoother than the ideal limiter. The differencemay be represented as a LPF, that has a very steep attenuation slope.The curves of figure 6.9 are calculated with a mathematical model. The actual transfer of a blockof a circuit may be calculated with software for analogic simulations. Particularly for circuitsworking with high signal frequencies and/or very steep signals there is another low-pass-filteringbehaviour that appears to limit the slope of the output signals. This is the slew rate, which isrelated to the biasing of the stage and to the load impedance. Together they determine themaximum slope of the output signal.Recently software implementations have appeared (see reference [Wiel97]) which allow one tocalculate a periodic transfer that is associated with a large driving signal. The periodic transferfunction is very useful to evaluate the noise at the output of strongly non-linear stages.

A simulation example is given in chapter 7, to compare practical and theoretical aspects of theperiodic transfer function.Finally we can observe that for Tw →0, the periodic transfer hPLS(t) approaches a comb sampler.This ideal sampler would completely suppress the AM component of a superposed noise.


Figure 6.9 Large Signal Transfer: ideal and hyperbolic-tangent limitations

A) B)

C) D)

E) F)

si

ideal

tanh

si

ideal

idealideal

tanh

tanh

tanh

tanhideal


This chapter discussed the generation of phase noise due to noise power that is added to a signal,or to noise that causes modulation of a signal. The representation of random electrical noise wasbriefly commented. Different notations were presented and related to the mechanisms of phasenoise generation.The periodic transfer of switching stages was modeled as a time variable transfer function, thatmay be used to calculate the noise at the output of non-linear blocks.

Chapter 7 / Phase Noise in the PLL context 141

Contents:

7. Phase Noise in the PLL context 141

7.1. Translating the SNF into phase, time, voltage and current noise ......................................................... 143

7.2. Sampling effects: SNF x fcp .................................................................................................................. 1477.2.1. Narrow bandwidth noise sources................................................................................................. 1497.2.2. Large bandwidth noise sources.................................................................................................... 151

7.3. Detailing noise sources in different PLL blocks ................................................................................... 1547.3.1. D-flip flop.................................................................................................................................... 1547.3.2. Charge Pump ............................................................................................................................... 158

7.4. Behavioural Models .............................................................................................................................. 1597.4.1. Frequency domain ....................................................................................................................... 1597.4.2. Time domain................................................................................................................................ 160

7.5. Implementation Loss due to Phase Deviations ..................................................................................... 1627.5.1. Signal to noise ratio and implementation loss ............................................................................. 1637.5.2. Digital Demodulator: clock and carrier recovery loops............................................................... 167

Figures:

Figure 7.1 PLL block diagram with signal+noise inputs........................................................................ 142Figure 7.2 Noise Transfer Slopes................................................................................................................ 143Figure 7.3 Synthesizer Noise Floor............................................................................................................ 144Figure 7.4 Sampled Loop Model ............................................................................................................... 148Figure 7.5 Large bandwidth noise folding ................................................................................................ 152Figure 7.6 DFF plus superposed noise in the clock input: time domain signals.................................... 155Figure 7.7 DFF plus superposed noise in the clock input: frequency domain signals .......................... 155Figure 7.8 Charge Pump current noise levels within one period............................................................ 158Figure 7.9 Behavioural model of the PLL for AC and noise simulations .............................................. 160Figure 7.10 Behavioural model of the PLL for transient simulations..................................................... 161Figure 7.11 Digital Demodulator and Decoder .................................................................................... ...... 162Figure 7.12 Noise Power added by the LO sidebands................................................................................ 164Figure 7.13 Behavioural Model of the Carrier Recovery loop................................................................. 167

Tables:

Table 7-1 Data sheet points from: TSA5059 - low noise PLL................................................................ 145Table 7-2 The influence of fcp change for narrow band noise ................................................................ 151Table 7-3 The influence of fcp change for large band noise.................................................................... 153Table 7-4 Implementation Loss X Phase deviations ............................................................................... 166

7 Phase Noise in the PLL context

In this chapter we continue our top-down analysis of the PLL circuit. The results from thepreceding chapters, about the transfer functions of the phase model and about the mechanisms ofphase noise generation, are combined, to analyze the noise contribution of different blocks.Simulations and measurement possibilities that are used to guide the design and the evaluation ofa PLL IC are also discussed.


This chapter combines the results of the previous chapters to develop a numerical analysis of thephase noise of a PLL synthesizer. It starts with the translation of the SNF requirement for noisedensities in phase, time, current and voltage magnitudes. These densities can be compared withthe simulation of the different constituent blocks.The noise densities are affected by the sampling effects of the edge triggered blocks. Thisinfluence is examined, considering the bandwidth of the noise sources. The possibilities todistinguish the dominant noise sources are also discussed. Two examples of simulation arepresented, for a D-flip fop and charge pump design, to illustrate the concept of the periodictransfer.Finally we present behavioural models that enable one to combine circuit and system leveldescriptions in AC and TR simulations. The behavioural model of a digital demodulator is alsopresented. These top level models can be used to examine the total implementation loss that iscaused by the phase deviations in the LO signal. The relationship between the phase deviationsand the implementation loss are presented with a short numerical evaluation. Later in chapter 8,these tools are illustrated by simulations and comparison to measurements.

The following block diagram with signal and noise inputs is used in this chapter.

Figure 7.1 PLL block diagram with signal+noise inputs

The noise inputs are indicated by grey rectangles.Npll is a phase degradation that was introduced in chapter 3 as the synthesizer noise floor (SNF).It is measured in rad/sqrt(Hz), and it is composed of the noise contributions from: the referencechain (crystal oscillator and reference divider), the main divider and the comparator (phasedetector and charge pump).The input vnvco represents the intrinsic noise of the VCO, and, vnf accounts for the noise sourcesof the loop filter. In chapter 4i, we saw that the noise contributions from a loop-filter (from thefilter impedance and the amplifier) are attenuated by the post-filter, and therefore it is practical tosplit these two contributions. Both vnvco and vnf are voltage noise densities given in ( V/sqrt(Hz)).The sketches and expressions below summarize the results from chapters 2 and 3 that are used inthe following sections. In figure 7.2 the noise transfer slopes are indicated for inputs with a whitespectral density.

i See table 4-3 : transfer functions of the disturbances that are related to the active loop filter.

Xosc

(ϕxosc)

÷ R

Npll

Ph. Det.&

Ch. Pump( Kϕ )

VCO( Ko )

÷ N

ϕosc

vnvco

Post-Filter

Zfilter

vnf


( )( )

+

⋅⋅+⋅⋅+

=≈=1

21

)(

2

2

3

3

nn

p

LPFpll

osc

w

s

w

sTs

NsBsB

N ξϕ

( ) ( )

+⋅⋅+⋅

⋅⋅=≈=

12

2

2

1_

nn

oBPFvcovco

nvco

osc

w

s

w

s

CsKsBsB

v ξα

ϕ

and)1( 3p

BPFvco

nf

osc

Ts

B

v ⋅+= −ϕ

Figure 7.2 Noise Transfer Slopes

In chapter 6 we discussed the deviations that are caused by noise contributions which aresuperposed to the signal or which modulate the signal. The superposed contributions cause bothamplitude and phase deviations. When the disturbed signal is propagated through stages thathave a periodic transfer with high gain around the zero-crossing instants and low gain elsewhere,the amplitude deviations are strongly attenuated. Therefore the noise from switching blocks ofthe PLL (Npll) is expressed as a phase deviation.

The sidebands that are found in the output of the VCO are mostly caused by the frequencymodulation of noise power at the input of the VCO. Part of the intrinsic noise of the VCO is notfrequency modulated, but just superposed or amplitude modulated. Nevertheless this part of thenoise is usually not significant. Hence we treat the sidebands of the output of the VCO as angularmodulated sidebands.

Our analysis starts with Npll , translating the phase deviation in voltage, time and currentdeviations. These translations are used to reflect the requirement of phase noise into magnitudesthat are comparable to the outputs of the different PLL blocks.

7.1 Translating the SNF into phase, time, voltage and current noise

The requirement of phase noise for PLL synthesizers is often specified as a maximum phasenoise density at the input of the phase detector. It is a single sideband measurement in dBc/Hz,referring to the noise performance of the in-loop zone of the output spectrum.

( ) ( ) [ ]HzdBc

loopinoffsetdBdBpll NfLN log20min __ ⋅−= (7.1)

The peaking that is indicated in figure 7.3 is the combination of two effects:- the mismatch of the closed loop bandwidth with respect to fi (the intersection frequency for

the asymptotes of the noise performances of the PLL and the VCO);- and the overshoot associated to the closed loop transfer function B(s). This resonant

overshoot is related to the stability of the loop, that is measured by the open loop phasemargin.

0 dB/dec

-60 dB/dec

+20 dB/dec

-40 dB/dec

ϕosc/Npll

ϕosc/vnf

-20 dB/dec

ϕosc/vnvco


It is important to notice that excessive peaking masks the measurement of the in-loop SSB noise(L(foffset) ). Loop filters with a large bandwidth (that assures a closed bandwidth equal or greaterthan fi ) and an elevated phase margin are indicated to perform the measurements of Npll.

Figure 7.3 Synthesizer Noise Floor

The value of Npll is derived from the SSB phase noise, and the latter is related to the peak phasedeviation that is caused by the PLL noise.We would like to express Npll as the equivalent phase and time deviations that would cause thesame LdB(foffset). The deviations are base band components that modulate the VCO output, aspresented in section 6.2.1. We calculate the deviations as noise densities that are denoted as δϕpll

and δtpll .Later on, we relate δtpll to the slope and the period of a carrier signal, and we derive δvpll usingthe slope approach (see section 6.2.3). Finally the sensitivity of the charge pump Kϕ is used totransform δϕpll into a current noise density δiChP .Let us picture these ideas through a numerical example. The values in the table below are takenfrom the data sheet of the Low Phase Noise Frequency Synthesizer, TSA5059 for satellitefrontend applications.ii

ii

A similar analysis for a GSM synthesizer can be found in [Gree95].

peaking

fosc

20.log(N)

in-loopLdB(foffset)

out-loopLdB(ffoffset)

foffset

Npll_dB : Synthesizer Phase Noise floor


Symbol Parameter Conditions Typical value

Npll-dB Equivalent phase noise atthe phase detector input

measured with:fcp = 250 KHz; Icp=1.2 mA

-157 dBc/Hz

IcpCharge pump current

(absolute value)4 programmable values

(2 bits)120 µA / 260 µA555 µA / 1.2 mA

R Reference divider ratio16 programmable values

[indicated as series in the form:(a+2k1).2k2 ]

2 / 4 / 8 / … / 128 / 256 ;24;

5 / 10 / 20 / … / 160 / 320

N Main divider ratio17 programmable bits

+optional prescaler (/2)

w/o presc.: 64 … (217-1)=131071or

w presc.: 128 … 262142

fcp Comparison frequencyfor a 4MHz crystal

directly relatedto R values

2MHz / 1MHz … / 15.625kHz ;166.67kHz;

800kHz / 400kHz … / 12.5kHz

frfRF input frequency

(main divider input ⇒frf = fvco )

Input sensibility+

related to N and fcp values64 MHz - 2700 MHz

Table 7-1 Data sheet points from: TSA5059 - low noise PLL

• The phase noise density at the phase detector input becomes:

Hzrad

rmspllHzdBcrmspll

dBpllN 8_ 10998.1157

2log20 −

−− ⋅=⇒−=

⋅= δϕ

δϕ

In table 7-1 the value of the synthesizer noise floor is referenced to certain conditions of fcp andIcp. The relationship between Npll and the comparison period appears as we look for theequivalent time noise density at the phase detector input.

• Time noise density at the phase detector input equals:iii

Hzs

pllcpcp

rmspllpll ftkHz

TT

t 72.12 and s4250

1for so

2===⋅= − δµ

πδϕδ L

When we compare the same δϕpll to the period of the crystal oscillator, we find a more strictspecification for the time density:

Hzs

XoscXoscXosc

rmspllXosc ftnMHz

TT

t 795.0 and s2504

1for

2===⋅= − δ

πδϕδ L

The values of the time noise densities that are calculated above do not take into account anypossible aliasing effects. Section 7.2 discusses the sampling effects for the noise transfer, taking

iii

From here on the notations δxrms are shortened to δx , but the noise density variables continue to be given in rmsvalues.


into account the noise bandwidth and the sampling frequency. For the moment we may considerthat our phase and time deviations are white band-limited noise densities, with a cut-offfrequency smaller than fcp/2 .

• The voltage noise density at the phase detector:The time noise may be translated into a voltage noise for any logical or switching stage that isdriven by a large periodic signal with a defined voltage slope (dv/dt) at the zero crossings.The output of the dividers and the phase detector itself are polarized with elevated biasingcurrents in order to increase their voltage slopes and decrease their sensibility to voltagedisturbances. The maximum voltage slope of the output of a block is called slew rate. Usualvalues of slew rate for PLL stages with strong biasing are to the order of 1V/ns, or 109 V/s.Under these conditions the voltage noise becomes:

HzVvdt

dv

dt

dvtv rmspllkHzpllpll /72.12 10for s

V9

crossingzero250ffor cp

µδδδ =⇒≈⋅=−

=L

The voltage density is referenced to a time noise, and consequently it is related to the period ofthe large signal driving the blocks under analysis.

• The current noise density at the charge pump output:The specification of phase noise may be translated into a current noise value that is related to thesensitivity of the charge pump Kϕ . Let us consider the minimum and maximum values of Icp intable 7-1, then:

HzpAimAI

HzpAiAI

rmsChP

rmsChP

pllChP Ki/82.3 1,2for

/382.0 120for

cp

cp

=⇒=

=⇒=⋅=

δ

δµ

ϕδϕδ L

• Noise performance of the free-running oscillator:Finally we may estimate the minimum noise performance of the VCO that enables us to assure asmooth transition between the in-loop and the out-of-loop zones of the output spectrum. Thesmooth transition is related to the optimization of the phase jitter σϕ in the output spectrum.

Let us consider the tuner of a satellite receiver, that down-converts the RF input signals from theL-band (950 MHz to 2150MHz) to an IF stage. The intermediate frequency equals 470MHz, andthe frequency of the local oscillator equals fRF + fIF . We suppose a comparison frequency of250kHz. The range of the LO frequency and the counting ratios of the main divider follow:

[ ] [ ]10480;5680250for 2620;1420 ∈→=∈ NkHzfMHzf cpvco K

Next we consider the level of the in-loop sidebands for the maximum closed loop bandwidth.The maximum closed loop bandwidth occurs for the largest open loop gain: α = αmax. Thissituation corresponds to small values of N, and large values of Icp.

iv The synthesizer noise floorin table 7-1 is indicated for the maximum Icp value, so we combine this data with the minimumvalue of N, to obtain the PLL in-loop contribution:

iv

Remembering N

KI vcocp ⋅=α .


( ) ( ) HzdBc

loopinpll fL 825680log20157 −≅⋅+−=−

Chapter 5 discussed the limitation of the maximum closed loop bandwidth for a given fcp value.If we take some practical margin to cope with gain variations (up to αmax/αn =3 ), the following

boundary may be suggested:10

cpol

ff ≤ .

Earlier in chapter 3, we saw that the optimum closed loop bandwidth equals fi ; and that the openloop bandwidth, fol , is related to the closed loop bandwidth, f3dB , by the following expression:

28.063,13 ±≈ol

dB

f

f .

Therefore we may estimate the maximum closed loop bandwidth and the corresponding noiseperformance of the VCO in order to match f3dB with fi . It follows that:

( ) ( ) HzdBc

vcoHzdBc

vcocp

i kHzLkHzLkHzf

f 90100828.408.4063.110

−<↔−<⇒=⋅<

where Lvco is the SSB phase noise of the free-running oscillator.The limit of Lvco that is indicated above would be just enough to obtain a smooth spectrum forα=αmax. Nevertheless if we want to optimize the phase jitter over a range of gain, we shouldconsider using a VCO with a better noise performance. Otherwise if there is no restriction toincrease the minimum tuning step, we may increase fcp and work with higher closed loopbandwidths.

The numerical examples developed in this section are a starting point for the analysis of the noiseperformance of a PLL circuit. They are mostly useful in two circumstances: while translating thespecifications of phase noise of the LO to specific blocks within the PLL; orwhen choosing adequate VCO and PLL circuits to compose a low-noise synthesizer.We continue our analysis looking for parameters that allow us to differentiate the noisecontributions that compose Npll . We will also treat the folding effects due to sampling of theswitching stages.

7.2 Sampling effects: SNF x fcp

We start recalling the discrete model for the PLL that was discussed in chapter 5. It is a phasemodel with an ideal sampler and a zero-order holder. The sampling rate equals the comparisonfrequency of the phase detector, fcp . The sampling accounts for the discrete outputs of thedividers and for the discrete input of the phase detector. The holder represents the charge pump,with a continuous current output.When we introduce the sampling operation in the phase model of the PLL, we obtain thediagram in figure 7.4.


Figure 7.4 Sampled Loop Model

The discrete input of the phase detector ∆ϕn is the same as defined in equation (5.17). It is theoutput of an ideal sampler with a comb shaped spectrum. The Fourier transform of ∆ϕn(n.Tcp) isnamed ∆ψn(w) , and it is analogous to the Laplace transform of ∆ϕn defined in equation (5.16).

( ) ( )∑+∞

−∞=

⋅+∆Ψ⋅=∆Ψn

cpcp

n wnwT

w1 with

cpcp T

wπ2=

The transfer of the ChP as a zero-order holder was defined in chapter 5, equation (5.18), as:

( )( )

⋅

⋅⋅⋅=∆Ψ

−

2sinc2 w

Tjw

cpn

o TweTK

w

wI w

ϕ

where Tw is the width of the current pulse, that outputs the charge pump for a given phasedeviation input.In chapter 5 we used this discrete model to discuss the constraints of stability during an intervalof lock acquisition. For this analysis we used the worst case of the delay for the stabilityconstraint: Tw = Tcp .Here we are interested in the transfer of the noise that appears in the output spectrum of a lockedLO. Therefore the output of the charge pump corresponds to the small pulses that are generatedto compensate the leakage currents and the residual transient currents. For an ideally matchedand leakless case we may consider that the signal output of the charge pump for a locked loop isnull. In what concerns the noise there is a difference. The instantaneous value of the phase noiseat the input of the phase detector is not null, and there is also the noise of the charge pump itself.The noise of the charge pump is related to the reset interval, τrst , during which both currentsources are activated in order to prevent dead-zone problems.v Thus we may consider aminimum Tw=τrst for the locked condition.Most of the synthesizers work with a reset interval much smaller than Tcp , and consequently thecharge pump transfer can be simplified to:

( )( ) cp

n

o TKw

wI⋅≈

∆Ψ ϕfor

rst

wτπ<

v The noise contributions that come from the sinking and sourcing side are added in power, hence their sum does not

equal to zero during the reset interval.

θosc(t)

( )woscΘ

[ ]HzV

io (t)

( )wIo

[ ]Hzrad

Npll

vnvcoXosc

∆ϕn(n.Tcp)

( )wn∆Ψ

∆ϕ(t)

( )w∆ΨTcp

ZOHChP

1/R

ZF (w) Ko/jw

1/N


This simplified transfer holds for frequency values that are within the first lobe of the sinc termin equation (5.18).The combined transfer for the phase detector plus charge pump becomes:

( ) ( )∑+∞

−∞=

⋅+∆Ψ⋅=n

cpo wnwKwI ϕ(7.2)

Equation (7.2) is used to describe the transmission of large bandwidth noise sources, which areeventually aliased by the sampling action of the dividers and the phase detector.vi

In chapter 6, we saw that the transfer of the digital blocks approached this representation of anideal sampler as their gain and/or the slope of the input signals increased. We call the switchingblocks, which are driven by the edges of the input signals: edge driven stages. In fact, increasingthe slope of the edges for a fixed voltage disturbance, decreases the resulting time and phasedisturbances. Therefore in the context of low phase noise synthesizer, we find logical blocks withrather steep edges, with transfers approaching the ideal Dirac comb sampler.Next we examine the influence of the comparison frequency for the noise contributions thatcompose Npll . We start considering narrow band noise contributions that are not aliased bydiscretization, and we continue with large bandwidth noise in section 7.2.2.

7.2.1 Narrow bandwidth noise sources

In section 7.1, we translated the SNF in time, voltage and current noise densities. Here we takethe inverse path, and discuss the total phase deviation that is caused by the voltage and currentnoises from the dividers, the phase detector and the charge pump. We also look for theparameters that may influence the noise contributions of each block, so that comparativemeasurements can be used to identify the dominant noise source in Npll .The total phase deviation of the PLL blocks, δϕpll , is composed of the following noisecontributions:

( )2222

2 222

+

⋅+

⋅+

⋅=

ϕ

δπδπδπδδϕK

i

Tt

Tt

Tt chp

cpphde

cpdiv

cprefpll

(7.3)

where δtref , δtdiv and δtphse represent the time noise densities from the reference chain, from themain divider and from the phase detector respectively. The current noise from the charge pumpis denoted as δichp . The noise densities are a function of frequency, and we simplify theirnotation, from δϕ(f) to δϕ, by supposing that they have white band limited spectra, and that weconsider the same frequency f for all the noise contributions.In equation (7.3) we see just one noise contribution that is independent of Tcp : the charge pumpnoise. However the time noise densities are a translation of voltage densities that are transmittedby edge driven blocks; and the slope of the edges may be a function of Tcp .We may distinguish two extreme behaviours for the voltage slopes with respect to the inputsignal frequency:• Transition slope limited by the slew rate:

vi

We recall that in lock mode the output of the two dividers, and the phase detector work at the same frequency.Therefore the sequence of coherent samplers can be replaced by a single discretization with period Tcp .


The slope of the output is fixed by the slew rate of the block transmitting the signal; dv/dt isindependent of the frequency of the input signal.

( ) ( )max

ttcrossingzero

max0

vdt

tdvcst

dt

tdv ′=

==

=−

This situation happens for stages that are driven by signals with very steep slopes, (the inputslopes are already close to the slew rate), and/or for stages that have a very high gain aroundthe zero crossings.

• Transition slope proportional to the frequency of the driving signal:The slope of the output signal is proportional to the frequency of the input signal.

( )inwA

dt

tdv ⋅==

−0tt

crossingzero

This case appears for stages that are driven by rather smooth inputs. Around the zerocrossings the slope of the input is amplified to an output slope which is not limited by theslew rate. The output slope equals the input slope times the gain around the zero crossing.vii

Table 7-2 examines the case of a voltage noise contribution that is transmitted by two edgedriven stages with the slope characteristics described above. The voltage noise δvn(f) isindependent of fcp , and it is band limited.

( ) [ ]2

for ; cp

HzV

non

ffVfv ≤=δ (7.4)

Equation (7.4) describes a voltage noise density in a single sided frequency spectrum, with onlypositive frequencies. It is a band base noise that modulates the phase of the signal that drives theswitching stage.In the table we observe the influence of a change of fcp , for the phase deviation that is caused byδvn . The phase deviation at the input of the phase detector and also at the output of the VCO areindicated.The change of the comparison frequency is compensated by changes in the divider ratios, R andN, in order to keep a fixed oscillator frequency. The time and frequency noise densities are validfor frequency offsets below fcp/2 .

vii

We may illustrate this case by a sinus input, or a series of harmonic sinus with the fundamental and theharmonics nearly in phase, then:

( ) ( ) ( )∑+∞

=

+⋅++=2

11 sinsinn

ninninin twnAtwAtv ϕϕ and 1ϕϕ ≈n

so ( )

⋅+⋅≈ ∑

∞+

==− 2

1

ttcrossingzero

0n

ninin AnAwdt

tdv


Transitiontype

( )dt

tdv o

[V/s]

wcp

[rad/s]

| δt |

[s/sqrt(Hz)]

| δϕpll |

[rad/sqrt(Hz)]

N | δϕosc |(in - loop)

[rad/sqrt(Hz)]

L(f) x fcp

[dB/fcp_octave]

wcp1max

1 v

Vt no

′=δ δt1.wcp1 N1 Ν1.δt1.wcp1

Slew rateslope

maxv′

2.wcp1 1tδ 2.δt1.wcp1 N1/2 Ν1.δt1.wcp1

0dB/oct.

A.wcp1 wcp1cp

no

wA

Vt

⋅=2δ

A

Vno=2δϕ N1 N1.δϕ2

Proportionalslope

2.A.wcp1 2.wcp1cp

no

wA

Vt

⋅⋅=

222δ

2δϕ N1/2 N1.δϕ2/2

6dB/oct.

Table 7-2 The influence of fcp change for narrow band noise

For the first type of transition with a slew rate slope, a change in fcp does not influence the timenoise, and the in-loop phase noise remains unchanged as the comparison frequency is doubled. Itcorresponds to a constant time noise density with respect to fcp .On the other hand, for the case of proportional slopes, we find a constant phase noise densitywith respect to fcp . The contribution of this phase noise to the in-loop L(f) is directly scaled byN.

We verify that besides the charge pump noise there is a second noise contribution that isindependent of Tcp . Nevertheless these two sources can be differentiated by another parameter:the charge pump sensitivity Kϕ , that is proportional to Icp .The noise of the charge pump is added in the loop after the phase detector sampling; and it islow-pass filtered by ZF before it attains an edge driven stage. We know that for stability reasonsthe bandwidth of the loop-filter is well below fcp/2 ; thus we may consider that the charge pumpnoise is a narrow band contribution suffering from no aliasing effect.So in the next section, which treats large bandwidth noises, we will only look at the time noisedensities of the logical blocks (dividers and phase detector).

7.2.2 Large bandwidth noise sources

Particularly in low noise PLLs, it is common to resynchronize the output of the reference and themain divider to their input signals. This resynchronization means that the output signal is in facta transition of the input signal that is copied to the output. Or in other words, the output of thecounter is triggered by a zero crossing of the input signal. This operation aims to conserve thephase quality of the input and to transmit it directly to the output, avoiding the additional phasedeviations of the counting-cells. The output of a resynchronization stage has a constant slopewith respect to the dividing ratio, since it is determined by the slope of the input signal.Furthermore these slopes are usually limited by the slew rate of the stage.


So next, as we consider the sampling effects for large bandwidth noises, we restrict our analysisto the time noise densities that are related to stages with a constant output slope.

We take the case of a broad band white noise, δvn , at the input of the phase detector. The noisebandwidth equals bwn , with bwn much larger than fcp . We call δvn-cp the voltage noise densitythat is equivalent to a sampled version of δvn .Figure 7.5 illustrates the aliasing of δvn as it passes the ideal sampler.

( ) [ ] nHzV

non bwfVfv ≤= for ; δ

Figure 7.5 Large bandwidth noise folding

The sampling is represented by a convolution product with a comb of rays that are spaced by fcp

intervals. The power density of δvn-cp is increased by the aliasing effect. The multiplying factorbetween the power levels of δvn and δvn-cp is named nlim . It is derived by observing the numberof frequency translated spectra that superpose each other. It follows that:

Nnf

bwnbwbwfn

cp

nnncp ∈

⋅≥⇒≥−⋅ limlimlim with;

2 (7.5)

Approximately, the power of δvn-cp equals 2lim noVn ⋅ for

2cpf

f ≤ . This frequency

boundary is related to a physical limitation. Mathematically the sampling is represented by aconvolution product. Physically, however, a signal that has been sampled at a ratio fcp, can notcontain power in frequencies above fcp/2. This limit equals half the sample frequency and it isalso called the Nyquist frequency.

Therefore δvn-cp becomes:

…

22lim noVn ⋅

…

-bwn -fcp/2 bwn f

-bwn bwn f

22noV

fcp

…

Pvn(f)[V2/Hz]δvn(f )

bandlimitedwhite noise

δvn-cp(f )δvn(f )

Tcp

1

…

Pvn-cp(f)[V2/Hz]


( ) [ ]2

for ; 2

limcp

HzV

cp

nnonocpn

ff

f

bwVnVfv ≤

⋅⋅=⋅=−δ (7.6)viii

Table 7-3 examines the influence of fcp for the phase deviation that is caused by δvn-cp .

Transition type wcp

[rad/s]

δvn-cp

[V/sqrt(Hz)]

| δt |

[s/sqrt(Hz)]

| δϕpll |

[rad/sqrt(Hz)]

N | δϕosc |(in - loop)

[rad/sqrt(Hz)]

L(f) x fcp

[dB/fcp_octave]

wcp1

=2π.fcp1

1

2

cp

nn f

bwv

⋅⋅

1max1

2.

cp

nno

f

bw

v

Vt

⋅′

=δ 11 cpwt ⋅δ N1 111 cpwtN ⋅⋅ δSlew rate slope

( )maxv

dt

tdv o ′=

[V/s]2.wcp1

1cp

nn f

bwv ⋅

1max

1 .2 cp

nno

f

bw

v

Vt

′=δ 112 cpwt ⋅⋅δ N1/2

2111 cpwtN ⋅⋅δ

3dB/oct.

Table 7-3 The influence of fcp change for large band noise

We observe that a broad band noise at the input of the phase detector causes a phase deviationthat depends on the sqrt(fcp). This behaviour results in a change of the synthesizer noise floor of3dB/oct-of-fcp , remembering that the SNF or Npll is directly related to δϕpll in the table 7-3.The SNF change of 3dB/oct-of-fcp is commonly observed in low noise PLL synthesizers.

Let us now compare the transfer of the ideal sampler with the periodic large signal transfer(HPLS(f)_equation (6.17) ) that was discussed in chapter 6:

• HPLS(f) tends to a comb as Tw tends to zero. The comb transfer is a reasonable approximation

for noise bandwidths such as: n

w

bwT

⋅> 21 .

Furthermore the output of the dividers often have a duty cycle that is smaller than 50%,which relatively increases the width of the first lobe of the sinc envelope of HPLS(f) .

• The slew rate of the switching stages is usually determined by the loading of the outputimpedance and the biasing level. It is represented as a low-pass-filter that follows HPLS(f) ,and this post-filtering does not limit the folding effects.

viii

The voltage noise density refers to a spectrum representation with only positive frequencies, explaining thefactor 2 with respect to the double sided (positive and negative frequencies) power spectrum.

( ) 2fH PLS⊗ LPF

Slew rate


7.3 Detailing noise sources in different PLL blocks

The preceding sections discussed the noise contributions that compose the SNF, and therelationships of these contributions to the parameters Icp and Tcp . Here we will look at twosimulations of different PLL blocks to examples the issues discussed above.We choose two blocks that have a different type of noise output: a D-flip flop (DFF) and acharge pump. The first is a basic cell that appears in the three logical blocks: the referencedivider, the main divider and the phase detector. The second has a particular noise contributionthat is not quantified as a time deviation but as a current deviation. The two examples use circuitblocks that are integrated in the testchips discussed in chapter 8.

7.3.1 D-flip flop

The simulation uses a DFF that is implemented in emitter-coupled logic (ECL). The D input ishard set to a logical “1” and we add a small signal deviation at the periodic clock input. The DFFalso has an asynchronous reset input. In the example the reset input alternates with the clock, sothat we obtain a periodic output with the same frequency as the clock frequency. This sequenceof clock and reset signals represents the inputs of one DFF of the phase detector for a lockedloop. The time domain signals are shown in figure 7.6. They are differential signals that refer tothe following voltages and currents:• (VT(“/ck”)- VT(“/ckn”)): differential clock input, with a fundamental frequency equals:

fclk=2MHz. It is a voltage signal. On one side of the input we add a series voltage source witha small sinus output. It represents a superposed noise. The frequency of the superposed toneequals: fn=11.4MHz .

• (VT(“/rst”)- VT(“/rstn”)): reset input. It is a periodic voltage pulse with no addednoise.

• (IT(“/Q10/C”)- IT(“/Q11/C”): differential current signal. It is the current at the collectorsof a pair of transistors that receive the clock input. The tail current in this differential pair isdeviated during the intervals where the reset impulse is high.

• (VT(“/cpon”)- VT(“/cponn”)): Q output of the DFF. It is also a voltage signal. The namescpon and cponn refer to the destination of these outputs, which command the inputs of thecharge pump.

The superposed tone in the clock input causes phase deviations in the collector currents of thetransistors Q10 and Q11. These currents are converted into voltage signals that command therising edge of the output signal. The falling edge of the Q output is determined by the reset input.In order to observe the sidebands that result from the phase deviations, we perform a discreteFourier transform (DFT) of the time domain signals. The spectra are shown in figure 7.7.


Figure 7.6 DFF plus superposed noise in the clock input: time domain signals

Figure 7.7 DFF plus superposed noise in the clock input: frequency domain signals

frequency[Hz]

[seconds]


The settings of the time simulation and of the DFT are carefully chosen to improve the accuracyof the frequency domain plots.The spectrum of the clock input is composed of a sequence of odd harmonics of the fundamentalfrequency: 2, 6, 10, 14 …MHz. There is also a ray that corresponds to the added tone at11.4MHz. We indicate this ray with an ellipse.The differential current signal is the output of a transconductor (the differential pair) that samplesthe input clock signal at every zero-crossing. So the sample frequency equals twice the clockfrequency, or 2.fclk= 4MHz.If we recall the results of section 6.3, we can represent the transfer function of thistransconductor as a periodic large signal transfer: HPLS(f), with rays at 4MHz and its multiples.The convolution product of the input with HPLS(f) should then present rays at the frequencies: ±fn

± n.2.fclk with n ∈ N; or numerically:

MHzMHzn

MHzMHzn

KK

KK

6.8;6.4;6.0;4.3;4.7;4.1144.11

6.8;6.4;6.0;4.3;4.7;4.1144.11

−−−+++⇒⋅±++++−−−⇒⋅±−

This is indeed the result we observe in the spectrum of the current signal.ix The rays due to theinput noise tone may also be seen as time or phase modulated sidebands, as discussed in section6.2.3. The sidebands appear at a frequency offset of ± 1.4MHz around the odd harmonics of fclk .There are also rays at the frequencies n.4MHz. These even rays of the fundamental appearbecause of the pulses that are caused by the reset input.

The differential Q signal has rising edges that are determined by the current signal(IT(“/Q10/C”)- IT(“/Q11/C”). Therefore the Q output samples this current signal every 1/fclk . Sothe output will present rays at: ±fn ± n.fclk with n ∈ N, or in other words it will presentsidebands at ±0.6MHz and ±1.4MHz . This expectation is once more verified by the simulation.Finally we can calculate the expected L(f) of these sidebands and compare it to the level found inthe simulation. We start with the sidebands of the current signal.The peak amplitude of the added noise tone in the clock input equals 25mV. The slope of the

differential clock input equals: ( )s

Vc Mns

mV

dt

tdv16

25

2002 =⋅= , with tc a zero crossing

instant. If we suppose that HPLS(f) is close enough to a comb sampler, the rays that are frequencytranslated at fclk±1.4MHz will present the same amplitude as the ray at 11.4MHz. Therefore wemake an analogy with equation (6.12), and we find the time deviation:

( ) ( ) snM

mVMHztft

sVpeaknoffsetpeakn 5625.1

16

254.1 ==∆=∆ −−

Next we use the relationships between time and phase deviations to find ∆ϕn-peak :

( ) ( ) ( ) radmftff offsetpeaknclkoffsetpeakn 63.192 =∆⋅⋅=∆ −− πϕ

So the L(f) of the sidebands in the current signal are estimated as:

( ) ( )dBc

ffL offsetpeakn

offsetdB 16.402

log20 −=

∆⋅= −ϕ

(7.7)

ix

We remark that figure 7.7 is a single sided frequency representation, so with respect to figure 7.5 the “negative”frequencies are folded in the positive side of the frequency axis.


In the simulation result the sidebands at ±1.4MHz around fclk , have an amplitude that is40.51dB below the amplitude of the fundamental. So the estimation of L(f) in equation (7.7) isquite accurate, which means that our periodic transfer HPLS(f) in this simulation is indeed close toa comb sampler. This result is reconfirmed by the fact that the rays at fn±2.n.fclk all have similaramplitudes within the frequency range that is plotted.If we continue to suppose a comb transfer from the signal current to the Q output, we expect tofind sidebands with an equal amplitude at the frequency offsets of ±0.6MHz and ±1.4MHz. Thelevel of these sidebands should be reduced by 3dB with respect to the sidebands in the currentsignal, because only the rising edges are transmitting the phase disturbances. So the expectedL(f) equals: ( ) ( ) dBcMHzLMHzL dBdB 16.436.04.1 −=±=±

The output of the simulations shows a L(f) of –44.4dBc, which is still reasonably accurate.This example shows that the periodic transfer of added noise sources can be accurately estimatedby the large signal linearization (transfer represented by HPLS(f)). The numerical applicationholds even for rather large perturbations such as the superposed tone used in this simulation.

In a PLL that has resynchronized dividers, we may concentrate our attention on a few nodes todetermine the total time noise density that is transmitted to the phase detector input by the logicalblocks. Once more the logical blocks are the phase detector, the reference and the main divider.If the resynchronization stages and the phase detector are composed of DFFs that have similarbiasing levels, we can try to find the one that represents the critical path with respect to the noiseperformance. It is often the reference chain, due to the broad band noise floor that outputs thecrystal oscillator (Xosc). If we consider that the output of the Xosc has a buffering stage that israther non-linear, with steep edges and Tw tending to zero; the broadband noise is then sampledto a Nyquist bandwidth equal to fxosc . Later on it is down-sampled by the resynchronizationstage, which causes a new folding to a Nyquist bandwidth of fcp/2 . Equation (7.5) can be used todefine a folding factor nlim for the noise coming from the Xosc. It equals:

Rf

f

f

bw

f

bwn

cp

xosc

cpsample

Xoscn

cpNyquist

Xoscn ⋅=⋅

=⋅

==−

−

−

− 222

lim (7.8)

where R is the dividing ratio of the reference divider.The noise of the Xosc that is transmitted to the phase detector input is then estimated usingequation (7.6). It becomes:

( ) [ ]2

for ; 2 liminputdetector

phase at thecp

HzV

nonoXoscn

ffRVnVfv ≤⋅⋅=⋅=−δ

(7.9)

The noise contribution of this broad band noise has a 3dB/oct-of-fcp behaviour as discussed intable 7-3. The value of Vno can be obtained by noise simulations using software that calculate aperiodic transfer for the noise.


7.3.2 Charge Pump

The simulation concerns a phase detector and a charge pump blocks that were designed to workwith very high comparison frequencies, to the order of 310MHz. It is part of a multi-loop PLLstructure that is discussed in chapter 8.The inputs of the phase detector are adjusted to correspond to a locked loop situation with anaverage current output equal to zero. Due to the elevated comparison frequency the charge pumpthat has slow pnp current sources, acts like a low-pass filter. The output currents sinking andsourcing are a filtered copy of the input impulses of the phase detector. We know that theminimum width of these impulses equals τrst . Here the ratio τrst/Tcp approaches 1/3 andconsequently the current sources are never completely switched off. Therefore the noisecontribution of the charge pump block can become very significant for the total phase noiseperformance.A series of noise simulations is realized around different points of a time domain simulation. Thepoints are chosen within an interval of one period, and, after the transient signals have attained aperiodic steady state, this corresponds to the locked-loop condition.The current noise densities that were calculated for the different transient points had roughly awhite band-limited shape with a cut-off frequency around 30MHz. The level of the current noisedensity at a frequency of 1MHz is sketched in figure 7.8. It corresponds to an instantaneousvalue calculated for a given time instant in a period. We indicated it as:δiChP-instant(1MHz) .

Figure 7.8 Charge Pump current noise levels within one period

In figure 7.8 the peak of noise level occurs during the zero crossing of the inputs that commandthe charge pumps. The total noise contribution of the charge pump is a time average of theinstantaneous noise power levels. Here it becomes:

( )

( ) ( ) HzA

n

np

n

np

T

Ti

T

TiMHzi

cpinstChP

cpinstChPtotalChP

22222

222.

121.

2

10.768.92.32

150.0140

2.3

9.28

...1

−

−−−

=⋅

⋅+⋅≈

+⋅+⋅= δδδ

The current density is transformed into a phase density using Kϕ , and finally expressed as a SSBphase noise, as follows:

300ps

t[s]

140p

8p

δiChP-instant(1MHz)A/sqrt(Hz)

n.Tcp (n+1).Tcp

δiChP-instant(f)

8p A/sqrt(Hz)

f[Hz]30M

Tcp=3.2ns

Icp=182uA


( )Hz

radp

K

iMHz totalChP

totalChP µπµ

δδϕϕ

079.12182

25.311 =⋅== −

−

( ) ( )Hz

dBcMHzMHzL totalChP

totalChPdB 35.1222

1log201_ −=

= −

−δϕ

This calculation is useful to estimate the limitation of the noise performance that is imposed bysuch a charge pump working with a high fcp . The calculation is compared to measurementresults in chapter 8.

7.4 Behavioural Models

The behavioural model is a synthetic form to represent different blocks of a circuit. It is used tosimulate an ensemble of blocks that interact among each other. Often they become interestingwhen a simulation using the full circuit description would demand too much memory and/or time. We may model all the circuit blocks in behavioural descriptions or combine behavioural andcircuit level descriptions. The following sections present briefly some points about a behaviouralrepresentation of the PLL synthesizer, for simulations in the time and in the frequency domains.Numerical examples are presented in chapter 8 while discussing the results of the testchips.

7.4.1 Frequency domain

A behavioural description of the PLL may represent the output of the VCO and the Xosc bytheir respective phases. This phase model greatly simplifies the representation of the dividers thatmay directly divide the phase values instead of identifying and counting zero-crossing moments.The PLL phase model that was presented in figure 2.1, is very close to a behavioural model thatmay be used for AC and noise simulations. In an analog simulator the phase signals have to betransformed in either voltage or current magnitudes. We choose to represent the phase signals asvoltages. The dividers are replaced by voltage controlled sources that have an output equal to1/N or 1/R times their input.The integration of the phase model of the VCO is represented by measuring the ddp of acapacitor that integrates a current. For a noise simulation we introduce two noise sources thatrepresent Npll and vnvco . In figure 7.9 the noise input of Npll is replaced by a source thatrepresents the noise of the crystal oscillator. The aliasing factor sqrt(2.R) is also included throughthe gain block that follows the noise source. The loop filter is an active one. The amplifier isrepresented by a transconductor with a capacitive input impedance, and the output impedanceequals the pull-up resistor.This model may also be used for AC simulations that verify the open and closed loop transfers.


Figure 7.9 Behavioural model of the PLL for AC and noise simulations

The output PHIvco (ϕvco) in this behavioural model may be used to calculate the total phase jitterof the LO signal. In fact ϕvco equals the mean square phase fluctuation Sϕ(f) (equation (3.5) ).The total phase deviation or phase jitter, σϕ , is then derived by integrating Sϕ (equation (3.21) ).The boundaries of the integral are related to the bandwidth of the channel that is being down-converted.In section 7.5 we continue to discuss these integration boundaries as we consider theimplementation losses that are caused by σϕ .

7.4.2 Time domain

The behavioural representation in the time domain also uses phase models for the dividers.However it is interesting to represent the phase detector and charge pump in a form that iscompatible with their circuit description, so that we may combine behavioural and circuit blocks.


Figure 7.10 shows a combined model that contain behavioural descriptions for the dividers andphase detector, and a circuit level charge pump and loop-filter amplifier. This schematic is usedto observe the transient residual currents that are due to mismatches between the sourcing andsinking sides.

Figure 7.10 Behavioural model of the PLL for transient simulations

The accuracy of simulations in the time domain is closely related to the ratio time-step/signal-period. The time step is the space between two consecutive points that are calculated in thetransient simulation. In an ensemble of blocks that work with different frequencies, we shouldconsider the smallest period.The difficulty to simulate the full PLL circuit is connected to the large difference between theperiod of the signals at different points of the loop. In this transient model we reduce thisdifference of periods changing the parameters Kvco and N. In fact the VCO is represented by itsphase and this phase is divided before it is re-transformed into a sinusoidal signal. Therefore wemay simply divide Kvco and N by a common factor, and reduce significantly the differencebetween the comparison frequency and the frequency of the VCO.


7.5 Implementation Loss due to Phase Deviations

Implementation loss is the difference between the theoretical limits that are calculated for thecorrect functioning of a system and the limits that are measured in a physical implementation.Here, we discuss the implementation loss that is caused by the phase deviations in the LO signal.The numerical values are related to the reception of a QPSK modulated channel in a satellitereceiver.

In the frontend or more specifically in the frequency conversion stage, the phase jitter of the LOadds noise to the RF data being down-converted.The circuit that receives the BB output from the frontend is a digital demodulator and decoder(see figure 7.11). The first part, demodulator, is composed of the following blocks: ADC, clockrecovery loop and carrier recovery loop. The decoder is the second part, and it contains thestages of forward error correction.

Figure 7.11 Digital Demodulator and Decoder

For digital modulations, the final consequence of phase jitter is measured as a bit-error rate(BER)x. In the case of QPSK signals the bit error rate reflects the probability that the additionalphase noise exceeds a value of π/4 .xi

Thus, for phase noise contributions that present a Gaussian distribution and a mean square valueor variance of σϕ , we can calculate the BER using the distribution curves of a Gaussian variable.Usually these results are presented in graphs of SNR versus BER. They show the theoretical andminimum signal quality that is required todecode the input signal with a certain amount of bit-errors. The SNR is often indicated as apower density ratio: energy per bit over noise, Eb/No , that normalizes the signal power withrespect to the bit rate.The decoder can correct a certain number of bit errors depending on the redundancy and therobustness of the coding. MPEG standards for video coding impose BER to the order of 10-11 atthe output of the decoder. For the satellite DVB-S that has an inner Reed-Solomon coding and anouter Viterbi coding; this implies a BER to the order of 2.10-4 at the input of the Reed Solomon

x The BER is a common unit used in the context of digital decoders. It measures the amount of errors encountered in

the reception of a bit stream.xi

Referring to a constellation diagram, as represented in figure 1.7 .

SDD: satellite demodulator and decoder

Frontend

Forward Error Correction

ViterbiDecoder

Reed-SolomonDecoder

Demodulator

ADC Clock & CarrierRecovery Loops

RFinput

LO

PLL


decoder, and a BER to the order of 6.10-3 at the input of the Viterbi decoder. The BER in theinput of the decoder is also called raw BER.Using the theoretical curves of SNR x BER for QPSK signals we find that the raw BER of 6.10-3

is equivalent to a theoretical Eb/No of 5dB. We may also express the SNR as an energy persymbol instead of an energy per bit, which gives us a Es/No of 8dB. The implementation loss ismeasured as the increase in the ratio Es/No which is required to obtain a raw BER of 6.10-3 .

7.5.1 Signal to noise ratio and implementation loss

The following treatment of the implementation loss and phase noise power is based on thereference [Sinde98b].Let us consider the signal and noise powers indicated in the schematic below:

where Ps : signal power measured within the bandwidth bwch ; PNin : noise power before the mixing stage, also measured within bwch ; PNϕ : noise power added by the phase noise of the LO, measured within bwch .

For an ideal receiver working with a noiseless local oscillator, SNRin and SNRmin are equal, andthey become:

1

1minNin

sin P

PSNRSNR ==

where PNin1 is the maximum noise power that can be handled by the receiver.When we consider a noisy LO the SNRmin equals:

ϕ

ϕϕ

SNRSNRP

P

P

PPP

PSNR

inss

NinNNin

s

1111

2

22min

+=

+=

+=

where PNin2 is the maximum noise power at the input, in the presence of the phase noise PNϕ ; andSNRϕ is the signal to noise ratio for the phase noise contribution.The implementation loss (IL) due to PNϕ is defined by the ratio of the input SNR for the noisyand noiseless cases:

ϕSNR

SNRP

P

SNR

SNRIL

Nin

Nin

in

in

min2

1

1

2

1

1

−===

It may also be expressed in dB as:

−⋅−=

− −−

10min

101log10dBdB SNRSNR

dBILϕ

(7.10)

where SNRmin-dB and SNRϕ-dB are the same ratios defined above, but expressed in dB.We can also calculate the SNRϕ which corresponds to a given IL and SNRmin. It equals:

SSNRminPs

PNin PNϕ


1min −

⋅=IL

ILSNRSNRϕ

or expressed in dB:

−⋅−+=

−− 110log10 10min

dBIL

dBdBdB ILSNRSNRϕ (7.11)

Let us now consider the relationship between SNRϕ and the phase noise parameter Sϕ(f) whichwas introduced in chapter 3. The latter is a noise to signal ratio, that considers the noisecontribution of a 1 Hz bandwidth in a certain offset from the carrier. The first one is a signal tonoise ratio that considers the noise within the bandwidth of the selected channel (bwch). So, weexpect the integral of Sϕ(f) to be related to SNRϕ

-1 .Indeed, if we consider the phase noise sidebands as narrow band noise contributions that are alsodown-converting the input channel, we find that:

( ) ( ) offset

bw fbw

fbw

fbw

chs

N dfdffSdffSbwP

PSNR

choffset

ch

offsetch

offsetch

∫ ∫∫

⋅+⋅==

+

−

−

−2

0

2

2

2

0

1

2

12ϕϕ

ϕϕ

(7.12)

1−− foffsetSNRϕ

where the noise being added corresponds to the frequency-shifted copies of the input channel.We should remember that Sϕ(f) is the double side band phase noise, which explains that theboundaries of the integral are limited to positive offsets.Figure 7.12 gives a physical idea of the integral above. It shows the noise contribution that isbrought by two narrow sidebands around the oscillator frequency.

Figure 7.12 Noise Power added by the LO sidebands

∆f1 foffset

∆− 12

fbwch

∆f1

Ss(f)[W/Hz]

f [Hz]

bwch

Sosc(f)[W/Hz]

f [Hz]

∆+ 12

fbwch

f [Hz]f [Hz]

SBBoutput(f)[W/Hz]

SBBoutput(f)[W/Hz]

foffset


The outermost integral in expression (7.12) sweeps the channel bandwidth from its center to oneof the extremities. The inner integral evaluates the noise power that is projected over eachnarrow bandwidth portion of the channel spectrum. The noise amount that is projected on twosidebands that are equally spaced with respect to the center of the channel bandwidth, is equal.Therefore the outermost integral just needs to sweep a range of one half channel.However, depending on the position of the narrow bandwidth within the channel spectrum, it is adifferent range of the DSB phase noise, Sϕ(f), that down-converts or projects noise. For offsetsclose to the center of the channel, or for foffset << bwch , it is basically Sϕ(f) in the range [0,bwch/2], where the DSB phase noise accounts for the left and right sided offsets from the centerof the channel. For offsets close to the extremities of the channel, or for foffset ~ bwch/2 , it isSϕ(f)/2 in the range [0, bwch].In expression (7.12), the total noise, PNϕ , is the sum of the noise contributions that are downconverted by the sidebands around the LO. In the present case, where we consider a singlechannel at the RF input, the maximum frequency offset for these sidebands equals bwch .Next, two particular cases, concerning random and spurious sidebands, are discussed.

7.5.1.1 Spurious Sidebands

Discrete spurious sidebands are also contributing to PNϕ . If we consider a pair of sidebands at afrequency offset f1, the DSB phase noise can be expressed as:

( ) ( ) [ ]2111 radffPfS s −⋅= δϕ for chbwf << 10

where Ps1 is the DSB spurious amplitude. It may also be expressed in dB, Ps1-dB , and comparedto As , the SSB spurious amplitude defined in equation (3.2).

[ ]dBcdBAP sdBs 31 +=− (7.13)

Then, replacing Sϕ1 in expression (7.12) results in:

[ ]211

11 1 rad

bw

fPSNR

chs

−⋅=−

ϕ for chbwf << 10

[ ]21

11max radPSNR s<−

ϕ (7.14)

Therefore Ps1 is an overestimation of the SNR related to these single tone sidebands.

7.5.1.2 Random Phase Noise

The random noise sources that modulate the tunable oscillator cause sidebands that are measuredby a phase noise density, Sϕ(f). These sidebands may be divided into two zones. The first, in-loop, is mostly flat with some peaking close to the intersection of the out-of-loop zone. In thesecond one, the power of the sidebands decreases with a 1/f slope. The PLL closed bandwidth(fcl) determines the size of the in-loop zone.Most of the phase deviation power is due to the sidebands that are found in frequency offsets inthe range [0 , fcl ] .


In most of the tuner applications, the PLL bandwidth is considerably smaller than the channelbandwidth (bwch) . Thus the parameter 1−

− foffsetSNRϕ in expression (7.12) is bounded by:

( ) [ ]22

0

10_

1_ raddffSSNRSNR

chbw

foffset ∫=≤ −−ϕϕϕ

Furthermore the value of 1−− foffsetSNRϕ is rather close to 1

0−

−ϕSNR for all the frequency offsets that

are in the range: [0 , bwch-fcl ] .If we replace 1−

− foffsetSNRϕ by 10

−−ϕSNR in equation (7.12), we obtain a simplified form of 1−

ϕSNR

that equals:

( )∫∫ ===⋅≈ −−−2

0

210_

2

0

10_

1 2chch bw

offset

bw

ch

dffSSNRdfSNRbw

SNR ϕϕϕϕϕ σ (7.15)

Expression (7.15) is an overestimation of 1−ϕSNR for the random noise sidebands; and it equals

the square of the phase jitter, for an integration within half of the channel bandwidth.

7.5.1.3 Numerical Example

The specifications of a receiver system define allocations of implementation losses for thedifferent parameters causing signal degradations. In TV and satellite tuners the implementationloss due to phase deviation of the LO are specified by a maximum value of 0.2dB.We can use expressions (7.10) and (7.11) to calculate some numerical examples for the satelliteQPSK receiver. Table 7-4 relates SNRϕ and IL for a Es/No of 8dB, corresponding to the raw BERof 6.10-3 .

ILdB SNRϕ-dB 1−ϕSNR 1−

ϕSNR

[dB] [dB] [rad] [°]

1.6 13.112 2.210E-01 12.662

0.8 15.741 1.633E-01 9.356

0.4 18.556 1.181E-01 6.766

0.2 21.467 8.446E-02 4.839

0.1 24.428 6.006E-02 3.441

0.05 27.413 4.259E-02 2.440

0.025 30.411 3.016E-02 1.728

Table 7-4 Implementation Loss X Phase deviations

We may also use expressions (7.13), (7.14) and (7.15) to relate the values of SNRϕ with thespurious level (As) and the phase jitter (σϕ) .For instance the implementation loss of 0.2 dB is equivalent to a phase jitter of 4.84°, or to asingle pair of spurious sidebands at – 24.5 dBc.


In practise the maximum 1−ϕSNR has to take into account both the phase jitter and the spurious

power. Hence we should seek a practical boundary that compromises the phase deviation of therandom and spurious noises and also preserves a margin for variations in the parameters thatdetermine As and σϕ .xii

A phase jitter of 2° and a spurious level below –36dBc is a compromise that implies a totalSNRϕ-dB of 28.2 dB,with a margin of 6.7 dB for the variation of the total phase deviation.

7.5.2 Digital Demodulator: clock and carrier recovery loops

Finally we need to consider the action of the demodulator blocks (carrier and clock recoveryloops) for the phase deviations that come from the frontend.There are different configurations of carrier and clock recovery loops, our model is based on thearchitecture of the circuit TDA8043, a satellite demodulator and decoder for BPSK and QPSKsignals.The behavioural model for the phase transfer of the clock and carrier recovery loops is shown infigure 7.13.

Figure 7.13 Behavioural Model of the Carrier Recovery loop

The two loops are based on PLLs of the 2nd order. The clock recovery loop is the external, slowloop, which works with the smaller closed loop bandwidth. There are three stages that arecontained in the clock recovery loop: the anti-alias filtering, the Nyquist filtering and theinterpolator. These stages are only represented by the delays that they cause in the signal path(block delay_2). The length of this delay depends on the symbol rate.

xii

The spurious level, As , depends on the amplitude of the modulating signal, on the frequency sensitivity of theoscillator (Kvco), and on the suppression of the loop filter. The phase jitter, σϕ , depends on the noise performance ofthe PLL and the VCO ( Npll , vnvco ), on the peaking of the closed loop transfer and on the closed loop bandwidth.

Clock recovery loop Carrier Recovery loop


There are other delay elements that account for the phase detectors functioning. These delays areindependent of the symbol rate.The carrier recovery loop is the internal, fast loop. The bandwidth and damping parameters ofeach loop are programmable. In the behavioural model these settings are translated to the loopfilter parameters that correspond to a 2nd order closed loop transfer with a natural oscillatingfrequency wn and a damping ξ .The ensemble of the demodulator blocks is synchronous, and it works with a clock at 65MHz.Therefore the delays may be normalized as an entier number of periods of the reference clock.

The TDA8043 can decode channels with variable symbol rates. The maximum symbol rate thatcan be decoded is 32Msps. For symbol rates below 10Msps, the loops should be interlaced (anexternal clock loop containing the carrier loop) as represented in figure 7.13. For symbol ratesabove 10Msps, the two loops should be connected in series. For the phase model, the seriesconnection just changes the feedback return for the clock recovery loop, which would be takenfrom the node at the input of the carrier loop.The overall transfer of the demodulator is very close to a high pass filter of 2nd order, with acutting frequency that equals the natural frequency of the fast loop. As we increase thebandwidth of either loop, the effect of the delays will become visible, causing some overshoot inthe transfer.

The phase model of the demodulator is used in noise simulations in combination with the PLLphase model. The demodulator input (PHIdemin) receives the phase noise density that outputsthe PLL. The output of the demodulator is a high-pass filtered portion of ϕosc.The combined PLL+demodulator model is used to calculate the phase jitter that appears at theinput of the digital signal decoder. In this manner, the IL that is measured at the input of thedecoder, can be correctly compared to a phase jitter value. Simulation examples are presented inchapter 8.

In this chapter we applied the results of the preceding parts, about the PLL model and the relatedtransfer functions, and, about the generation of phase noise.The analysis of a PLL design, in a top-down approach, was discussed with numerical examplesrelated to existing ICs.A systematic approach to investigate the dominant noise sources was presented, with suggestionsfor simulations and measurements.Finally, behavioural models for transient and AC simulations were briefly described. A modelfor a QPSK demodulator, used in the analysis of chapter 8, was also introduced.

Chapter 8 / Testchips Realized 169

Contents:

8. Testchips Realized 169

8.1. Gm-C oscillator..................................................................................................................................... 1708.1.1. Structure ...................................................................................................................................... 1708.1.2. Results ......................................................................................................................................... 172

8.2. TC2 : Mixer-Oscillator-PLL circuit for satellite direct conversion ..................................................... 1738.2.1. Double Loop Synthesizer ............................................................................................................ 1738.2.2. TC2 structure ............................................................................................................................... 1758.2.3. TC2: results ................................................................................................................................. 177

8.3. TC3 : single PLL plus QCCO circuit .................................................................................................... 180

8.4. Comparative analysis: phase jitter and implementation loss................................................................ 1838.4.1. Configurations compared ............................................................................................................ 1838.4.2. Conditions for the simulations..................................................................................................... 1848.4.3. Results and conclusions............................................................................................................... 187

Figures:

Figure 8.1 Gm-C integrated oscillator .......................................................................................... ............ 171Figure 8.2 Double loop MOPLL: block diagram..................................................................................... 174Figure 8.3 Block diagram of TC2 .............................................................................................................. 176Figure 8.4 Photo of a testchip TC2............................................................................................................ 177Figure 8.5 TC2 _ in-loop spectrum for N1=7 and fcp1=300Mhz............................................................. 179Figure 8.6 TC2 _out-of-loop spectrum for N1=6 and fcp1=300MHz ...................................................... 179Figure 8.7 TC3 _ single low noise PLL plus QCCO................................................................................ 181Figure 8.8 Simulation result for the SSB phase noise _ linear scale ....................................................... 182Figure 8.9 Spectra for ∆fstep =125kHz and flo =900MHz .......................................................................... 186Figure 8.10 Phase noise simulation for DL+QCCO with and without demodulator .............................. 186

Tables:

Table 8-1 Measurements of the frequency coverage of the QCCO....................................................... 172Table 8-2 Double Loop: minimum step and comparison frequencies................................................... 175Table 8-3 Parameters of the two zero-IF configurations being compared ........................................... 183Table 8-4 Parameters and outputs for comparative analysis ................................................................ 184Table 8-5 Settings of the demodulator block........................................................................................... 185Table 8-6 Phase Jitter and implementation loss for rs=30Msps and fLO = 2,2GHz.............................. 188Table 8-7 Phase Jitter and implementation loss for rs=3Msps and ∆fstep = 125kHz............................. 188Table 8-8 Margin for degradations in the oscillators phase noise performance .................................. 189

8 Testchips Realized

This chapter presents two synthesizer testchips which contain a fully integrated Gm-C oscillatorcovering the satellite band-L. The synthesizers are designed for a monodyne or zero-IF receiver,and they present a multi-loop architecture.The structures of the Gm-C oscillator and a double loop PLL synthesizer are exposed in tablesand block diagrams. The performance of the double loop synthesizer, with an integrated satelliteband oscillator, is compared to a classical single loop and external LC oscillator. Finallymeasurement results of phase noise and implementation losses are compared to simulations.


A fully integrated oscillator becomes quite interesting in monodyne receivers where the radiationof the input RF signal may significantly deviate a LC externally-coupled oscillator.In terrestrial and satellite tuners the usual range of the tuning voltage is 30V. This high voltagesupply can be suppressed if the LO can be tuned under a 5V range.The integrated Gm-C oscillator has a range divided into 4 bands that are tuned in a 5V range. Itsphase noise is on average 20dB worse than a LC oscillator covering the same range with a 30Vtuning range. The solution, to cope with the degradation of the phase noise, is to increase theclosed loop bandwidth. In order to respond to both the specifications of a maximum tuning stepand a minimum closed loop bandwidth, a multi-loop structure is needed.The first testchip that is discussed, TC2, is an implementation developed in collaboration withNat.Lab. the research laboratory of Philips. It is a double-loop PLL synthesizer. The first loopdrives an oscillator in the VHF band, which is used as the input reference for the second loopwhich drives the Gm-C oscillator. The two oscillators are tuned in a 5V range.The second testchip, TC3, exploits the possibility of a single loop, with a wide closed bandwidth,to drive the same Gm-C oscillator. The input reference in this case is a crystal oscillator.The testchips were realized in a bipolar process that is derived from a BiCMOS process. Thestripped bipolar process kept the gate oxide of the CMOS components for the capacitors. Thisenables us to compose a native PMOS, which gives us a bipolar+PMOS process. The peak valueof the ft of the NPN transistors equals 13GHz. The maximum ft of the lateral PNP equals200MHz. There are three levels of metallization, with a pitch of 2.4µm.We start describing the results of the Gm-C oscillator, which is a common block in the twotestchips. A fuller description of the double loop structure and the Gm-C oscillator can be foundin references [Vauc98] , [Tang97] and [Kokk92].

8.1 Gm-C oscillator

The Gm-C oscillator is a ring structure with two integrator stages and an inverting feedback. Thetwo stages have outputs with an equal frequency, and phases that are shifted by 90° with respectto each other.i The oscillating frequency depends on the value of the capacitors and on thetransconductance Gm. The frequency tuning is made by varying the biasing current of thetransconductance stages. Hence the oscillator is also called a QCCO: quadrature currentcontrolled oscillator.

8.1.1 Structure

Let us consider the block schematic of figure 8.1. It shows the basic parts of the QCCO. Part8.1.a presents a single ended integrator stage. The transconductance gma compensates the current i These quadrature outputs are very convenient for a receiver with a monodyne structure. A monodyne receiver

needs to provide two outputs, in quadrature to each other, so that the demodulator can distinguish the channel fromits mirror image. In a zero-IF architecture the mirror image is a flipped version of the selected channel, which is alsoconverted to base band.Basically there are two possibilities to provide the two outputs in quadrature: either phase shifting the input RFchannel, or having a LO oscillator with quadrature outputs. The second solution is often chosen because it demandsa phase shifter for a single tone signal, instead of a large bandwidth shifter.Furthermore the digital standards of satellite broadcasting use QPSK modulation. Therefore the quadrature outputsmay be directly sampled and demodulated to retrieve the I and Q streams of data.


losses in the resistor R, keeping the quadrature between the input and output voltages vin andvout . Implementation in the testchips uses differential transconductances gmt and gma as draftedin figure 8.1.b.

Fig.8.1.a Single ended Gm-C integrator Fig.8.1.b Differential cascaded integrators

Figure 8.1 Gm-C integrated oscillator

The condition of oscillation, a unitary feedback with a phase shift of 360° , is met by cascadingtwo integrator stages and an inversion. In the differential scheme the inversion is simply acrossover between the feedback signals.If the transconductance gma compensates exactly the losses of each integrator stage( )Rgm a

1−= , the closed loop transfer function for a voltage input becomes:

( ) 2

1

1

⋅+

=

t

QCCO

gm

CssB (8.1)

where the transfer of a single integrator is :( )( ) n

t

in

out wCs

gm

sV

sV =⋅

= ;

which is also equal to the natural oscillating frequency wn .This situation is identified as the linear mode of the QCCO. In practice an amplitude control, thatacts on gma , is needed to assure a minimum negative impedance during the start up of theoscillator and later on to fix the value of the amplitude.The phase noise performance of the QCCO depends: on the inherent noise sources, on thefrequency sensitivity of the oscillator and on the amplitude of the signals VI and VQ .We can define a frequency sensitivity Kcco in Hz/A .If we decrease Kcco by increasing the capacitors C, we will need a higher Igmt to cover thefrequency range, which implies an increase in some noise sources that are proportional to thebiasing currents.On the other hand, as we increase the amplitude of the oscillating signal the transconductors gmt

will no longer work in a linear mode, and the losses due to this non-linear function have to becompensated by the negative resistance, or in other words by increasing Igma .

C R

Igmt

gmt

voutvin

Igma

gma

vQvIgmt (tune)gma (amp)

gmt (tune)gma (amp)

Igmt Igma IgmtIgma


In fact Igma is already the parameter that controls the amplitude, and, for oscillators working in anon-linear mode the amplitude control is also influencing the frequency. Therefore the design ofthe QCCO is a tricky compromise between the requirements of phase noise, tunable range andconsumption budget.

8.1.2 Results

The QCCO implemented in TC2 and TC3 has a frequency range divided into 4 bands. The bandsare selected by programmable inputs. The frequency range covers the entire band-L from950MHz to 2150MHz, with some overlap in the extremities and in between each band. Theoutputs VI and VQ have a peak value to the order of 200mV to 300mV. This amplitude representsthe result of the compromise between consumption and phase noise performance. The ensembleof the biasing and transconductance blocks consume 26mA under a 5V bias.The first design was reworked to improve the band coverage and the uniformity of the Kcco andthe L(f) throughout the 4 bands.ii The measurement results are presented in table 8-1, incomparison to the ideal band partition shown below. The overlap for the limits of each band ischosen as 100MHz.

Ideal band partition:

MHzMHzf 4254

3008502250band =+−=∆

Measurements:

Band 1 Band 2 Band 3 Band 4 measurement conditions:

FrequencyRanges[MHz]

815|

1230

1190|

1640

1520|

1950

1850|

2310

∆fband [MHz] 415 450 430 460

Kv-cco [MHz/V] 119 129 123 131

constant Vamp =2.6V

Vtune ∈ [0.1 ; 3.6]

Table 8-1 Measurements of the frequency coverage of the QCCO

The frequency sensibility Kv-cco is equivalent to the Kvco of the LC tuned oscillator. The tuninginput of the QCCO is a voltage/current (V/I) converter that receives Vtune as input, and output Igmt

ii

The bands have an equal frequency range, that enables a simple programming mode for the QCCO, and assures alow Kcco variation throughout the band.

1175M

1600M

1825M 2250M

1500M

950M 1275M

850M 1925M

2150M


. The parameter Kv-cco is the overall sensitivity that includes the gain of the V/I converter plusthe Kcco of the Gm-C oscillator. The input range for Vtune is limited by the working range of theV/I converter.A second V/I input is used for the amplitude control, and its input is called Vamp . The presentdesign was improved to work with a fixed Vamp value, so that this input can be used tocompensate the process spread.The same uniformity was also aimed at for the SSB phase noise performance, and the followingvalues are measured in the two extremes of the tunable range:

( ) ( ) HzdBc

HzdBc

QCCO KHzLKHzLGHzf 8.761004.926002.1 −=↔−=⇒=

( ) ( ) HzdBc

HzdBc

QCCO KHzLKHzLGHzf 9.751005.916001.2 −=↔−=⇒=

At the beginning of the band the main noise source is the thermal noise of the resistors loadingthe transconductors; and at the end of the band the L(f) is limited by the shot noise of thetransistor of gmt . The noise from the biasing stages is minimized by using a large voltageinterval for the degeneration of the current sources.

8.2 TC2 : Mixer-Oscillator-PLL circuit for satellite direct conversion

The testchip TC2 contains several blocks of a double loop PLL synthesizer. The synthesizer chipis combined with mixer-oscillator blocks to compose a MOPLL circuit. The circuit isdimensioned for a monodyne receiver, which means that the input RF channels are directlydown-converted to band base.

8.2.1 Double Loop Synthesizer

Figure 8.2 is a block schematic of the double loop architecture.The tuning system is composed of two cascaded PLLs. The first one (loop #1) locks the QCCOto the reference delivered by the second loop. Loop #1 works with small divider ratios (N1)which allows one to obtain a quite low phase noise for part of the in-loop spectrum (to the orderof -108 dBc/Hz).Loop #2 drives an oscillator that works in the VHF range. This VHF-oscillator has a strictrequirement for phase noise, since its spectrum is “copied” to the LO output.The reference of loop#2 is a traditional 4MHz quartz oscillator (Xosc). The reference divider iscomposed of two counters, one is programmed with the same count (N1) as the divider of loop#1, and the other (R2) determines the minimum tuning step.Table 8-2 shows the relationships among the comparison frequencies and the oscillatorfrequencies.


Figure 8.2 Double loop MOPLL: block diagram

Parameters:

∆fstep : minimum tuning step;fcco1 : QCCO frequency, output frequency of loop #1;N1: main divider ratio in loop #1;fcp1: comparison frequency in phase detector #1;

fvco2 : VCO-VHF frequency, output frequency of loop #2;N2: main divider ratio in loop #2;R2: reference divider ratio in loop #2;fcp2: comparison frequency in phase detector #2;fXosc: Xosc frequency.

RFinput I

Q

RFAGC-Loop

BB output - I

QCCO - LO

Ph. Det. + Ch.P.#1

V/Iconverter

/ N1

Ph.Det.+Ch.P.#2

Zfilter #2VCO2

VHF band

/N2

/N1 /R2Xosc

(4 MHz)

double-loop MOPLL circuit

Loop #1

Loop #2

BB output - Q

Zfilter #1


It is important to notice that thecomparison frequency of loop #2becomes:

12 N

ff step

cp

∆=

Table 8-2 Double Loop: minimum step and comparison frequencies.

The main divider of loop#1 is composed of two swallow counters and N1 belongs to the set: [4, 5, 6, 7]. Thefrequency range of VCO2 is then determined with respect to the limits of the QCCO band. It follows that:

MHZM

fvco 5.2374

950max 2 ==

MHzM

fvco 1.3077

2150min 2 ==

Actually the range of VCO2 should also include some margin at the extremities. If we consider amargin of 20MHz and a tuning range of 4 V, the average Kvco of VCO2 equals 27.4MHz/V.Thus VCO2 works in the range of a VHF-III oscillator, with a frequency sensitivity that is closeto the Kvco of UHF oscillators. These parameters serve as references for the design and theapplication of loop #2.The comparison frequency of loop #1 equals the VCO2 frequency, which means a maximum fcp1

to the order of 330MHz. The design of the charge pump and the phase detector are mostlydetermined by this constraint, since the transfer characteristics Iaverage / ∆ϕin should cover aminimum input range of ±180° . This condition assures that the comparator can retrievefrequency and phase differences (see chapter 5).

8.2.2 TC2 structure

The blocks that are colored in grey in figure 8.2 were implemented in the testchip TC2. A moredetailed schematic diagram is included in figure 8.3.

The testchip is basically divided into two parts, analog and digital, that interact through interfaceblocks. The analog part has symmetrical inputs for the RF signal and asymmetrical outputs forthe BB signals: I and Q. There are external control inputs for the amplitude and frequency of theQCCO. The frequency input is bound to the charge pump output and to an external LPFimpedance. The LO signal can be monitored through a test output. The ensemble of blocks isprogrammed by a 3-wire bus. The bus has an additional acknowledge block that indicates the

oscillatorsfrequency

fvco2 = fcp1 fcco1

wrt fcp fcp2*N2 fcp1*N1

wrt N and R 1*2

2*

NR

NfXosc

2

2*

R

NfXosc

wrt ∆fstep

with:

∆fstep = 2R

f Xosc 1

2*

N

Nfstep∆2* Nfstep∆


reception of a full programming word. The output of the acknowledge block is equivalent to anI2C bus output. In reality this block is included to test the sensibility to bus cross-talk.iii

The charge pump has 2 programmable values of Icp ( 20µA and 190µA) and it can also be set totest modes with sinking, sourcing and high-impedance outputs.

Figure 8.3 Block diagram of TC2

There are 4 supply pins, a pair for the analog part and another for the digital one. The totalconsumption is 60mA under 5V, and the active layout area equals 1.2mm2 . The total layout areais 2.1mm2 , which includes the 20 input/output pins.The symmetry of the layout of the analog part is stressed to guarantee the quadraturecharacteristics of the I and Q branches. Figure 8.4 shows a photo of a testchip TC2. On the leftside there are the digital blocks (bus, main divider and phase-detector /charge pump, from thehigher to the lower corner); and on the right side, the analog part (QCCO, mixer, regulator, inputand output buffers).

iii

Bus cross-talk denotes the interference of the bus activity in the others blocks of the synthesizer. It is measured asperturbations in the output spectrum when the synthesizer is continuously receiving a repetitive programming word.

Vreg

2

22

2

2

4 44

2

Dual Mixer

Phase Det.+

Ch. Pump #1

V/I

Div.1(4.5.6.7)

Sym--> Assym Output stage

BBQ

BBI4

Q

I

QCCO

Vamp Rfin

Bus data loadsynchronization

Plus blockcombine I &Q

CCOoutoutput for

Z=50Ω

TestBus

SDA

SCL

ENB

ACK

3QCCO

2DIV456

4PhDetChP

Biasref

VCCO

GNDO

ANALOGPART

BN--ISOLATION

Pin for externalLoop Filter

Ref

VCC

GND DIGITALPART

INTERFACE LAYER

Bandgapregulator

V/I


Figure 8.4 Photo of a testchip TC2

TC2 was measured in a separate board using a signal generator as input and also in combinationwith a terrestrial synthesizer whose application was adapted to cover the frequency range of loop#2. The results are discussed in the following section.

8.2.3 TC2: results

The blocks are all functional and the loop locks correctly. Some particular points of themeasurements of the different blocks are summarized below:

• 3W + acknowledge bus: there is no visible interference in the LO spectrum for a continuous programming

sequence.

• Phase detector and Charge Pump: The comparator is able to retrieve frequency differences for a maximum fcp equal

to 450MHz, with no loss in its sensibility Kϕ (no dead zone).The SNF for a fcp of 300MHz is measured as –124dBc/Hz. This result is veryclose to the estimation of the charge pump noise presented in section 7.3.2. Thusthe SNF of this wide band loop is set by the charge pump noise performance.


• Mixer and BB buffers:The conversion gain of the mixer plus BB stages equals 5dB.iv The IP3 referencedto the input is measured as 17dBm. These two values agree with the simulationresults.The leakage of the LO signal at the RF inputs is measured as –64dBm, whichindicates that there is no major pollution of LO signals in the supplies that areshared with the mixer. The noise performance of the mixer is good enough to keepthe same L(f) of the LO in the BB outputs.

• QCCO:The frequency coverage is the same presented in section 8.1.2. The quadrature ofthe I and Q outputs is measured in the 4 bands. The measurement was madecomparing I and Q single tones around 10MHz in the base band outputs. Thephase deviations are kept under 2° as long as the amplitude control assures aminimum level around 200mVpeak for the oscillator signal. In the worst case forlow vagc input and in the highest band the maximum deviation is 3.5° .The spurious rays at ±fcp1 are lower than –62 dBc , for a loop filter with a closedbandwidth around 2MHz.

• Pulling:The interference of the RF input on the LO signal was evaluated by a methodwhich is used in the characterization of terrestrial MOPLL circuits. A strong RFcarrier, 100% AM modulated by a signal at 100kHz, is injected into the mixer.The sidebands that appear around the LO carrier at the same 100kHz frequencyoffset are measured.

RF input power Interference at ±100 kHz offset from LO

0 dBm -45 dBc-5 dBm -55 dBc-10 dBm -64 dBc

These levels are roughly 10dB better than the requirements for terrestrial MOPLL.In ZIF satellite receivers the pulling is also evaluated as the deviation of the LOfrequency for a given RF power. However this method is mostly adapted to theLC oscillator where the radiation of the RF input disturbs the resonator. In theQCCO, as expected, there is no frequency deviation of the carrier for RF inputpowers exceeding 10dBm.

Two plots of the LO spectrum are shown in figures 8.5 and 8.6. The first is measured with asmall span of 250kHz, for an fcco1 of 2.1GHz. It shows the in-loop zone of loop #1, when thereference input is a signal generator. The L(f) is indicated in the plot.

( ) ( ) ( ) HzdBc

NloopHzdBc

MHzfNMHzSNFkHzL

cp9.1231log2010730010725

711#3001−=−−=⇒−=

==

iv

We should remember that the current testchip does not contain the pre-amplifier block that should significantlyincrease the range of dynamic gain.


Figure 8.5 TC2 _ in-loop spectrum for N1=7 and fcp1=300Mhz

Figure 8.6 TC2 _out-of-loop spectrum for N1=6 and fcp1=300MHz


The second plot shows a larger span where the out-of-loop zone can be observed. The chargepump current was set to 20µA to decrease the closed loop bandwidth. There is a supplyinterference at 2.3MHz that causes visible sidebands. It is an external disturbance from thelaboratory environment that unfortunately could not be suppressed.

( ) ( ) HzdBc

GHzfHzdBc

GHzf ccoccokHzLMHzL 24.7610028.1084

8.18.1−=⇒−=

==

The noise measurements with great dBc dynamics are very sensitive to the surroundingenvironment. For the plots presented above the output spectra were averaged over several sweepsin order to keep the static signals and filter the sporadic interference. In figure 8.6 this average isparticularly difficult, because of the large span combined with a narrow resolution bandwidth.The consequence is that the central carrier frequency changes slightly during the averages (due tothe finite precision of the spectrum analyzer) and the marker indicating this reference is nolonger fixed at the reference value. This problem is already previewed by the measurement toolthat provides a steady reference for the noise measurement, which is fixed in the first sweep.

An application board of a terrestrial mixer-oscillator, the TDA5732, was adapted to use its UHFoscillator as the reference VCO2 oscillator. The phase noise performance of this referenceoscillator was measured as –114 dBc/Hz at a 100kHz offset.The ensemble of the two boards (loop#2 plus loop#1) was evaluated in a bit-error-rate (BER)measurement.v This measurement is used to quantify the implementation loss that is due to thefrequency synthesizer.Different QPSK channels with symbol rates from 3Msps up to 30Msps were tested. Theperformance of the double loop synthesizer was compared to a single loop synthesizer with a LCoscillator that has an L(100kHz)=-98dBc/Hz. The implementation losses of both systems arepractically identical. The influence of the L(f) of VCO2 appears mainly when we are decodingnarrow channels, for instance with the symbol rate of 3Msps. In this case the phase noise ofVCO2 has to be kept better than L(100kHz)=-112dBc/Hz. Otherwise the implementation loss ofthe double loop is worse than the LC oscillator plus a single loop.

8.3 TC3 : single PLL plus QCCO circuit

The testchip TC3 contains a low noise satellite PLL plus a QCCO. The low noise PLL wasdesigned by the PLL-tuner development group at Philips Semiconductors in Caen. The objectiveof this testchip is to verify the maximum closed loop bandwidth that can be achieved in a singleloop configuration.Figure 8.7 shows a plot of the output spectrum of this single loop. The comparison frequencyequals 1MHz and the loop filter is calculated for an open loop bandwidth around 165kHz. Theclosed loop bandwidth or the 3dB bandwidth for the PLL is: f3dB = 279kHz.If we refer to the results of chapter 5 we see that this closed loop bandwidth comes close to themaximum stable value. Indeed a 50% increase of the open loop bandwidth would already causethe instability of the system.

v The BER is a common unit used in the context of digital decoders. It measures the amount of errors encountered in

the reception of a test sequence.


Figure 8.7 TC3 _ single low noise PLL plus QCCO

Figure 8.8.a Linear scale

1


Figure 8.8.b Logarithmic scale

Figure 8.8 Simulation result for the SSB phase noise _ linear scale

The measurement may be compared with the simulation results presented in figures 8.8.a and8.8.b. They show the result of a noise simulation with the AC behavioural model of the PLL (seesection 7.4.1). Figure a uses a linear scale for the abscissa so that it can be better compared withthe spectrum output. Figure b uses a logarithmic scale to emphasize the LPF transfer of Npll andthe BPF transfer of vnvco.

The noise simulations used the parameters Lvco and Npll that were found in the measurements,and the results agree very closely with the output of the spectrum analyzer.The comparison between the plots 8.8.a and 8.8.b evidences the influence of the peaking inmasking the noise performance of the PLL in the in-loop zone. Actually in order to measure Npll

it is necessary to use a very small span around the carrier.We measured Lpll and calculated Npll , measuring the spectrum in a span of 10kHz. They werefound to be: Lpll(2kHz) = -86.7 dBc/Hz ; with: N = 900 ; fcp = 1MHz ⇒ SNF(1MHz) = -145.7 dBc/Hz

The noise performance of the VCO is the same encountered in TC2, which is: Lvco(100kHz) = -76 dBc/Hz .


The intersection frequency for the two noise asymptotes equals: 343kHz ; which indicates thatthe open loop frequency of the filter should be increased to have a smaller peaking in thespectrum. However, we know that we already reached the maximum values of fol with respect tothe stability constraints.The phase jitter of the present output spectrum exceeds the limit value of 4.84° that would benecessary to keep the implementation loss below 0.2 dB (see section 7.5.1.3). Therefore thissingle loop plus QCCO configuration would need to incorporate a fractional divider, in order tohave two different values for the minimum frequency step and the comparison frequency.

8.4 Comparative analysis: phase jitter and implementation loss

In this section we compare the spectra of two synthesizer configurations for a zero-IF satellitereceiver: the double loop plus QCCO and the single loop plus LC oscillator.Currently the satellite tuner has separated ICs for the MO and PLL functions. This analysisintends to orient the next steps of the IC development of a single chip MOPLL for satellitereception.

8.4.1 Configurations compared

The configuration, double loop plus QCCO (DL+QCCO), corresponds to the architecture ofTC2, and its present status of development was discussed in section 8.2.The configuration, single loop plus LC oscillator (SL+LC-osc), is based on the Philips IC: theTDA8060, a mixer-oscillator for zero-IF satellite reception.The values used in the simulations, for the noise performance of the PLL and the VCO,correspond to the measurements of the parameters Lvco and SNF in TC2 , TC3 and in theTDA8060. The table below summarizes these parameters:

Double Loop + QCCO Single Loop + LC oscillatorLoop #1:

SNFloop#1(fcp = 300MHz) = -124 dBc/Hz

LQCCO (foffset = 100kHz) = -76 dBc/Hz

Kv-cco = 125 MHz/V ; Icp1 = 190 µA

Loop #2:

SNFloop#2(fcp = 125kHz) = -154.7 dBc/Hz

LVCO2 (foffset = 100kHz) = -114 dBc/Hz

Kvco2 = 27.4 MHz/V ; Icp2 = 1.2 mA

Single loop parameters:

SNF(fcp = 125kHz) = -154.7 dBc/Hz

LVCO (foffset = 100kHz) = -100 dBc/Hz

Kvco = 100 MHz/V ; Icp = 550 µA

Table 8-3 Parameters of the two zero-IF configurations being compared


The current of loop #2 in the DL+QCCO is chosen as the largest value for which we havealready tested low noise charge pump designs. The need for this high Icp2 value appears when weare minimizing the phase jitter in loop#2. In fact, VCO2 has a very tight phase noiseperformance and the noise from the resistors of the loop filter becomes significant for valuesabove 2kΩ. High Icp2 values enable us to decrease the loop filter impedance.The synthesizer noise floor of loop #2 in the DL+QCCO, and in the SL+LC-osc are derived fromthe measurements of TC3.There are already some stand-alone PLL ICs that present a better SNF (see data about theTSA5059 in section 7.1). However when combining the PLL and the MO in the same IC, it isprobable that the crystal-oscillator design should work with smaller amplitudes and currents, andcloser to a linear mode; in order to avoid excessive interference in the common substrate, andunder-sampling phenomena with respect to strong RF and BB signals.The calculations use the SNF of TC3 that contains a more linear design for the crystal oscillator.When the simulations are made with comparison frequencies that are different from the valueindicated in table 8-3 (125kHz); the changes in SNF are assumed to respect the variation rate of3dB/octave-of-fcp . This variation rate is discussed in chapter 7, and it is confirmed bymeasurement results.

8.4.2 Conditions for the simulations

The comparative analysis is based on simulation results for the phase jitter in the LO signal. Thesettings of the simulations are the same used during the BER measurements of TC2. So that wecan evaluate the accuracy of the behavioural model used in the simulations.Table 8-4 lists the variable parameters and the outputs that were calculated:

Variable Parameters: Simulated Outputs:

• LO frequency [Hz]:flo = 900M ; 2.2G ;changes the dividing ratios (N1, N2);

• Tuning step [Hz]:∆fstep = 125k ; 1M ;changes the comparison frequencies and theloop filters;

• Symbol rate for QPSK modulation [sps]:rs = 3M ; 30M ;changes the settings of the demodulator andthe integration boundaries for the phase jitter;

• Phase Jitter at the PLL output:σϕ-pll (fmin, fmax) [°] ;where fmin and fmax are the integrationboundaries.

• Phase Jitter at the demodulator output:σϕ-dem (fmin, fmax) [°] ;σϕ-dB-dem (fmin, fmax) [dΒ] ;

• Implementation loss due to the phase jitter at thedemodulator output:ILdB [dB]

Table 8-4 Parameters and outputs for comparative analysis

Let us examine these outputs and parameters.The phase jitter is evaluated at two points of the reception chain, at the PLL output, and at thedemodulator output. The second one is also expressed in dB and translated in an implementationloss. The implementation loss is calculated for a SNRmin of 8dB, which corresponds to the rawBER of 6.10-3 .


The value of ILdB accounts for the losses due to the phase jitter, and it can be compared to the0.2dB threshold discussed in section 7.5.The power of the spurious rays is not included in this ILdB . However we can easily derive aspecification for the acceptable spurious level looking at the value of σϕ-dB-dem , andremembering expressions (7.13) and (7.14). In general a pair of spurious rays with a SSB level of(σϕ-dB-dem – 6dB) in dBc, should be the maximum discrete disturbance allowed. If there are morepairs of spurious rays, the maximum power level should be divided by the number of rays thatare found within the range of phase jitter integration.The phase jitters are integrated in the bandwidth: [fmin ; fmax ] = [0 ; bwch]. The higher boundaryis chosen as bwch instead of bwch/2, as indicated in expression (7.15). In fact the earlierexpression takes into account a single channel, with no disturbance from adjacent channels.When we enlarge the integration boundary to bwch we are also taking into account the effect ofthe two closest adjacent channels, considering that they have the same power density as theselected channel.

The LO frequency range covers the band-L with a small margin. We simulate the two extremitiesto test the cases of the largest and the narrowest loop bandwidths, with the lowest and the highestin-loop noise contribution from the PLL.The settings of the demodulator block are derived from the satellite demodulator and decoderTDA8043. The phase model of the demodulator part was discussed in section 7.5.2.The frequency and phase detection range of the carrier recovery loop equals rs/8 , where rs is theinput symbol rate. Therefore, with respect to the demodulator, the maximum tuning step for agiven symbol rate would be rs/4. Nevertheless the circuit specifications often demand muchlower tuning steps. For satellite applications the typical value is 125kHz, and more recentlyhigher steps like 1MHz are discussed to tune high symbol rate channels.In a QPSK modulated channel the symbol rate is equal to the channel bandwidth in Hz. Thesimulations test two symbol rates or channel bandwidths: 3Msps (bwch=3MHz) and 30Msps(bwch=30MHz).The bandwidth and damping parameters for both clock and carrier recovery loops are derivedfrom the application note of the demodulator, and they are the same as those used in themeasurements of TC2. Table 8-5 lists the inputs of the behavioural model of the demodulator forthe two symbol rates:

rs [sps] Nd1 WNslow/2π [Hz] ξslow WNfast/2π [Hz] ξfast1.56k 0.68

3M 74 722 1.164.95k 0.83

30M 20 7.91k 1.13 15.2k 0.81

Table 8-5 Settings of the demodulator block

Nd1 is the number of delays within the clock recovery loop, WN and ξ determine the loop filterparameters, and the subscript fast and slow refer to the carrier and clock recovery loopsrespectively.The tightest situation for the LO requirement appears for the narrowest channels, where thedemodulator loops are narrower, and they filter less of the LO phase jitter. We test two values forthe bandwidth of the fast loop to verify the influence of this parameter.


Figure 8.9 Spectra for ∆fstep =125kHz and flo =900MHz

Figure 8.10 Phase noise simulation for DL+QCCO with and without demodulator

fcp2 = 31,25k

3k 5k 320k 5M

-71,6

-77,6

-112

L(f)(dBc/Hz)

log (foffset)[Hz]

L(foffset=10kHz) ~ -80 dBc/Hz

fcp = 125k

SL+LC-osc

DL+QCCO


Figure 8.9 is a sketch of the spectra found at the output of the two configurations for a tuningstep of 125kHz, and an LO frequency of 900MHz. The levels indicated correspond to the SSBphase noise at the output of the PLL. The spurious rays due to the reference breakthrough arealso indicated.The level of the L(f) for the inner part of the double loop configuration (determined by loop #2)is generally higher than the L(f) of the single loop configuration. In the outer part, for foffset above320kHz), the double loop is also worse because it adds some noise with respect to the singleloop.Nevertheless we know that the double loop, with an integrated oscillator, presents advantages ofcompactness and robustness with respect to strong RF inputs. Therefore, our analysis evaluates ifthe losses of the double loop, when compared to a single loop, are really influencing the ILdB

that is measured at the input of the decoder.

Figure 8.10 shows the output of a noise simulation for the DL+QCCO configuration. The noisedensity is plotted for the phase at the output of the PLL, and also at the output of thedemodulator.

The curves of figure 8.10 are also calculated for fLO =900MHz and ∆fstep=125kHz. Theparameters of the demodulator are the ones listed in table 8-5 for a rs = 3Msps and aWNfast=4.95kHz. We observe that most of the phase jitter below WNfast is filtered by thecarrier recovery loop, which may significantly change the value of the total phase jitter beforeand after the demodulator.

The loop filters of the two configurations were set to minimize the phase jitter at the output ofthe PLL ( σϕ-pll (0, bwch) ). The values used in the simulations were:

• filters for DL+QCCO (foln: C1/C2/R1/C3/R3):loop#1: 8MHz: 10pF/0.39pF/10kohms ; (no post-filter, and equal values for the 2 cases of ∆fstep)loop#2:for ∆fstep 1MHz: 5.5kHz: 100nF/3.9nF/1.2kohms/3.9nF/1kohms;for ∆fstep 125kHz: 2.5kHz: 68nF/2.7nF/4.7kohms/2.2nF/3.9kohms;

• filters for SL+LC-osc (foln: C1/C2/R1/C3/R3):for ∆fstep 1MHz: 46kHz: 2.2nF/82pF/8.2kohms/27pF/15kohmsfor ∆fstep 125kHz: 3kHz: 68nF/2.7nF/3.9kohms/820pF/8.2kohms

8.4.3 Results and conclusions

The largest differences in σϕ-pll (0, bwch) appear for fLO = 2.2GHz, and N1=7. Therefore we startcomparing these situations for a high symbol rate channel with rs=30Msps. The simulationoutputs are shown in table 8-6.


∆fstep = 1MHz ∆fstep = 125kHz

Configuration σϕ-pll[°]

σϕ-dem[°]

σϕ-dB-dem[dΒ]

ILdB[dB]

σϕ-pll[°]

σϕ-dem[°]

σϕ-dB-dem[dΒ]

ILdB[dB]

DL+QCCO 4.38 1.65 -30.8 0.023 7.76 1.63 -30.9 0.022

SL+LC-osc 2.72 2.19 -28.4 0.040 4.02 0.67 -38.7 0.004

Table 8-6 Phase Jitter and implementation loss for rs=30Msps and fLO = 2,2GHz

The results above verify that both configurations have quite some margin with respect to the 0.2dB threshold for the ILdB due to phase deviations. The phase jitter of the DL+QCCO after thedemodulator, for a large carrier recovery loop is very close to the SL+LC-osc.The filter of the SL+LC-osc for ∆fstep of 1MHz could probably be made narrower to improve theσϕ-dem with some loss in σϕ-pll .The next table shows the outputs for a low symbol rate channel of 3Msps. In this case only thesmaller frequency step of 125kHz is presented. The phase jitter at the output of the demodulatoris calculated for two values of carrier recovery loop bandwidth.

WNfast=1,56kHz WNfast=4,95kHz

Config. fLO

[Hz]

σϕ-pll

[°]σϕ-dem

[°]σϕ-dB-dem

[dΒ]ILdB[dB]

σϕ-dem

[°]σϕ-dB-dem

[dΒ]ILdB[dB]

900M 3.19 2.24 -28.1 0.042 1.38 -32.4 0.016DL+

QCCO 2.2G 7.68 3.88 -23.4 0.127 2.16 -28.5 0.039

900M 2.81 2.29 -28.0 0.044 1.61 -31.0 0.022SL+

LC-osc 2.2G 4.01 2.52 -27.1 0.053 1.50 -31.6 0.019

Table 8-7 Phase Jitter and implementation loss for rs=3Msps and ∆fstep = 125kHz

In the reception of low symbol rate channels, and in particular with small carrier recovery loops,we start to notice the influence of the LO phase jitter.The results for low and high symbol rates are coherent with the comparative measurements ofTC2 and the zero-IF mixer-oscillator TDA8060.The measurement set that was used enables a precision of 0.05dB in the readings ofimplementation loss. Therefore a quantitative analysis needs to identify the most significantparameters for the performance of each configuration and vary them as much as to causedifferences in the ILdB above the measurable limit.The most sensible parameters in the configuration DL+QCCO are Lvco2 and SNFloop#1 . Theexperience of the testchips implemented show that SNFloop#1 is quite stable among differentsamples and different diffusion lots. However the Lvco of LC oscillators tends to vary within a 3to 6 dB range amongst different samples and application layouts. Therefore this last parameter isconsidered as the most critical.


In the SL+LC-osc configuration, it is again the Lvco that is the most influencing parameter. Table8-8 shows the margin for degradations in the Lvco of the two configurations for the low symbolrate reception. The minimum values of Lvco should be compared with the nominal values thatwere presented in table 8-3 (DL+QCCO: LVCO2(foffset = 100kHz)=-114 dBc/Hz; and SL+LC-osc: LVCO (foffset = 100kHz) = -100 dBc/Hz).In particular for the double loop system we also test the margin of acceptable degradation of theQCCO phase performance (nominal value: LQCCO(foffset=100kHz)=-76 dBc/Hz). The margins aremeasured as the maximum Lvco value that would cause an ILdB of 0.2dB for the reception of a3Msps channel.

Margin for Lvco(100kHz) degradation to achieve ILdB = 0.2 dB

Config. WNfast=1.56kHz WNfast=4.95kHz observations

maxLvco2=-110 dBc/Hz max Lvco2=-104.5 dBc/Hz only varying Lvco2(f)DL+

QCCO max Lvco2=-110 dBc/Hzmax LQCCO=-65 dBc/Hz

max Lvco2=-105 dBc/Hzmax LQCCO=-64 dBc/Hz

Varying bothLvco2(f) and LQCCO(f)

SL+

LC-oscmax Lvco=-92 dBc/Hz max Lvco=-88 dBc/Hz

Table 8-8 Margin for degradations in the oscillators phase noise performance

The margins of Lvco degradation in both configurations show that these system specifications arepracticable for production on an industrial scale. We notice that the bandwidth of the carrierrecovery loop, when increased to 4.95kHz, can improve the margins of 4 to 5dB.The margins of the Lvco have to be respected within the entire frequency range, which means arange of 1.3GHz for the SL+LC-osc , and a range of 110MHz for the VHF oscillator ofDL+QCCO. Therefore the larger margin in the performance of the Lvco for the SL+LC-osc is notnecessarily easier to be held than the margin of the VHF oscillator.Besides, for values of carrier recovery bandwidth that are close to or larger than the PLLbandwidth, the SNF has no major influence. This effect can be verified for the SL+LC-osc wherea variation of 10dB in the SNF is barely visible for a WNfast of 4.95kHz. In the double loop onlythe SNFloop#2 can be relaxed; in fact variations of 7dB can also be tolerated for the large carrierrecovery loop.This analysis and the conclusions are valid for the context of a QPSK receiver where theneighbouring channels have power density levels that are close to the level of the selectedchannel. Other extended models can be derived to analyze the implementation losses for FM,QAM and OFDM receivers. Furthermore the behaviour of the decoder, for the final output signalquality should also be examined, in particular the sensitivity to the shape of the random phasenoise sidebands (white or 1/f2).

This chapter presented physical results from testchips and comparative measurements for adouble loop synthesizer with a completely integrated Gm-C oscillator, that covers the satelliteband-L.

Chapter 9 / Conclusions 191

9 Conclusion

New communication standards are very demanding for tuner specifications. Thereforebehavioural system analysis becomes a more and more relevant step, in evaluating anddimensioning circuit and block requirements.

In this work we analyzed the PLL frequency synthesizer for its stability and noise aspects. Theapplication context was the frontend of TV tuners, with special focus on satellite receivers.

The PLL was presented as a control system, in order to study the influence of differentparameters using a simple and flexible model. This representation was used to examine someissues around the application and specification of the PLL: controlling the feedback bandwidth,working with larger comparison frequencies, dealing with phase noise, stability and spuriousrequirements, etc.

We continued pushing the noise issue farther away in the PLL system, and looked for atheoretical basis that could be linked to the measurement and simulation contexts.

Next, we treated an example of a new frontend architecture: the near-zero IF receiver for asatellite tuner, using an integrated oscillator. The concept and the implementation of twotestchips was discussed and the measurements were compared to calculations and simulationsresults.Finally, the loss of signal quality, which is due to the phase deviations of the LO, was studiedand a numerical example was calculated for the case of a QPSK receiver.

In summary, there were three basic parts in our study: control theory applied to PLL, treatingphase noise in the PLL system, examining new architectures and system specifications.

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FOLIO ADMINISTRATIF

THESE SOUTENUE DEVANT L’INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON

NOM: de Queiroz Tavares DATE DE SOUTENANCE: 09 /12 / 1999

PRÉNOMS: Marina

TITRE:

SYNTHETISEUR DE FREQUENCE A BOUCLE DE VERROUILLAGE DE PHASE:

ETUDE DU BRUIT DE PHASE ET DE BOUCLES A LARGE BANDE

NATURE: Doctorat Numéro d’ordre: 99 ISAL 0086

FORMATION DOCTORALE: Dispositifs de l’électronique intégrée

ECOLE DOCTORALE: Electronique, Electrotechnique, Automatique (EEA)

Cote B.I.U. – Lyon : T 50 / 210 / 19 / et bis CLASSE:

RESUME:

Les synthétiseurs de fréquences à boucle de verrouillage de phase sont largement utilisés dans les récepteurs et les transmetteurspour les télécommunications, comme partie du bloc de conversion de fréquence. Ils sont constitués d’un oscillateur accordable etd’une boucle à contrôle de phase programmable. Les tendances actuelles dans le développement des PLL concernent lesperformances en bruit et un plus haut degré d’intégration. Le premier est en relation direct avec les nouvelles techniques demodulation numériques, nécessitant souvent un plus fort rapport porteuse/bruit dans la chaîne de traitement du signal. Les secondesrépondent à l’orientation générale vers des systèmes plus petits et plus compacts.La thèse développe et discute les modèles d’un système PLL pour étudier les aspects stabilité et bruit. Les résultats du modèle sontutilisés pour la conception des circuits intégrés et de leur applications. Ces résultats sont confirmés par les mesures.L’approche «stabilité» étudie la robustesse du système PLL, travaillant typiquement avec des très grandes variations de gain. Uneapproche du système au circuit (top-down), étudie la génération et la transmission du bruit. Finalement, des réalisations de circuits-tests du PLL avec des oscillateurs intégrés sont présentés.La thèse s’est déroulée dans le cadre d’une collaboration entre le CEGELY - INSA de Lyon et Philips Semiconductors et plusparticulièrement au sein du centre de production et développement de Caen.

MOTS-CLES:

‘‘Tuner’’, Partie Entrée Récepteur RF, Boucle Phase Asservie, Bruit de Phase, Stabilité, Oscillateurs OTA-C

Laboratoire de recherche: CEGELY – INSA de Lyon

Directeur de thèse: Jean Pierre Chante

Président de jury: ……..

Composition du jury:

Richard-GRISEL Professeur - Université Picardie rapporteurMichiel-STEYAERT Professeur - K.U. Leuven rapporteurJean-Pierre-CHANTE Professeur - INSA de Lyon directeurBruno-ALLARD Maître de Conférences - INSA de Lyon examinateurPhilippe-KLAEYLE Ingénieur - Philips Semiconductors - Caen examinateurEduard-Stikvoort Chercheur - ingénieur – Philips Nat.Lab. – Eindhoven examinateur

PLL Frequency Synthesizers, Phase Noise and Wide Band

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