PLL Based Bridge Synchronization as anAlternative to Digital Isolators for Dual Active

Bridge DC-DC ConvertersShahab Poshtkouhi, Aliakbar Eski, Olivier Trescases

University of Toronto10 King’s College Road, Toronto, ON, M5S 3G4, Canada

E-mail: shahab.poshtkouhi@utoronto.ca

Abstract— Digital isolators are widely used in isolated powerconverters for transmitting high-frequency gating pulses. Conven-tional opto-isolators suffer from low reliability and poor delaymatching, while emerging RF based isolators are either expensiveor power-hungry. In this work, a Phase-Locked-Loop (PLL)based synchronization scheme is demonstrated to operate a bi-directional Dual-Active-Bridge (DAB) dc-dc converter withoutany digital isolators. The converter is targeted to renewableenergy applications with integrated storage. The reference clockis generated on the secondary-side controller and sensed on theprimary-side using the main power transformer. A synchronizedclock within the primary-side controller is generated using thePLL by modulating the supply voltage of a voltage controlled os-cillator. The proposed method is implemented and demonstratedon a 150 W, 94.2% efficient DAB converter prototype. With thissynchronization scheme in place, low-frequency communicationacross the isolation transformer is also demonstrated by modu-lating the switching frequency.

I. INTRODUCTION

The Dual-Active-Bridge (DAB) isolated dc-dc converter iswidely used for bi-directional power applications, since itoffers 1) soft-switching operation, 2) a wide voltage range,3) excellent transformer utilization, and 4) simple phase-shiftpower control [1]–[3]. In recent years, high-efficiency DABconverters have been demonstrated for applications rangingfrom Electric Vehicle (EV) battery chargers [4], [5] to Photo-voltaic (PV) micro-inverters with integrated storage [6]. Oneof the main disadvantages of the DAB converter, especiallyfor power levels below 1 kW, is the large number of switchesand the need for precise phase synchronization across theisolation boundary. Using a conventional driving scheme, thecontroller operates either on the primary or secondary-sideof the transformer and four high-frequency gating signalsare transmitted to the other side using digital isolators, asshown in Fig. 1. Low-power opto-isolators are commonlyused in power electronics applications, however they sufferfrom long delays (above 15 ns is typical) and short life-time at high temperature [7], [8], which is a major issue inrenewable energy applications. More recently, isolated gatedrivers based on miniaturized magnetic components eitheron the PCB [9] or on-chip [10]–[14] have solved some ofthese shortcomings, while offering a high level of integration.In the case of [13], [14], the digital isolator is capable of

transmitting both the signal as well as the gate-driver powersupply using a dedicated coil. Such RF based digital isolatorstypically modulate the PWM signal with a carrier in the rangeof hundreds of MHz [13], [14] to several GHz in order toreduce the communication transformer’s size, however theyrequire precise mechanical alignment between primary andsecondary-side coils and/or specialized assembly processes.These isolators are also susceptible to potential Electromag-

LDAB

Primary-Side Controller

+

Vbus

-

clk_ref

M1 M2

M3

M4

M5 M6

M7M8

c1 c3 c2 c4

Vx1Vx2

+ +

-

1 : n

Vsns-

+

-

Osc.

c5

c7

c6

c8

DigitalIsolators

+

Vpv

-

Vs5

Vs5

Vs6

Vs1

LDAB+

Vbus

-

M1 M2

M3

M4

M5 M6

M7M8

Vx1Vx2

+ +

-

1 : n

Vsns-

+

-

c4

c2

c3

c1

DigitalIsolators

+

Vpv

-

Secondary-Side Controller

clk_ref

c5 c7 c6 c8

Osc.

Vs1

Vs2

Vs1

Vs2

Fig. 1. DAB dc-dc converter with (a) primary-side and (b) secondary-sidecontroller utilizing conventional digital opto-isolators.

netic Interference (EMI) issues and consume nearly as muchpower as the gate-driver itself. In this work, an alternativescheme is demonstrated specifically for the DAB converter,which eliminates the need for costly isolated gate-drivers.

II. PROPOSED SYNCHRONIZATION SCHEME

The ideal switching waveforms of the DAB converter oper-ating in steady-state are shown in Fig. 2. The gating signals,c1−8, have a duty cycle of D = 50%. The average power fromVpv to Vbus, PDAB , is

PDAB =VPV Vbus

nωsLDABϕ

(1− |ϕ|

π

), (1)

where n is the transformer turns ratio, LDAB is the DABinductance, which is the sum of transformer’s leakage induc-tance and the external inductance. ϕ is the phase-shift betweenthe two bridges, and ωs = 2πfs, where fs is the switchingfrequency. The primary controller sets PDAB by adjusting thedelay, td = ϕTs/2π, for the purpose of Maximum Power PointTracking (MPPT) in the targeted PV application.

One method of reducing the number of digital isolators isto synchronize the primary and secondary-side drivers usinga single high-speed digital isolator, as shown in Fig. 3. Inthis application the DAB converter is used to interface ahigh voltage dc bus, Vbus, to a combination of PV moduleand integrated battery storage. The secondary-side controllerperiodically transmits a high-frequency signal to the primary-side controller. The system reference clock, clk ref , is pro-vided by the oscillator on the secondary-side controller. Usingthis scheme, the clock used on the primary-side controller,clk sync, is synchronized to clk ref using a digital Phase-Locked-Loop (PLL). Data can also be transmitted via the samechannel.

c1,4

c2,3

c5,8

c6,7

t

t

t

t

t

t

Vx1

Vx2

ILDAB

VPV

-VPVVbus

-Vbus

TsTs/2

s1

-s1

t

s2

-s2

pj2

s

d

Tt =

I II III IVState:

Fig. 2. Steady-state switching waveforms for the DAB converter.

=

=

LDAB

Primary Controller Secondary Controller

+

Vbus

-

+

Vpv

-

Osc.clk_ref

PLLclk_sync

M1 M2

M3 M4

M5 M6

M7M8

c1 c3 c2 c4 c5 c7 c6 c8

Vx2

1 : n

Vx1Vx1V+x1VVx1VV

-

Vsnssns+

sns-

Vs5Vs1

or

Fig. 3. DAB dc-dc converter with PLL based gate-drive synchronization.

The system architecture can be further simplified as shownin Fig. 4, which is the main focus of this work. Unlike Fig. 3,the PLL is locked by directly sensing the reflected voltage atVsns = Vx2/n, as explained in Section III. The main powertransformer is therefore used both for power isolation andgating synchronization. As demonstrated in Section V, thisscheme can also be used to transmit data to the primary-sideusing frequency modulation.

=

=

LDAB

Primary Controller Secondary Controller

+

Vbus

-

+

Vpv

-

Osc.clk_ref

PLLclk_sync

M1 M2

M3 M4

M5 M6

M7M8

c1 c3 c2 c4 c5 c7 c6 c8

Vx2

1 : n

Vx1+

-

Vsns+

-

Vs5Vs1

Fig. 4. Modified PLL scheme with synchronization achieved using trans-former sensing.

III. DIGITAL PLL AND COMMUNICATION SCHEME

A. Digital PLL Scheme and Analog Interface

The detailed clock generation scheme for the primary-side controller is shown in Fig. 5(a). The majority of thefunctionality is implemented in the digital domain within anFPGA. A high-speed comparator generates the comp signalwhen the sense signal, Vsns, changes polarity. The comp signalis in-phase with clk ref , as shown in Fig. 1. The VoltageControlled Oscillator (VCO) within the FPGA is implementedusing a ring oscillator comprised of 2k delay elements, whosesupply voltage is adjusted by a Digital-to-Analog Converter(DAC). The core supply voltage, Vcore, of the entire FPGAis controlled in this way. An on-chip implementation wouldallow the PLL to be implemented more efficiently. The outputof the ring oscillator is divided by an m−bit counter toproduce clk sync. The digital phase detector and loop filterare used to adjust the DAC input voltage such that the VCOfrequency is locked to 2mfs, while the phase of clk syncis aligned to clk ref . Similar to the well known hybrid

Secondary-Side Controller

+

Vbus

-

Osc.clk_ref

M5 M6

M7M8

c5 c7 c6 c8

Vx2x2

+

x2-

1 : n

Vsnssns

+

sns-

comp

MUX

Logic +

DT Control

Counter

2k cells

Phase

Detect

Loop FilterGl(z)

DACVcore

clk_syn

c

PLL

DelaySelect

m

MPPT

+

Vref

Vpv ADC

ADCIpv

Gc(z)

seltp

k

selct

m

to power stage

c1-4

selselFPGA:

Primary-Side Controller

CommDetect

data_out

Clk Div

data_in

Vs5

Fig. 5. PLL implementation for clock synchronization across the DAB transformer. The primary-side bridge is not shown.

Digital Pulse-Width Modulators [15]–[17], the combinationof a counter and delay-line with a total resolution of k + mbits allows a flexible trade-off between power consumptionand area real-estate for future on-chip implementation. Thedelay-line allows a high-resolution phase-shift control to beimplemented, in this case for the purpose of regulating theinput voltage Vpv to Vref . The reference voltage, Vref , isgenerated by an MPPT block, however the focus of thispaper is limited to the PLL demonstration. The ideal startupsequence is shown in Fig. 6(a). The secondary-side controllerfirst starts switching the bridge through c5−8 when reset isdisabled. Once multiple transitions are detected on the compsignal, the primary-side controller enables the phase detectorand locks clk sync to clk ref by adjusting Vcore. When alock is detected within the phase generator, the lock ok signalis asserted and triggers the primary-side controller to turn onthe gating pulses c1−4. The phase offset between the primaryand secondary-side bridges is then separately controlled by thevoltage feedback loop.

B. Data TransmissionThe proposed synchronization scheme can also used to

transmit arbitrary data from the secondary to the primary-side with minimal additional hardware, by slowly modulat-ing the switching frequency. Frequency modulation has beendemonstrated in other Power Line Communication (PLC)schemes [18]. The low-frequency data can be used to transmithigh-level supervisory commands, temperature information,configuration parameters, etc. The process is illustrated inFig. 6(b). When communication is periodically enabled, thedata in bit stream modulates the reference frequency on thesecondary-side through a clock divider (Clk Div), as shown inFig. 5. On the primary-side, the change in frequency causes thePLL to temporarily go out of lock, while Vcore is adjusted. Theoutput of the digital PLL loop filter is fed to a communicationdetection block (Comm Detect), that reconstructs the databased on the deviation from the nominal value in the locked

reset

c5-8

c5

c1D = 50 %

comp

pll_enstart PLL

Vcore

lock_ok

t

t

t

t

t

tc1-4

td

(a)

data_in

fs

Vcore

lock_ok

t

t

t

t

1 0 1 1 0 1 1 0 0

data_outt

(b)

Fig. 6. (a) Startup of the synchronization process. (b) Power line communi-cation based on frequency modulation.

frequency. The communication bit-rate rate is limited by theswitching frequency and PLL locking time. In many power

electronics applications including PV, a bit-rate in the few kHzrange is acceptable for supervisory functions.

IV. EFFECT OF TRANSFORMER LEAKAGE INDUCTANCE

The DAB inductance, LDAB , is the sum of the transformer’sleakage inductance, Lleak, and an external inductance, Lext,as shown in Fig. 7. In theory a DAB converter can bedesigned without any external inductance, however, this isusually avoided due to the unpredictable nature of Lleak. Thewaveforms of Vsns and Vcomp are shown in Fig. 8(a) forLleak ̸=0. The leakage inductance distorts the Vsns duringtd. If Lleak is sufficiently large, or if the PV voltage is muchhigher than the reflected bus voltage on the primary side, thePLL will not lock to the secondary-side switching waveform.It can be shown that the PLL remains locked to the secondary-side if the following condition is satisfied

Vbus

n

Lext

Lleak≥ Vpv. (2)

Transformer

LLeakLext +Vsns-

+Vx2-

+Vx1-

comp

Fig. 7. Sensing scheme with non-zero leakage inductance.

t

t

t

Vx1

Vx2

Vsns

VPV

-VPVVbus

-Vbus

t

comp

td

(a)

t

t

t

Vx1

Vx2

Vsns

VPV

-VPVVbus

-Vbus

t

comp

td

(b)

Fig. 8. (a) Waveforms for Vsns and comp when (2) is satisfied and (b)when (2) is not satisfied, causing the PLL to lock to the primary-side whichleads to system instability.

If (2) is not satisfied, the comparator output follows theprimary-side timing, as illustrated in Fig. 8(b), thus the in-tended PLL lock to the secondary-side is lost. In this conditionthe system can start up properly; however due to PLL drift,the primary and secondary-side frequencies will gradually driftapart, causing the converter to malfunction. From Fig. 8(b) itcan be seen that an automatic adjustment of the comparatorthreshold is one way to prevent with this scenario. A plot ofthe locking range based on (2) is shown in Fig. 9.

0.5

1

1.5

2

2.5

0 1 2 3 4 5

nV

pv /V

bus

Lext/Lleak

PLL Synchronization

not Feasible

PLL Synchronization

Feasible

Fig. 9. Feasible operation region for the PLL synchronization scheme.

V. EXPERIMENTAL RESULTS

A 150 W DAB converter prototype, as shown in Fig. 10, wasfabricated on a custom PCB with the parameters listed in TableI. The primary-side controller is implemented in an FPGAevaluation board, modified to accommodate the supply voltagemodulation scheme shown in Fig. 5. The FPGA is a XilinxSpartan 3E, implemented in 65 nm CMOS with a nominalcore voltage of Vcore = 1.2 V. The secondary-side controlleris implemented with a low-cost Complex Programming LogicDevice (CPLD) on the same PCB as the DAB converter.

TABLE IDAB CONVERTER PROTOTYPE SPECIFICATIONS

Parameter Value Units

Rated Power, Pnom 150 W

Dc-dc Stage Switching Frequency, fs125-135 kHz

Primary-Side Capacitance, Cin 1 mF

Secondary-Side Capacitance, Cbus 270 µF

DAB Inductance, LDAB 3.5 µH

Primary-Side Voltage, Vpv 24 V

Bus Voltage, Vbus 400 V

Transformer Turns Ratio, n 15

The steady-state DAB waveforms at fs = 125 kHz andPDAB = 140 W are shown in Fig. 11. The converter effi-ciency for the nominal switching frequency of fs =135 kHzand modulating frequency of 125 kHz is shown in Fig. 12.The DAB achieves a peak efficiency of 93.4%, and 94.2%respectively.

Primary Side

Secondary

-Side

Bridge

FPGA ConnectorFVcore

Connect

CPLD

Primary-

Side

Bridge

Fig. 10. The 150 W DAB converter prototype which includes no digitalisolators. The controller is implemented on an FPGA board (not shown).

ILDAB

Vs1

Vs5

comp

Fig. 11. Measured DAB waveforms in steady-state (ILDAB :1/3 A/div,Vs5:500 V/div (attenuated by 10×). comp is the sensed reference clock onthe primary side.

The relatively poor light-load efficiency of the DAB con-verter can be improved using a number of techniques, includ-ing burst-mode and flyback-mode [19], which is outside thescope of this work. The PLL parameters are set to k = 3 andm = 9. The measured delay versus core voltage for each delayelement in the FPGA is shown in Fig. 13. The equivalent VCOfrequency varies by ≈42% over the operating range of Vcore.

The PLL operation and successful locking after startup isshown in Fig. 14. The lock ok signal is asserted 160 µs afterstartup. The communication process is shown in Fig. 15, whichshows the PLL locking to both values of fs. The powerconsumption of the entire FPGA is 72 mW, which would begreatly reduced in a custom IC, while a set of 4 typical TTLlogic opto-isolators consume at least 130 mW. The data outbit-stream is correctly reconstructed with a ≈ 200 µs delay.In a typical application, the DAB converter would operate atthe nominal fs, and initiate the frequency modulation onlywhen data transmission is needed.

−200 −150 −100 −50 0 50 100 150 20050

60

70

80

90

100

Pout

(W)

Effic

iency (

%)

fs = 125 kHz

fs = 135 kHz

Fig. 12. Measured efficiency of the DAB converter at two different switchingfrequencies.

0.8 0.9 1 1.1 1.2 1.31.4

1.6

1.8

2

2.2

2.4

2.6

2.8x 10

−9

Vcore

(V)

Tim

e D

ela

y (

s)

Fig. 13. Measured unit time delay versus core voltage for the VCO in theprimary-side controller.

Vcore

comp

clk_sync

lock_ok

Vgs3

160 µs

Fig. 14. Measured PLL locking in the DAB converter, showing synchroniza-tion of the two bridges without any digital isolators resulting in the activationof the DAB converter.

Vcore

lock_ok

data_in

data_out

44 mV

fs = 135 kHz

fs = 125 kHz

Fig. 15. Frequency-modulation based data communication. Vgs3 denotes thegate-to-source voltage of MOSFET M3, controlled by gate signal c3.

VI. CONCLUSIONS

A novel synchronization scheme based on power trans-former sensing was demonstrated for isolated converters. ThePLL based synchronization scheme is a promising alternativeto opto-isolators and emerging RF based digital isolators,increasing the system reliability and potentially reducing thecontroller power consumption. Low-frequency communicationwas also demonstrated with minimal additional complexity.The effect of the transformer leakage inductance on the PLLaccuracy is an interesting area for further study. Compared tothe approach of Fig. 3, the PLL frequency in Fig. 4 is limitedto the switching frequency, which heavily restricts both thelocking speed and the data transmission rate, however this maybe justified by the reduced cost and simplicity of operatingwithout any digital isolators.

ACKNOWLEDGEMENT

This project was supported by Solantro Semiconductor,Ontario Centres of Excellence and the Canada Foundation forInnovation.

REFERENCES

[1] F. Krismer and J. Kolar, “Efficiency-optimized high-current dual activebridge converter for automotive applications,” IEEE Transactions onIndustrial Electronics, vol. 59, no. 7, pp. 2745–2760, 2012.

[2] F. Krismer and J. Kolar, “Accurate small-signal model for the digitalcontrol of an automotive bidirectional dual active bridge,” IEEE Trans-actions on Power Electronics, vol. 24, no. 12, pp. 2756–2768, 2009.

[3] H. Qin and J. Kimball, “Generalized average modeling of dual ac-tive bridge dc-dc converter,” IEEE Transactions on Power Electronics,vol. 27, no. 4, pp. 2078–2084, 2012.

[4] Y.-C. Wang, Y.-C. Wu, and T.-L. Lee, “Design and implementation of abidirectional isolated dual-active-bridge-based dc/dc converter with dual-phase-shift control for electric vehicle battery,” in 2013 IEEE EnergyConversion Congress and Exposition (ECCE), Sept 2013, pp. 5468–5475.

[5] D. Costinett, K. Hathaway, M. Rehman, M. Evzelman, R. Zane, Y. Lev-ron, and D. Maksimovic, “Active balancing system for electric vehicleswith incorporated low voltage bus,” in 2014 Twenty-Ninth Annual IEEEApplied Power Electronics Conference and Exposition (APEC), March2014, pp. 3230–3236.

[6] S. Poshtkouhi, M. Fard, H. Hussein, L. Dos Santos, O. Trescases,M. Varlan, and T. Lipan, “A dual-active-bridge based bi-directionalmicro-inverter with integrated short-term li-ion ultra-capacitor storageand active power smoothing for modular pv systems,” in Applied PowerElectronics Conference and Exposition (APEC), 2014 Twenty-NinthAnnual IEEE, March 2014, pp. 643–649.

[7] A. Thaduri, A. Verma, G. Vinod, and R. Gopalan, “Reliability predictionof optocouplers for the safety of digital instrumentation,” in 2011 IEEEInternational Conference on Quality and Reliability (ICQR), Sept 2011,pp. 491–495.

[8] P. Jacob, G. Nicoletti, and M. Rutsch, “Reliability failures in smalloptocoupling and dc/dc converter devices,” in 2006. 13th InternationalSymposium on the Physical and Failure Analysis of Integrated Circuits,July 2006, pp. 167–170.

[9] S. Hui, S. C. Tang, and H.-H. Chung, “Optimal operation of coreless pcbtransformer-isolated gate drive circuits with wide switching frequencyrange,” IEEE Transactions on Power Electronics, vol. 14, no. 3, pp.506–514, May 1999.

[10] Y. Moghe, A. Terry, and D. Luzon, “Monolithic 2.5kv rms, 1.8v;3.3vdual-channel 640mbps digital isolator in 0.5 um sos,” in IEEE Interna-tional SOI Conference (SOI), Oct 2012, pp. 1–2.

[11] T. V. Nguyen, J.-C. Crebier, and P.-O. Jeannin, “Design and investigationof an isolated gate driver using cmos integrated circuit and hf trans-former for interleaved dc/dc converter,” IEEE Transactions on IndustryApplications, vol. 49, no. 1, pp. 189–197, Jan 2013.

[12] S. Nagai, T. Fukuda, N. Otsuka, D. Ueda, N. Negoro, H. Sakai, T. Ueda,and T. Tanaka, “A one-chip isolated gate driver with an electromagneticresonant coupler using a spdt switch,” in 2012 24th InternationalSymposium on Power Semiconductor Devices and ICs (ISPSD), June2012, pp. 73–76.

[13] K. Muhammad and D.-C. Lu, “Magnetically isolated gate driver withleakage inductance immunity,” IEEE Transactions on Power Electronics,vol. 29, no. 4, pp. 1567–1572, April 2014.

[14] B. Chen, “icoupler products with isopower technology: Signal andpower transfer across isolation barrier using microtransformers,” AnalogDevices Inc., 2006, available http://www.analog.com/static/imported-files/overviews/isoPower.pdf.

[15] D. Costinett, M. Rodriguez, and D. Maksimovic, “Simple digital pulsewidth modulator under 100 ps resolution using general-purpose fpgas,”IEEE Transactions on Power Electronics, vol. 28, no. 10, pp. 4466–4472,Oct 2013.

[16] O. Trescases, G. Wei, and W.-T. Ng, “A segmented digital pulsewidth modulator with self-calibration for low-power smps,” in IEEEConference on Electron Devices and Solid-State Circuits, Dec 2005, pp.367–370.

[17] H. Chen, S. Li, Q. Niu, Y. Wu, and F. Zhou, “A multi-phase self-sensingclock generator for hybrid dpwm application,” in ASIC, 2007. ASICON’07. 7th International Conference on, Oct 2007, pp. 635–638.

[18] W. Stefanutti, S. Saggini, P. Mattavelli, and M. Ghioni, “Power linecommunication in digitally controlled dc-dc converters using switchingfrequency modulation,” IEEE Transactions on Industrial Electronics,vol. 55, no. 4, pp. 1509–1518, April 2008.

[19] S. Poshtkouhi and O. Trescases, “A dual active bridge dc-dc converterwith optimal dc-link voltage scaling and flyback mode for enhancedlow-power operation in hybrid pv/storage systems,” in press, May 2014.