PLACEMENT - Narula Institute of Technology › pdf › M.TECH-ECE-BROCHURE.pdf · contest,...
Transcript of PLACEMENT - Narula Institute of Technology › pdf › M.TECH-ECE-BROCHURE.pdf · contest,...
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
Dr. Saradindu Panda -
Being the Head of the
Department of Electronics and
Communication Engineering
(ECE), I am delighted to express my thoughts about the
departmental growth.
It offers four years full time B.Tech program in
ECE. The course is accredited by NBA.
The average passing result is excellent in the
department. Almost 10-15% students scored above 9 DGPA. Apart from this we are running P.G.
Programs, M. Tech. in Electronics & Comm.
Engineering since 2009 and M.Tech in
Microelectronics & VLSI since 2012. The
department of ECE offers premier professional technical training that keeps in pace with the latest
developments in the field of Electronics and
Communication Engineering. We have excellent
infrastructure, highly experienced faculties and
professionals, associated with research work which
collectively ensure dynamic and vibrant environment in the campus. Some of the Faculty
members of this department went to attend
International Conferences in abroad. The
department organized so many International &
National Educational Programs (i.e. IEEE sponsored Seminars, Workshops, Faculty Development
Programs and one day educational Industrial
tours). There are so many events like Paper
presentation, Poster presentation, Technical Quiz
contest, Technical Report writing Contest &
Technical Workshop cum contest associated with IIT, Bombay are organized for the the students by
this department. There are more than 150
publications are done by the the faculty & students
in National & International Journals &
Conferences. Furthermore four MODROB Projects are going on in this department. Many of
our Alumni are settled in abroad and also many of
the students are placed in so many reputed
Govt sectors and Private Sectors Company and
Research Organizations. There is also separate
Departmental Library apart from the Central Library in the ECE department. There are so many
high valued simulation software are present in our
department like Tanner SPICE, CADENCE, Matlab
2014b, Visual TCAD, HFSS, Qualnet, Active HDL,
MPLS, Altera & Quartus II, TMS Kit with Code Coposer Studio etc. We have very prestigious PCB
design Laboratory with full set up.
PLACEMENT:
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
CENTER OF EXCELLENCE LAB: The department of ECE have two Center of Excellence Lab named: Advanced Communication & Signal Systems Lab & Nano Device Simulation & Integrated systems development Lab
Advanced Communication & Signal Systems Lab
This lab has been established to give idea to the
students & researchers of Electronics & Communication Engineering, those who would like
to develop themselves in the configuration and
simulation of –
Studies on satellite communication System:
To setup Active and passive Satellite Communication Link.
To communicate Voice signal through Satellite link.
To transmit and receive various Wave from a function Generator through a satellite link
using different combination of uplink and
down link frequency.
To Transmit and Receive PC to PC Data through Satellite link.
Studies on cellular mobile communication
System:
Working principle, input /output Signal of different sections, Transmitter and Receiver
section.
Study of SIM Card and its Detection, SIM reset, SIM Clock, SIM Data, and SIM Supply.
Studies on GSM: Understanding of GSM
Technology Signal like its network, network
commands:
Modem Commands, Simcard hardware commands, Network registration commands,
Call control commands, Phone book commands, and Message handling
commands.
Study of GPS system:
To determine the current location of the GPS receiver.
Study of the receiver and transmitter
parameters of a typical radio communication
system:
Selectivity, sensitivity and fidelity
In this laboratory there is provision to configure and simulate the experiments like:
ADPCM – granular noise and quantization noise.
Digital filters – ripples in pass band and stop band, slope in transition band, poles and
zeros.
Optimum filter for receiving base band random binary data
Throughput vs input density in different types of chip code.
Cellular architecture, WiFi, WiMAX using QUALNET.
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
OFDM using QUALNET.
Different routing algorithms and protocol.
To generate a QPSK signal using the Agilent 89600 VSA software Agilent IO Libraries
Suite software
This lab has been established to give idea to the
students & researchers of Electronics &
Communication Engineering, those who would like
to develop themselves in the configuration and simulation of –
Multimedia-Multidimensional Signal Processing spanning from text, document,
graphics and animation through speech,
audio, image and video signals
Signal Analysis and Decision support systems for biological/biomedical/genomic
Automotive/industrial and metallographic signals
Signal Processing Applications in
RF/Microwave/Optical Communication
DSP/Reconfigurable/Full custom VLSI Hardware Technologies for Signal/Image
Processing Applications Development
Nano Device Simulation & Integrated systems development Lab This lab has been established to give idea to the
students & researchers of Electronics &
Communication Engineering, those who would like
to develop themselves in the configuration and
simulation of Very Large Scale Integrated Circuits
& Systems, Nano device simulation & design parameter extraction & System programming for the
embedded systems.
In this laboratory there is provision to configure
and simulate CMOS Circuit & Systems using Mixed signal design methodology.
It is possible to design of layout of various CMOS
Circuits in micron, submicron and deep
submicron level using Tanner Tools & CADENCE.
The Spice Simulation of different types of complex
digital & analog circuits and Circuit Layout design of
different types of digital & analog circuits using EDA
Tools (i.e. TSPICE, CADENCE) will be carried out.
Also it serves as a guide to make it understood
the complete process to work through in designing
onto Programmable logic devices like that is
CPLDs and FPGAs, right from the simulation
(zero delay to the implementation aspects).
The complete FPGA design process, including adding timing constraints, pin assignment,
synthesis, placement & routing, bit-stream
generation, will be carried out.
This Lab helps to reduce uncertainties by providing
knowledge as well as efficient software development and system integration.
To fabricate and characterize the circuits, we
have world class PCB Design facilities.
EDA software (tools) can be used to solve the
problems encountered during synthesizing,
analyzing, verifying and testing a design. We are
seeking more powerful algorithms for solving these
problems to minimize chip size and power
consumption while optimizing chip performance.
Facilities for PG Students:
1) Computational facility
Advanced Communication & Signal Processing
Lab has 20 computers with Windows and Unix operating systems and also houses the mail and web
servers. Its computers have modeling and simulation
software including finite element analysis, ANSYS
HFSS, QUALNET & MATLAB.
Nano-Devices and VLSI Circuit Simulation Lab
has 20 computers with Windows and Unix operating
systems and also houses the mail and web servers.
Its computers have modeling and simulation
software including finite element analysis and Visual TCAD.
Also pursued in the lab are projects in algorithms for
simulation and scientific computing including
graphical processor unit (GPU) based computing.
Apart from the local computing resources, we use
the intra-departmental computing facility provided
from the ISI (Kolkata), Jadavpur University (Kolkata)
and IIEST (Kolkata).
2) Simulation Software facility :
ANSYS HFSS
Achieve high-frequency, high-speed component
design with state-of-the-art tools from ANSYS.
Integration into ANSYS Workbench. The complete high-frequency solver toolbox enables
simulation across multiple applications.
Leverage the accuracy of HFSS from ECAD interface
with Solver on Demand.
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
With our advanced solver options, you can take on the largest and most complex design problems.
HPC options leverage compute power to rapidly solve
large-scale EM field simulations with rigor and
accuracy.
HFSS is an integral part of the ANSYS suite, which
solves multiphysics problems with ease.
QUALNET
The QualNet® communications simulation platform
(QualNet) is a planning, testing and training tool that
"mimics" the behavior of a real communications
network. Simulation is a cost-effective method for
developing, deploying and managing network-centric
systems throughout their entire lifecycle. Users can evaluate the basic behavior of a network, and test
combinations of network features that are likely to
work. QualNet provides a comprehensive
environment for designing protocols, creating and
animating network scenarios, and analyzing their performance.
QualNet is composed of the following components:
QualNet Architect, QualNet Analyzer, QualNet Packet
Tracer, QualNet File Editor, QualNet Command Line Interface.
QualNet enables users to:
Design new protocol models, Optimize new and
existing models, Design large wired and wireless
networks using pre-configured or user-designed models, Analyze the performance of networks and
perform what-if analysis to optimize them.
Code Composer Studio™ -Integrated
Development Environment
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller
and Embedded Processors portfolio. Code Composer
Studio comprises a suite of tools used to develop and
debug embedded applications. It includes an
optimizing C/C++ compiler, source code editor,
project build environment, debugger, profiler, and many other features. The intuitive IDE provides a
single user interface taking you through each step of
the application development flow. Familiar tools and
interfaces allow users to get started faster than ever
before. Code Composer Studio combines the advantages of the Eclipse software framework with
advanced embedded debug capabilities from TI
resulting in a compelling feature-rich development
environment for embedded developers.
Features by Platform
The features available for a specific processor family: MSP430 Ultra Low Power MCUs, C2000 Real-time
MCUs, SimpleLink Wireless MCUs, TM4x MCUs,
TMS570 & RM4 Safety MCUs, Sitara (Cortex A &
ARM9) Processors, Multicore DSP and ARM
including KeyStone Processors: For F24x/C24x
devices and for C3x/C4x DSPs.
Visual TCAD for process/device simulation
Visual TCAD is the latest graphical user interface for
the Genius device simulator. Visual TCAD is
designed to suit novice TCAD users and students,
and focuses on ease of use. Using TCAD has never
been as easy, no more command line or coding is required. Beginners will be able to get started within
just a few minutes. On the other hand, it doesn't
sacrifice the power of Genius. All the physical models
and options are accessible with Visual TCAD.
Visual TCAD combines with the Genius Device
Simulator to create a next-generation TCAD solution. Genius is a parallel 2D/3D TCAD device simulator,
featuring a wide range of advanced physical models
and simulation capabilities. Incorporating the latest
parallel computation technology, the Genius Device
Simulator is able to handle large problems with 200,000 or more mesh nodes and is capable of
speeding up simulation times by a factor of 10 or
more.
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
Genius provides unprecedented capability and performance with leading parallel computing
technologies. Genius is the first commercial TCAD
device simulator that scales beyond the 10-transistor
barrier. With Genius, one is able to routinely
simulate circuit cells like inverter, 6T SRAM, latch
and flip-flop, and expect 10 fold reduction in simulation run times.
Unlike many TCAD products in the market, the
Genius Device Simulator is a completely new design.
Parallelism, scalability and extensibility were
considered in its design goals at a very early stage. Furthermore, Genius has been constructed using the
atest numerical simulation techniques and software
development tools.
Gds2Mesh is a 3D TCAD model construction tool. It
takes GDSII mask layout as input, and construct the
device model with predefined and customizable process rules.
The 0.13um process rule extracts the various layers
in the mask set, and constructively build the device
geometry objects via extrusion and other geometric
operations. The placement of doping profiles is also
based on the masks layouts. The geometric engine is capable of re-creating
slanted STI side-walls, rounded STI corners, bird's
beak and other details. Mesh is generated
automatically, and mesh in the channel and junction
regions are refined for accurate simulation. The generated device structure can be imported in
Genius for device simulation.
GSeat is a Monte-Carlo simulator for studying high-
energy particles passing through semiconductor
devices, and is part of the SEE (Single-Event Effects)
solution of Cogenda. Visual Particle provides a user-friendly GUI to GSeat.
CRad provides an integrative framework for the
analysis of space radiation environment and
radiation effects in microelectronics components. It
features an intuitive flow-chart based GUI, following the necessary steps in the analysis of single event,
total dose and NIEL effects.
VisualFab is an integrated workbench for process
simulation experiments. It adopts the concepts
familiar to fab engineers, e.g. process module, split,
wafer and split table. It also allows user to visualize these concepts and design experiments in a user-
friendly GUI.
CADENCE Virtuoso Multi-mode Simulation with AP
Simulator:
Cadence® Virtuoso® AMS Designer is a mixed-signal simulation solution for the design and verification of
analog, RF, memory, and mixed-signal SoCs. It is
integrated with the Virtuoso full-custom
environment for mixed-signal design and verification.
It is also integrated with the Cadence Incisive® functional verification platform for mixed-signal
verification within the digital verification
environment.
Virtuoso Schematic Editor XL
Cadence® Virtuoso® Schematic Editor provides
numerous capabilities to facilitate fast and easy
design entry, including design assistants that speed
common tasks by as much as 5x. Well-defined
component libraries allow faster design at both the gate and transistor levels. Sophisticated wire routing
capabilities further assist in connecting devices. For
larger and more complex designs, Virtuoso
Schematic Editor not only supports multi-sheet
designs but also provides the ability to design hierarchically, with no limit on the number of levels
used. The Hierarchy Editor makes hierarchical
designs easy to traverse, and automatically ensures
all connections are maintained accurately
throughout the design.
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
Virtuoso Analog Design Environment XL Designed to help users create manufacturing-robust
designs, Cadence® Virtuoso® Analog Design
Environment is the advanced design and simulation
environment for the Virtuoso platform. It gives
designers access to a new parasitic estimation and
comparison flow and optimization algorithms that help to center designs better for yield improvement
and advanced matching and sensitivity analyses. By
supporting extensive exploration of multiple designs
against their objective specifications, Virtuoso Analog
Design Environment sets the standard in fast and accurate design verification.
Virtuoso Layout Suite XL
As the high-end custom block authoring physical layout tool of the Cadence® Virtuoso® platform,
Cadence Virtuoso Layout Suite supports custom
digital, mixed-signal and analog designs at the
device, cell, and block levels. Its advanced features
include automation to accelerate custom block
authoring, as well as industry-leading Cadence space-based routing technology that automatically
enforces 65/45nm process and design rules during
interactive and automatic routing. Working in
concert with other components of the Virtuoso
platform, Virtuoso Layout Suite enables the creation of differentiated custom silicon that is both fast and
silicon-accurate.
Virtuoso Digital Implementation
Virtuoso Digital Implementation delivers a capacity-
limited, automatic, RTL-to-GDSII implementation
solution for small digital blocks that complements an analog-driven mixed-signal design methodology with
the Virtuoso platform. Virtuoso Digital
Implementation leverages Cadence Encounter® RTL
Compiler for physical synthesis and Encounter
Digital Implementation System functionality for
physical implementation. Used in combination, these technologies speed turnaround time from synthesis
to optimization to verification, and deliver high-
quality, high-performance, and lower-power digital
blocks for mixed-signal designs.
Cadence provides two sophisticated debug solutions
to address all of your RTL, testbench, and SoC
verification debug needs:
SimVision: a unified graphical debugging
environment within Enterprise Simulator that supports signal-level and transaction-based flows
across all IEEE-standard design, testbench, and
assertion languages, in addition to concurrent
visualization of hardware, software, and analog
domains. Learn more »
Incisive Debug Analyzer: a new, unique, “interactive” post-process debug solution to help you debug in
minutes instead of hours. Learn more »
Enterprise Simulator supports all IEEE-standard
languages, the Open Verification Methodology (OVM),
Accellera’s Universal Verification Methodology (UVM), and the e Reuse Methodology (eRM), making it quick
and easy to integrate with your established
verification flows.
Cadence Physical Verification System (PVS)
integrates with industry-standard Cadence
Virtuoso® custom/mixed-signal and Cadence
Encounter® digital design flows.
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
Tanner Spice
T-Spice: Analog Simulation: T-Spice offers
HSPICE® and PSpice® compatible syntax and
supports the latest industry models, including PSP,
BSIM3.3, BSIM4.6, BSIM SOI 4.0, EKV 2.6, MOS 9, PSP, RPI a-Si & Poly-Si TFT, VBIC, and MEXTRAM
models to allow easy integration of legacy designs
and foundry models.
T-Spice lets you precisely characterize circuit
behavior using virtual data measurements, Monte Carlo analysis, and parameter sweeping.
For greater efficiency and productivity, T-Spice puts
you in control over your simulation process with an
easy-to-use graphical interface and a faster, more
intuitive design environment.
With key features such as multi-threading support, automatic selection of advanced convergence
algorithms, and “.alter― command for easy
what-if simulations with netlist changes, T-Spice
saves you time and money during the simulation
phase of your design flow. Additional T-Spice Engine licenses can boost your
innovation and experimentation capability with
greater simulation capacity. Perform simultaneous
runs and increase simulation run-time by adding up
to ten (10) more engines. Click here to contact our
Sales Team regarding this capability. T-Spice supports Verilog-A behavioral
modeling. Click here to read the whitepaper on this
important productivity aid.
S-Edit: Schematic Capture: S-Edit's tight
integration with SPICE simulation allows viewing
operating point results directly on the schematic and performing waveform cross-probing to view node
voltages and device terminal currents or charges.
S-Edit imports schematics via Open Access and via
EDIF from third party tools, including Cadence, Mentor, Laker, ORCAD and ViewDraw with
automatic conversion of schematics and properties
for seamless integration of legacy data.
S-Edit's schematic design checks enables you to
check your design for common errors such as
undriven nets, unconnected pins and nets driven by multiple outputs so you can catch errors early before
running simulations.
W-Edit: Waveform Viewing & Analysis
The W-Edit waveform analysis tool is a
comprehensive viewer for displaying, comparing, and analyzing simulation results. W-Edit provides an
intuitive multiple-window, multiple-chart interface
for easy viewing of waveforms and data in highly
configurable formats.
W-Edit is dynamically linked to T-Spice and S-Edit
with a run-time update feature that displays simulation results as they are being generated and
allows waveform cross-probing directly in the
schematic editor for faster design cycles.
Focus on and optimize your design with W-Edit's
advanced features such as automatically calculating
and displaying FFT results in a variety of formats, including dB or linear magnitude, wrapped or
unwrapped phase, and real or imaginary parts.
W-Edit allows creation of new traces based on
mathematical expressions of other traces for
advanced analysis and easy comparison with measured data.
L-Edit: Layout Design & Analysis
L-Edit is a complete hierarchical physical layout
editor combining fast rendering and built-in
productivity tools to let you maximize your efficiency
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
when creating the layout for your design. Take full advantage of L-Edit's optimized editing
which allows you to edit layout with fewer mouse
clicks than any other layout editor, for maximum
efficiency.
Speed up design cycles with built-in productivity
tools such as object snapping, alignment tools, automatic guard ring generation, complex boolean
operations on objects or layers, and cross-probing
between schematic and layout.
L-Edit supports parameterized cells allowing you to
create automatic custom layout generators or use DevGen to easily setup layout generators for most
common devices such as MOSFETs, resistors, or
capacitors.
L-Edit's built-in Interactive DRC displays violations
in real time while you edit your layout, helping you
create compact, error-free layouts the first time. L-Edit's Node Highlighting capability allows you to
highlight all geometry connected to a node so you
can quickly find and fix LVS problems such as
shorts and opens.
Physical Verification: HiPer Verify
HiPer Verify is a comprehensive yet affordable
solution for analog/mixed signal IC design rule
checking (DRC) and netlist extraction. HiPer Verify runs Calibre®, Assura®, and Dracula®
foundry files natively, without conversion or
modification.
HiPer Verify's hierarchical rule checking engine finds
violations in the cell where they occur, enabling you to correct a violation once rather than sorting
through many duplicate violations as flat processing
requires.
HiPer Verify is integrated with the L-Edit Layout
Editor, allowing for precise location of errors, quick
turnaround of corrections, and faster debugging.
Schematic Drive Layout: SDL & SDL Router SDL is integrated with the L-Edit Layout Editor and
provides tools to increase the speed and quality of
custom layout by allowing the designer to manage
the routing flow and to focus on layout quality.
SDL imports a netlist from any schematic tool and
automatically instances all needed subcells, including parameterized cells using the parameters
associated with each device in the netlist.
SDL displays flylines allowing you to place your
blocks to minimize routing congestion.
SDL can perform engineering change orders (ECO) and highlight differences in the netlists for faster
layout of design changes.
Check for connectivity issues using SDL’s Short and
Open Checker
SDL Router is an automatic routing engine
integrated with SDL that speeds layout of analog cells and top-level chip assembly routing.
SDL Router allows the designer to focus on routes
that require expensive hand craftsmanship for
performance or addressing analog-sensitive nets or
parts of nets, then letting the SDL Router
automatically route the non-critical nets. SDL Router can route different nets with different
user specific widths with support for multiple vias
used for layer transitions.
SDL Router allows designers to mark existing
geometry as part of a specific net allowing selection, highlighting, and rip-up of geometry by net to
capture the designer's intent.
Physical Verification: HiPer PX
HiPer PX is a high performance parasitic extraction tool that is offered as an optional add-in (please
speak with your sales representative for licensing
options and pricing). HiPer PX is integrated with
Tanner's L-Edit layout editor for easy and rapid
extraction of parasitics. HiPer PX quickly extracts simulation-ready SPICE
netlists from layout, including devices (MOSFETs,
bipolars, etc) and interconnect parasitics.
HiPer PX extracts accurate, complete parasitic
networks for each node, including vertical and lateral
coupling capacitance and interconnect resistance. HiPer PX can simplify the parasitic RC network
without reducing simulation accuracy up to a user-
specified frequency with the built-in netlist reduction
algorithm.
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
Matlab
Tool Box: Simulink, Control System Toolbox,
Symbolic Math Toolbox, Simscape,
SimPowerSystems, Signal Processing Toolbox, DSP System Toolbox, Neural Network Toolbox, Fuzzy
Logic Toolbox, Partial Differential Equation Toolbox,
Optimization Toolbox, Statistics Toolbox, Image
Processing Toolbox, Computer Vision System
Toolbox, Bioinformatics Toolbox, Communications System Toolbox, SimElectronics.
ISE Design Suite: WebPACK Edition
ISE WebPACK delivers a complete, front-to-back
design flow providing instant access to the ISE
features and functionality at no cost. To learn more,
please visit ISE WebPACK Design Software landing page.
The ISE Design Suite also offers a-la-cart tools to
enhance designer productivity and to provide flexible
configurations of the Design Suite Editions.
High-Level Synthesis – Vivado™ High-Level Synthesis accelerates IP creation by enabling C, C++
and System C specifications to be directly targeted
into Xilinx All Programmable devices without the
need to manually create RTL.
Partial Reconfiguration – Xilinx Partial
Reconfiguration technology allows designers to change functionality on the fly, eliminating the need
to fully reconfigure and re-establish links,
dramatically enhancing the flexibility that FPGAs
offer.
ChipScope – The ChipScope Pro Serial I/O Toolkit provides a fast, easy, and interactive setup and
debug of serial I/O channels in high-speed FPGA
designs for use with the WebPACK edition.
Embedded Development Kit – The Embedded
Development Kit (EDK) is an integrated development
environment for designing embedded processing systems for use with WebPACK edition.
System Generator for DSP – The industry’s leading
high-level tool for designing high-performance DSP
systems using Xilinx devices for use with the
WebPACK edition.
Active HDL:
FPGA Design Creation and Simulation
Active-HDL™ is a Windows® based, integrated FPGA
Design Creation and Simulation solution for team-
based environments. Active-HDL’s Integrated Design
Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language
simulator for rapid deployment and verification of
FPGA designs.
The design flow manager evokes 120+ EDA and
FPGA tools, during design entry, simulation,
synthesis and implementation flows and allows
teams to remain within one common platform during
the entire FPGA development process. Active-HDL supports industry leading FPGA devices from
Altera®, Atmel®, Lattice®, Microsemi™ (Actel),
Quicklogic®, Xilinx® and more.
3) Hardware Development & Application Board Facility:
TMS320C6713 DSP Starter Kit (DSK) includes
C6713 DSP Development Board with 512K Flash and 16MB SDRAM, C6713 DSK Code Composer Studio™
IDE including the Fast Simulators and access to
Analysis Toolkit on Update Advisor, Quick Start
Guide, Technical Reference, Customer Support
Guide, USB Cable, Universal Power Supply, AC
Power Cord(s), MATLAB from The Mathworks. TMDSDSK6713 includes a standard US power cord,
TMDSDSK6713-0E version includes both UK &
European power cords. Embedded JTAG support via
USB, High-quality 24-bit stereo codec, Four 3.5mm
audio jacks for microphone, line in, speaker and line
out, 512K words of Flash and 16 MB SDRAM, Expansion port connector for plug-in modules, On-
board standard IEEE JTAG interface, +5V universal
power supply.
TMS320VC5416 DSP Starter Kit (DSK) includes
C5416 DSP Development Board -C5416 DSK Code
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
Composer Studio™ v2.1 IDE, Quick Start Guide, Technical Reference, Customer Support Guide, USB
Cable, Universal Power Supply, AC Power Cord(s),
Embedded JTAG support via USB, High-quality 16-
/20-bit stereo codec, Four 3.5mm audio jacks for
microphone, line in, speaker and line out, 256K
words of Flash and 64K words RAM, Expansion port connector for plug-in modules, On-board standard
JTAG interface, +5V universal power supply.
The TMS320C5416 features the TMS320C5416 DSP
- the designer's choice for applications that require
an optimized combination of power performance and area. With 160 MIPS performance, designers can use
the 160 MHz device as the foundation for a range of
signal processing applications, including speech
compression/decompression, speech recognition,
text-to-speech conversion, fax/data conversion and
echo cancellation.
Scientech 2211 demonstrates FDM technique. It basically fulfills the need for communication of two
different inputs through a single channel by
Frequency Division Multiplexing method. 2211 has
the provision for onboard modulating signal as well
as voice input. For reducing the complexity same carriers are used for demodulation also. In actual
FDM communication method carrier is obtained
through the modulated output only. But the basic
concept remains the same. DSB-SC modulation
technique is used for modulation and demodulation.
Features: Self-contained and easy to operate, Two variable modulating (sinusoidal) input channels with
provision of voice inputs, Two DSBSC modulators for
frequency band translation of two test signals, Two
Carrier Generators, Two sets of audio input
amplifier, One adder/transmission amplifier, Two Demodulators, Two low pass filters for smooth
output, 2 Sets of audio O/P amplifier
Scientech 2503 provides all necessary inputs and connections for students to study Analog Time
Division Multiplexing / Demultiplexing, Digital Time
Division Multiplexing/Demultiplexing of signals,
Pulse Position Modulation and Manchester Encoding
/ Decoding techniques.
Features: Functional blocks indicated on board mimic, Crystal Controlled Clock, On board Sine wave
and Digital Signal Generator, 4-channel Time
Division Multiplexing/Demultiplexing (Analog), 16-
channel Time Division Multiplexing/ Demultiplexing
(Digital), Manchester Coding and Decoding, Pulse Position Modulation, Can be used with Fiber Optic &
various other Communication Links.
Understanding Mobile Phone Scientech 2132 provides basic theory & working fundamentals of a
2G handset based on the most popular handset
Nokia 3310/3315. It provides network, power
supply, charging & user interface circuit`s for their
detailed block wise study. Features: Real time mobile operation, Expanded and
open TechBook, Full explaination of mobile phone
working, Frequency measurement and band
verification, Provides study of all sections in mobile
phone, TX/RX Frequency measurement, 2G
technology & GMSK signals, GSM data rate, Detail study of User Interface Control signals, Detail study
of SIM operation, Battery identification and charging
study, Switched Faults.
Scientech 2501 Optical Fiber Communication TechBook demonstrate simplex method of
transmitting information from one place to another
by sending pulses of light through an Optical fiber.
The TechBook demonstrates the properties of
Simplex Analog and Digital Transreceiver, characteristics of Fiber Optics cable, Modulation /
Demodulation techniques. A large number of
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
experiments are included in the workbook and many more can be performed using Scientech 2501.
Features: Simplex Analog and Digital Transreceiver,
660 nm channel with Transmitter & Receiver, AM-
FM-PWM modulation / demodulation, On board
Function Generator, Crystal Controlled Clock,
Functional Blocks indicated on-board mimic, Input-output & test points provided on board, On board
voice link, Built in DC power supply, Numerical
Aperture measurement jig and mandrel for bending
loss included, Switched faults on Transmitter &
Receiver
Scientech 2276 Understanding Global Positioning
System (GPS) technology is rapidly changing how
people find their way around the earth. Whether it is
for fun, saving lives, getting there faster, or whatever
uses you can dream up, GPS navigation is becoming
more common everyday. GPS Trainer Kit will provide a basic understanding of the GPS Fundamentals,
Satellites & Design Aspects of GPS Receiver by
actually connecting to the Satellite by GPS Antenna.
Features: 12 channel GPS & carrier, Fast
Cold/Warm/Hot start TTFF time of 45/38/8 sec,
Fast requisition time of 0.1 second, NMEA 0183 Ver 2.2 GGA, GLL, GSA, GSV, RMC and VTG sentences
output, SiRf binary protocol output, On board real
time RTCM SC-104 differential, 1PPS (one pulse per
second) signal, USB Powered, USB for PC
Communication, GPS Software for analysis, Battery operated (optional), Zigbee interface (optional)
Scientech 2506 LASER fiber optic platform model
has been designed to conduct studies on LASER diodes, optical fibers and optical communication
methods, by transmission either through an optical
cable or free space. The experiments introduce the
student to the concepts underlying LASER
technology in simple way. The platform includes
accessories to conduct experiments, however instrument like DMM are needed extra.
Features: 660 nm Laser diode source with external signal modulation facility, Selectable Automatic
Power control/ Automatic Current control mode,
SMA connector for coupling optical power in to fiber,
Optical intensity/ Carrier level control facility, Laser
diode current and monitor photo detector current
monitoring facility, Free space communication facility through a line-of-sight path, On-board Photo
detector & Power meter.
BT - 2001, Bluetooth Technology Experimental
Equipment is developed for student education about
hardware experiments and software protocol stock
practices of Bluetooth technology. It can be used for development tool also.
The Hardware experiments include theory and
experiment about Audio communication, Data
communication with the UART, USB, SPI and Radio
Frequency communication.
The Software practices are divided largely into monitoring practice and emulation practice and in
order to improve learning efficiency of students.
Each Monitoring practice consists of 3 steps;
Step1 and 2 focus on basic understanding of stack
and Step3 enables students to monitor the data communicated actually.
The Emulation practice enables student to
understand exactly the sequential flow of Bluetooth
protocol stacks to conduct programming for real
communication. All the program required for the
practices are provided with this product saved int the C. The Software practices include HCI Protocol,
L2CAP Protocol, RFCOMM Protocol, SDP Protocol.
Features: RF Hardware Experiments, DATA
Communication ( UART , USB , SPI ), Full Duplex
Audio Conversion, Monitiring Experiments of HCI, L2CAP , RFCOMM , SDP, Protocol Analysis and
Emulation, Used for students and researcher, Used
in PC Circumstances (Win98, Windows 2000,
Windows XP), Network Program upgrade
Experiments
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
Scientech 2272A Satellite Communication platform provides an indepth study of basic Satellite
Communication system. It consists of Uplink
Transmitter, Satellite Link and Downlink Receiver,
which can be conveniently placed in the laboratory.
The Satellite can be placed at an elevated, position if
needed. The Satellite Transponder receives signal from Uplink Transmitter and retransmits at different
frequencies to a Downlink Receiver. The Uplink and
Downlink frequencies are selectable and can have
variety of signals such as Video, Audio, Voice, Tone,
Data and Telemetry (Temperature and Light intensity).
Features: Simultaneous communication of three
different signals, Communicate Audio, Video, Digital
data, PC data, Tone, Voice, function generator
waveforms etc, 2414 - 2468MHz PLL microwave
operation, Communication of external broad band digital signal, Choice of different transmitting and
receiving frequencies, Built-in Speaker and
Microphone for Voice and Audio link, Remote
detection of Light intensity and environment
temperature, Detachable Dish Antenna at each
station, USB port for PC communication
GSM Mobile Phone System is a unique designed standalone product for in-depth study of GSM
techniques, like transmission of voice & data calls,
SMS (Short Message Service), AT Commands in GSM
network without using Personal Computer. It has
two modes, User mode & AT command mode to understand working of Global System for Mobile
communication. Scientech 2138 also enables user to
study different signal like Transmission Clock,
Receiving Clock, Buzzer, Vibrator, Voice, Sync & SIM
Card indication in GSM Mobile Phone System.
Features: Simple/Easy operation, Built-in Graphical User Interface, User mode and AT command mode,
Facility to study signals in GSM network, Real time
operation, External Antenna, Attractive look & Light
weight, Audio jack
The ZyAIR B-1000 v.2 is an IEEE802.11b compliant
11 Mpbs wireless LAN access point. It is suited for
wireless connections to the wired network in the
home and small office environment. The key features of the ZyAIR are configurable output power,
limitation of client connections, IEEE 802.1x, WEP
data encryption and MAC address filtering.
Features: Wi Fi Protected access, IEEE 802.1xMD-
5/TLS/TTLS/PEAP pass through, RADIUS client, Central Network Management, Adjustable Antenna
for customer requirement, Configurable output
power, Auto scan for interference-free channel,
Dynamic WEP key, 64/128 WEP encryption, MAC
address filtering, DHCP client, Web based configurator, IPSec, PPTP and L2TP pass through.
Switch type supported ISDN Trainer Kit: ETSI euro-
ISDN (subset of CTR3), also supports SPID's for N I
½. BRI interface: Quantity 4 (1xRJ45 socket per
port). B channels: 2 per BRI. Display indicators: P (physical), D (data link), and B1/B2 (B Ch.) per
interface. Protocol analyzer: Layer 2, 3 can be
analyzed N for all networks irrespective of networks
simulated. User interface: Windows application on
computer. Directory numbering: Two numbers per interface normal BRI, dual fixed, dual floating and
ten numbers per interface if using MSN.
Supplementary service support: Euro-ISDN caller
line, Identification, multi Sub Numbering, sub
addressing, user to user signaling, terminal
portability, connected party number, low layer compatibility and high layer compatibility. Power
requirements: 230Vac, 50Hz.
Features: No physical ISDN line required, 4 BRI
ports with S interface, 2 channels for each BRI port,
2 ISDN terminal adapters, 2 ISDN phones and 2 analog phones, Simulates all the functionalities of
regular ISDN lines, Built in protocol analyser,
Analyze layer 2 and 3, LEDs to show the status of
each ISDN port, Display of P, D and B channel,
Emulates euro-ISDN type of network variants,
Simple configuration using windows application, Multimedia based interactive e-manual.
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
4) PCB Design and Circuit Characterization Facility:
We have a world class PCB Design and Circuit
characterization facility. Automatic PCB manufacturing equipment from Crescent includes:
Art work table with application software for
designing layout, PCB Curing Machine, Deep Coating
Machine, Photo Exposure, Photo resist, UV
Exposure, Etching machine, Drilling machine Shearing Machine, DYE DEVELOPER Machine and
Tinning machine, Dark room and chemical process
room facility.
RESEARCH FCILITY FOR THE PG STUDENTS
We have a strong research program in various
aspects of Advanced Communication & Signal
Processing. We are engaged in the complete Signal &
image Processing research including conceiving novel ideas, physics based analysis and simulation
and characterization.
We have a strong research program in various
aspects of micro and nano devices. We are engaged
in the complete spectrum of device research
including conceiving novel device ideas, physics based analysis and simulation, fabrication and
characterization.
The ongoing research include:
Wireless Communications
Software Defined Radio and Cognitive Radio Networks
Wireless Sensor Networks and Protocols
Cyber Physical Systems and other related areas
Signal Processing
Adaptive Signal Processing and techniques
Biomedical Signal Processing
Image processing and other related areas
Optical Fibre Communications
Optical Networks and Systems: PHY layer Issues, MAC Protocols & Resource Allocation
Fiber-to-the-Premises
Optical CDMA Coding for information flow networks
Network Coding for wireline and wireless networks
Network-Error Correction
Index Coding
Local-Error Correction
Convolutional Codes Device Technology
Study of Design parameters of advanced Nano devices like
DGMOSFET, FiNFET, MultiGate
MOSFET using High K dielectric material
High-k dielectric integration on MOSFET gate stack
High-k DRAM
Ge shottky S/D
Heterostructure solar cells
Magnetic materials for RF CMOS
Design of High frequency Diode &
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
Transistors Modeling and Simulation
Compact modeling
Variability in analog circuits
Noise Modelling of advanced Nano MOSFETs
Mixed Signal Analysis in VLSI Circuits
MIMO Circuits
Different Adder & Multiplier Circuits
Power, Delay & Noise Analysis of VLSI Circuits
Adiabatic Logic
Effect of gate engineering in JLSRG MOSFET
Sensors
MEMS Capacitive Shunt Switch
FACULTY MEMBERS:
For M.Tech ECE:
Permanent Faculty:
Prof. (Dr.) P.K.Banerjee
Ex-Professor, Electronics & Telecommunication
Engineering, Jadavpur University, Kolkata.
Prof. (Dr.) J.K.Das Ex Professor, IIT, Mumbai
Prof.(Dr.) A.K.Mallick
Ex Professor, IIT, Kharagpur
Mr. Anilesh Dey,
Assistant Professor, Department of Electronics &
Communication Engineering, Narula Institute of Technology, Kolkata
Mr. Kaushik Sarkar,
Assistant Professor, Department of Electronics &
Communication Engineering, Narula Institute of
Technology, Kolkata Mr. Pranab Hazra
Assistant Professor, Department of Electronics &
Communication Engineering, Narula Institute of
Technology, Kolkata
Mrs. Sandhya Pattanayak,
Assistant Professor, Department of Electronics & Communication Engineering, Narula Institute of
Technology, Kolkata
Mrs. Sangita Roy,
Assistant Professor, Department of Electronics &
Communication Engineering, Narula Institute of Technology, Kolkata
Mrs. Arpita Burman Santra, Assistant Professor, Department of Electronics &
Communication Engineering, Narula Institute of
Technology, Kolkata
Mrs. Swati Barui,
Assistant Professor, Department of Electronics &
Communication Engineering, Narula Institute of Technology, Kolkata
Visiting Faculty Prof. Dr.-Ing. Horst Schwetlick
Senior Experten Service, Bonn, Germany
Dr.Christophe Fumeaux
Professor, School of Electrical and Electronic
Engineering, The University of Adelaide, Australia. Dr. A. Alphones
Professor, School of Electrical & Electronic
Engineering, Nanyang Technological University,
Singapore.
Dr. M.H.Kori
Technology Consultant & Advisor, Validus Technologies, USA.
Prof.(Dr.) M. Mitra
Professor & Head, ECE Deptt, IIEST, Shibpur
Mr. Chanchal Chakraborty
Chief Technology Officer, Reliance Prof.(Dr.) Nabanita Das
Professor, ISI, Kolkata
Dr. Debotosh Guha
Professor, Institute of Radio Physics and Electronics,
University of Calcutta.
Prof. Asoke Dutta
Ex Professor, ISI, Kolkata Prof Phalguni Gupta
Director NITTTR, Kolkata Mr. Debasis Mazumdar
CDAC, Kolkata
FACULTY MEMBERS:
For M.Tech Microelectronics &VLSI
Design :
Permanent Faculty:
Prof. (Dr.) M.R. Kanjilal
Principal, Narula Institute of Technology
Prof.(Dr.) J.Das
Ex Professor, ISI, Kolkata
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in
Dr. Saradindu Panda Head, ECE Department, Narula Institute of
Technology, Kolkata.
Mr. Surajit Bari
Assistant Professor, Department of Electronics &
Communication Engineering, Narula Institute of
Technology, Kolkata Mr. Anilesh Dey,
Assistant Professor, Department of Electronics &
Communication Engineering, Narula Institute of
Technology, Kolkata
Mr. Kaushik Sarkar, Assistant Professor, Department of Electronics &
Communication Engineering, Narula Institute of
Technology, Kolkata
Mr. Soumen Pal
Assistant Professor, Department of Electronics &
Communication Engineering, Narula Institute of Technology, Kolkata.
Mr. Sohan Ghorai
Assistant Professor, Department of Electronics &
Communication Engineering, Narula Institute of
Technology, Kolkata.
Visiting Faculty Prof.(Dr.) Susanta Sen
Professor, Institute of Radio Physics and Electronics,
University of Calcutta
Prof.(Dr.) S.K.Sanyal
Professor, ETCE Deptt, Jadavpur University
Prof. (Dr.) H.Saha Professor, School of VLSI design, IIEST, Shibpur
Prof.(Dr.) C. K.Sarkar
Professor, IC Centre, ETCE Deptt, Jadavpur
University
Prof.(Dr.) J.P.Bandopadhyay Professor, Institute of Radio Physics and Electronics,
University of Calcutta
Dr. Moumita Mukherjee
Scientist, DRDO, CMSDS, Calcutta University
Dr. Sanatan Chottapadhyay
Professor, Institute of Radio Physics and Electronics, University of Calcutta
Prof. (Dr.) D. Roy Chowdhury
Professor, Institute of Radio Physics and Electronics,
University of Calcutta
Prof.(Dr.) Bhaskar Gupta Professor, ETCE Deptt, Jadavpur University
Prof. S.Basu
Professor, KGEC, Kalyani
Prof. D.N.Tibrewala
Professor, Deptt of Biomedical Instrumentation, JU,
Kolkata Prof. Debashis De
Professor, WBUT, Kolkata
Publications by our PG Students: Publication Type Nos
International Journal 8
National Journal 2
International Conference 12
National Conference 22
FEEs STRUCTURE
NARULA INSTITUTE OF TECHNOLOGY ELECTRONICS & COMMUNICATION ENGINEERING
81, Nilgunj Road, Agarpara, Kolkata-700109
Phone:+91 33 2563 8888/7777, Telefax:+91 33 2583 7029
Website:www.nit.ac.in, Email:info @nit.ac.in