PLA Page 1 ECEn 224 PLAs Programmable Logic Arrays.

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PLA Page 1 ECEn 224 PLAs Programmable Logic Arrays

Transcript of PLA Page 1 ECEn 224 PLAs Programmable Logic Arrays.

Page 1: PLA Page 1 ECEn 224 PLAs Programmable Logic Arrays.

PLA Page 1

ECEn 224

PLAs

Programmable Logic Arrays

Page 2: PLA Page 1 ECEn 224 PLAs Programmable Logic Arrays.

PLA Page 2

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PLAs Objectives

• Explain the operation of a PLA

• Use a PLA to implement a logic network

• Given a PLA design, determine the logic functions implemented

Page 3: PLA Page 1 ECEn 224 PLAs Programmable Logic Arrays.

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Programmable Logic Array (PLA)

...

n Input Lines

ANDArray

...

m Outputs Lines

.

.

.OR

Array

k Word Lines

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PLA AND-OR Equivalent

F1 = AB’+ C

F2 = A’C’ + BC

F3 = AB’ + A’C’

F4 = A’C’ + BC + AB’C

ANDArray

ORArray

AB'

C

A'C'

BC

AB'C

CBA

F1

F2

F3

F4

Note: Not every minterm is available

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ProductI nput

(Actual)I nput

(Specified) OutputsTerm A A' B B' C C' A B C F1 F2 F3 F4

AB' 1 0 0 1 0 0 1 0 - 1 0 1 0C 0 0 0 0 1 0 - - 1 1 0 0 0

A'C' 0 1 0 0 0 1 0 - 0 0 1 1 1BC 0 0 1 0 1 0 - 1 1 0 1 0 1

AB'C 1 0 0 1 1 0 1 0 1 0 0 0 1

PLA Table Generation

F1 = AB’+ C

F2 = A’C’ + BC

F3 = AB’ + A’C’

F4 = A’C’ + BC + AB’C

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+ V

+ V + V

+ V

+ V

A B C

A' B' C'

F1

F2

F3

F4

AB'

CA'C'

BC

AB'C

Internal PLA Structure

Outputs

Inputs

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+ V

+ V + V

+ V

+ V

A B C

A' B' C'

F1

F2

F3

F4

AB'

CA'C'

BC

AB'C

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Internal PLA Structure

Outputs

Inputs

The AND plane lines get pulled up to +V

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+ V

+ V + V

+ V

+ V

A B C

A' B' C'

F1

F2

F3

F4

AB'

CA'C'

BC

AB'C

Internal PLA Structure

The AND plane lines stay at +V unless oneof the connected inputs pulls it low.

0

Outputs

Inputs

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+ V

+ V + V

+ V

+ V

A B C

A' B' C'

F1

F2

F3

F4

AB'

CA'C'

BC

AB'C

Internal PLA Structure

The AND plane lines stay at +V unless oneof the connected inputs pulls it low.

1

Outputs

Inputs

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+ V

+ V + V

+ V

+ V

A B C

A' B' C'

F1

F2

F3

F4

AB'

CA'C'

BC

AB'C

Internal PLA Structure

The OR plane lines get pulled down to Ground

Outputs

Inputs

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+ V

+ V + V

+ V

+ V

A B C

A' B' C'

F1

F2

F3

F4

AB'

CA'C'

BC

AB'C

Internal PLA Structure

The OR plane lines get pulled down to Ground

Outputs

Inputs

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+ V

+ V + V

+ V

+ V

A B C

A' B' C'

F1

F2

F3

F4

AB'

CA'C'

BC

AB'C

Internal PLA Structure

The OR plane lines stay at GND unless oneof the AND plane lines pulls it high.

Outputs

Inputs

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+ V

+ V + V

+ V

+ V

A B C

A' B' C'

F1

F2

F3

F4

AB'

CA'C'

BC

AB'C

Internal PLA Structure

The OR plane lines stay at GND unless oneof the AND plane lines pulls it high.

Outputs

Inputs

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+ V

+ V + V

+ V

+ V

A B C

A' B' C'

F1

F2

F3

F4

AB'

CA'C'

BC

AB'C

Internal PLA Structure

The OR plane lines stay at GND unless oneof the AND plane lines pulls it high.

Outputs

Inputs

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+ V

+ V + V

+ V

+ V

A B C

A' B' C'

F1

F2

F3

F4

AB'

CA'C'

BC

AB'C

Internal PLA Structure

The OR plane lines stay at GND unless oneof the AND plane lines pulls it high.

Outputs

Inputs

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Another PLA Representation

Outputs

Inputs

AB'

C

A'C'

BC

AB'C

CBA

F1

F2

F3

F4

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Programmable Logic Array (PLA)

• All inputs and inverted inputs available• Limited number of AND functions

– This is the biggest difference between a ROM and a PLA

• Complete choice of inputs and inverted inputs for each AND function

• OR function for each output• Complete choice of AND functions for

each OR function (output)

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PLA Example

Implement these equations:X = ABC + B’D’ + AB’D + C’D’Y = BC + D’Z = CD + B’D’ + A’BC

in this PLA:CBA D

X Y Z

6 terms or ANDplane lines

8 terms

1 2 3 4

5 6

7 2 8

How can we implement 8 product terms with 6 AND plane lines?

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PLA Example

Implement these equations:X = ABC + B’D’ + AB’D + C’D’Y = BC + D’Z = CD + B’D’ + A’BC

A B X A B Y A B Z

C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10

00 00 00

01 01 01

11 11 11

10 10 10

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PLA Example

Implement these equations:X = ABC + B’D’ + AB’D + C’D’Y = BC + D’Z = CD + B’D’ + A’BC

A B X A B Y A B Z

C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10

00 1 1 1 1 00 00

01 1 01 01

11 1 1 11 11

10 1 1 1 10 10

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PLA Example

Implement these equations:X = ABC + B’D’ + AB’D + C’D’Y = BC + D’Z = CD + B’D’ + A’BC

A B X A B Y A B Z

C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10

00 1 1 1 1 00 1 1 1 1 00

01 1 01 01

11 1 1 11 1 1 11

10 1 1 1 10 1 1 1 1 10

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PLA Example

Implement these equations:X = ABC + B’D’ + AB’D + C’D’Y = BC + D’Z = CD + B’D’ + A’BC

A B X A B Y A B Z

C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10

00 1 1 1 1 00 1 1 1 1 00 1 1

01 1 01 01

11 1 1 11 1 1 11 1 1 1 1

10 1 1 1 10 1 1 1 1 10 1 1 1

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A B X A B Y A B Z

C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10

00 1 1 1 1 00 1 1 1 1 00 1 1

01 1 01 01

11 1 1 11 1 1 11 1 1 1 1

10 1 1 1 10 1 1 1 1 10 1 1 1

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PLA Example

C’D’ is in X and Y and looks useful

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B’D’ is in all three functions

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PLA Example

C’D’ is in X and Y and looks useful

A B X A B Y A B Z

C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10

00 1 1 1 1 00 1 1 1 1 00 1 1

01 1 01 01

11 1 1 11 1 1 11 1 1 1 1

10 1 1 1 10 1 1 1 1 10 1 1 1

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PLA Example

C’D’ is in X and Y and looks useful

B’D’ is in all three functions

A’BC and ABC cover a lot of minterms

A B X A B Y A B Z

C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10

00 1 1 1 1 00 1 1 1 1 00 1 1

01 1 01 01

11 1 1 11 1 1 11 1 1 1 1

10 1 1 1 10 1 1 1 1 10 1 1 1

Page 26: PLA Page 1 ECEn 224 PLAs Programmable Logic Arrays.

B’D’ is in all three functions

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PLA Example

C’D’ is in X and Y and looks useful

The only ones left are AB’ and CD

A’BC and ABC cover a lot of minterms

A B X A B Y A B Z

C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10

00 1 1 1 1 00 1 1 1 1 00 1 1

01 1 01 01

11 1 1 11 1 1 11 1 1 1 1

10 1 1 1 10 1 1 1 1 10 1 1 1

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PLA Example

X = C’D’ + B’D’ + AB’ + ABCY = C’D’ + B’D’ + ABC + A’BCZ = B’D’ + CD + A’BC

A B X A B Y A B Z

C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10

00 1 1 1 1 00 1 1 1 1 00 1 1

01 1 01 01

11 1 1 11 1 1 11 1 1 1 1

10 1 1 1 10 1 1 1 1 10 1 1 1

All of the functions are covered using only 6 product terms

How is this possible?

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PLA Example

X = C’D’ + B’D’ + AB’ + ABCY = C’D’ + B’D’ + ABC + A’BCZ = B’D’ + CD + A’BC

Product I nput OutputTerm A B C D X Y Z

C'D'B'D'AB'ABCA'BCCD

Page 29: PLA Page 1 ECEn 224 PLAs Programmable Logic Arrays.

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PLA Example

X = C’D’ + B’D’ + AB’ + ABCY = C’D’ + B’D’ + ABC + A’BCZ = B’D’ + CD + A’BC

Product I nput OutputTerm A B C D X Y Z

C'D' - - 0 0B'D' - 0 - 0AB' 1 0 - -ABC 1 1 1 -A'BC 0 1 1 -CD - - 1 1

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PLA Example

X = C’D’ + B’D’ + AB’ + ABCY = C’D’ + B’D’ + ABC + A’BCZ = B’D’ + CD + A’BC

Product I nput OutputTerm A B C D X Y Z

C'D' - - 0 0 1 1 0B'D' - 0 - 0 1 1 1AB' 1 0 - - 1 0 0ABC 1 1 1 - 1 1 0A'BC 0 1 1 - 0 1 1CD - - 1 1 0 0 1

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PLA ExampleX = C’D’ + B’D’ + AB’ + ABC

Y = C’D’ + B’D’ + ABC + A’BC

Z = B’D’ + CD + A’BC

Product I nput OutputTerm A B C D X Y Z

C'D' - - 0 0 1 1 0B'D' - 0 - 0 1 1 1AB' 1 0 - - 1 0 0ABC 1 1 1 - 1 1 0A'BC 0 1 1 - 0 1 1CD - - 1 1 0 0 1

CBA D

X Y Z

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Summary

• Explain the operation of a ROM

• Use a ROM to implement a logic network

• Explain the operation of a PLA

• Use a PLA to implement a logic network

• Given a PLA design, determine the logic functions implemented