-PIPELINE ADC-

-Presented byPrashant Chaudhari

-Guided by Prof.G.R.Phulay

Contents-

• Introduction• Literature Reviews• System Development• Performance Analysis• Conclusions

Introduction• Need of the system

• A single ADC model to meet requirements for multiple applications• Implementation in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability

• Objective• Provide a background on pipeline adcs• Introduce a novel front-end capshare technique that saves power in the front-end S/H• Show the theoretically power savings of the technique through a design comparison

LITERATURE REVIEWSBasic types of ADCs•Flash type of ADC

•Successive approximation (SAR) type ADC

•Sigma- Delta convertor

ARCHITECTURE LATENCY SPEED ACCURACY AREA

Flash No High Low High

Delta-Sigma Yes Low High Medium

Successive Approximation (SAR) Yes Low Medium-High Low

Pipeline Yes Medium Medium-High Medium

ONE-STAGE PIPELINE

Basic structure of 1 stage pipeline ADC

System Developments

PIPELINE ADC BUILDING BLOCKS

AND DESIGN METHODOLOGY

• Opamp design

• Building blocks

• Design procedure

• Capacitor-sharing pipeline

OPAMP design

Gain:

Bandwidth:

Output voltage swing

BUILDING BLOCKS1) Sub-ADC:

2) SampleAnd Hold:

Performance analysisREGULAR VERSUS CAPSHARE ADC

1) Regular pipeline ADC with a flip-around MDAC in the first stage:

2) Pipeline ADC with capacitor-sharing front-end:

POWER COMPARISON And ANALYSIS

SNDR and SNR at fin = 61/128 ・ fSSim Pipeline Type fS

Thermal Noise SNDR[dB] SNR[dB] ENOB[bits]

1 Regular 2 No 62.1 62.5 10

2 Capshare 2 No 60.9 61.4 9.82

3 Regular 2 Yes 59.0 59.4 9.51

4 Capshare 2 Yes 59.2 59.3 9.54

5 Regular 20 No 52.2 61.4 8.37

6 Capshare 20 No 54.1 62.6 8.70

7 Regular 20 Yes 51.2 58.2 8.21

Experimental results of capshare ADC measured at different fin and fS

.Measure-

ment

Fs

[MHz]

Fin [MHz] SNDR [dB] SNR [dB] ENOB [bits] Panalog [mW] Pdigital [μW] FOM

[pJ/step]

1 0.4 0.19 53.9 54.2 8.67 4.06 8.64 26.2

2 5 2.38 53.8 54.3 8.65 4.21 106 2.25

3 10 4.77 53.8 54.4 8.65 4.25 212 1.17

4 14 6.67 53.1 53.7 8.52 4.28 297 0.93

5 20 2.03 53.0 53.9 8.51 4.26 422 3.15

6 20 4.84 53.1 54.4 8.53 4.28 422 1.32

7 20 9.53 53.0 54.1 8.51 4.30 423 0.68

8 20 12.0 51.4 53.5 8.25 4.32 421 0.65

9 20 13.6 51.0 52.6 8.18 4.31 423 0.60

10 24 11.4 51.9 53.6 8.33 4.34 507 0.66

CONCLUSIONS

• A novel front-end capacitor-sharing technique

that significantly reduces the power consumption in

the front-end S/H

• A comparison was conducted between a cap-share

pipeline ADC and a regular pipeline ADC

•The front-end capshare stage caused the dynamic

range to drop below the thermal noise level

THANK YOU…