Pilsung Taegyun AB A - kn-OWL-edge EWSD (Electronic Wahler System Digital), NEAX-61E ... • This...

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Fathur AB

Anin A

Afif A

Hari A

Gary A

Dhika AB

April AB

Mulya AB

Rizka B

Dion AB

Siska AB

Mirel AB

Hani AB

Airita AB

Yusuf AB

Pilsung AB

Taegyun A


Digital Switch

Course Number : TTH2A3

CLO : 3

Week : 9


Inside the Digital Local Exchange

MD

F M

DF

Subscriber Concentrator Unit Subscriber Concentrator Unit Group Switch Unit Group Switch Unit

subscriber line termination unit

subscriber line termination unit

MU

X

MU

X

digital line termination unit (DLTU)

digital line termination unit (DLTU)

subscriber concentrator switch block

subscriber concentrator switch block

exchange control system exchange control system

analog trunk termination unit

analog trunk termination unit

DD

F D

DF

group switch block

group switch block

CAS CAS

CCS CCS

DLTU DLTU

DLTU DLTU

DLTU DLTU

DLTU DLTU

analog trunk

digital trunk

switch block control





Exchange Control System

• Consists of CPU and Memory, to control relay switch

• CPU could be:

– Distributed Control • Vertical Decomposition

• Horizontal Decomposition

– Centralized Control • Standby Mode

• Synchronous Duplex Mode

• Load Sharing Mode


Digital Switch

Cascading Switch

and

Blocking Probability


Cascading Switch

Requirements:

• Digital Traffic, where information from user has a dedicated slot and frame

• Switching, exchange the content between one time slot to another

Examples: EWSD (Electronic Wahler System Digital), NEAX-61E (Nipon Electronic Automatic Exchange), 5-ESS (Electronic Switching System)

IST (International Switching and Transmission) standard:

• Number of frame in a SN (Switching Network)

• Number of time slot in a frame = 32 (PCM 30)

.....

.....

.....

....

....

highway 1

highway 2

highway n

TS 0 TS 1 TS k

Frame

OUTPUTINPUT


Digital Switch – Time Switch

TA

TB

TB

TA

TA(n)

TA(n+1)

TB(n)

TB(n+1)

A

B

TA (n+1) = TB (n)

TB (n+1) = TA (n)

time switchingTA

TB

TB

TA

A

B

For comparison: Analog Switch – Space Switch


Time Switch

• Exchange TS in the same frame

Space Switch

• Exchange same-number TS but in different frame

Time Switch and Space Switch

TATB

A

B

TB TA

A

B

FA

FB

FA

FB

• In small SN (<32) we use single stage time switch (T) or space switch (S) • In large SN (>32) we use multistage Switching, for example:

• 3 stages STS or TST • 5 stage STSTS or TSTST

• Larger SN = more stages = faster switching rate


Space Switch

• Address = timeslot: Address 1 = TS 1 Address 2 = TS 2 • Word length = S cross point in 1 column + 1 Word Length = n + 1 = bit • How it works?

– CM contain address for selected cross point – Switching Control reads each CM based on

address sequence – While TS 1 is closed, address in 1st CM

determines which cross point is ON – Process next CM, if last CM found, go back

to 1st CM

1

2

3

w

1

2

3

w

1

2

3

w

1

2

3

w

1 2 3 N

1

2

3

N

Inlet Bus

Outlet Bus

crosspoint

address bus

connection

memories

address=ts/frame

......

......

. . . . . .

.

.

.

1nlog 2


Space Switch Explained

& & &

&&&

&&&

A 4 A 3 A 2 A 1

B 4 B 3 B 2 B 1

C 4 C 3 C 2 C 1

A 4

A 3 A 2

A 1

B 4

B 3

B 2 B 1

C 4

C 3

C 2

C 1

3

1

2

3

1

3

3

1

2

2

1

2

connection memory 1connection memory

2

connection memory

3

8 bit PCM word

3

2

1

t4 t3 t2 t 1

Periode s

8 bit PCM word

t4 t3 t2 t1

Periode s

Control Address

(number of incoming highway)


Time Switch

• Space (highway) unchanged

• Timeslot change create delay

(TS 3)

(TS 3)

(TS 8)

(TS 8)

AT

BT

AR

BR

5 TS D

elay

(32-8) + 3 = 27 TS delay

(TS 3)

(TS 8)5

(TS 8)

(TS 3)27

PCM Frame


Time Switch

Speech Memory (SM) : stores content of TS

Connection Memory (CM) : controls read sequence from SM

Counter : control write sequence into SM

Cell

content

Cell

address

D 1

C 2

B 3

A 4

A B C D

Frame

D C A B

4ts : 3 2 14ts : 3 2 1

Counter

1 - 4

3

4

2

1

(TS1)

(TS2)

(TS3)

(TS4)

acycliccyclic

Speech Memory

write

time

slot

rea

d

write

rea

d

write

rea

d

write

rea

d

Frame

write

address

read

address


Time Switch Explained

t4 t3 t2 t1

Speech

Memori 1

A 4 A 3 A 2 A 1

A 1

Speech

Memori 2

A 2

Speech

Memori 3

A 3

Speech

Memori 4

A 4

t 4 t 2t 3 t 1

Periode s

timeslot outgoing

A 4 A 3A 2 A 1

3

1

4

2

Control Address

(location of Speech Memory)

control memory

Periode s

timeslot incoming

Cyclic Writing Acyclic Reading

Highway outgoingHighway incoming

8 bit PCM world 8 bit PCM world

t 1

t 2

t 3

t 4 t 3

t 1

t 4

t 2

t 1

t 2

t 3

t 4

Speech Memory


Matrix Switch

• Basic element of matrix switch is the switch

• N x M switch is a switch with N input and M output

• Single stage matrix switch is the most simple switch but with several drawbacks:

o Inefficient cross point usage (number of cross points is very large)

o Capacitive load is big

o Each cross point dedicated for specific connection, a failure on that cross point means no connection can be made available

• To overcome this weaknesses, we use multi stage switching network

2

)1(

NN

XN

1

2345

a. Triangular Matrix

12345

b. Square Matrix

1

2

3

N

1 2 3 N

c. Full interconnection crosspoint

NxNX

N

)1( NNX

N


Multi Stage Switch

• Multi stage switch has blocking probability due to the shared cross points

• To provide lower blocking probability, numbers of matrix in center stage play significant role:

• Replacing k in (1):

n.k

n.k

n.k

N/n .N/n

N/n .N/n

N/n .N/n

k.n

k.n

k.n

N/n

array k arrayN/n

array

N inlet N outlet

knn

N

n

N

n

Nkkn

n

N

XN

2

2

n

NkNkXN

(1)

NX = total number of cross points

N = number of inlet/outlet

n = size of every switch block inlet/outlet

k = number of center stage

)12(4 NNNx

.)(min121)1()1(

12

nnnk

nk

2

)12()12(2

n

NnnNN X

(2)

0dn

dN X

2/1

2

N

n (3)

(2) (3)

Number of minimum cross point :


Cross Point Calculation Example

A Switching Network has inlet and outlet group of 100 lines, number of inlet and outlet of 1000, with 10 matrix for center stage

Calculate the number of matrix in single stage and in 3 stages

From above information, we have:

• n = 100

• N = 1000

• k = 10

N(N - 1)/2 N(N-1)

1

N

1

N

1

N

1

N

Triangular Matrix Square Matrix

N X N

1

N

1

N

Full Connection Matrix

Nx = N x N Nx = N(N-1)/2 Nx = N(N-1)

= 103 x 103 = 103(103-1)/2 = 103(103-1)

= 106 cp = 499,5 x 103 cp = 949 x 103 cp

10 x 10

10 x 10

100 x 10

1

100

100 x 10

1

100

100 x 10

1

100

10 x 100

1

100

10 x 100

1

100

10 x 100

1

100

1

10

= (2 x 103 x 10)+ 10 (103/102) 2

= 21 x 103 cp

2

2

n

NkNkXN


See you on next class


Time Switch

• Exchange TS in the same frame

Space Switch

• Exchange same-number TS but in different frame

Time Switch and Space Switch

TATB

A

B

TB TA

A

B

FA

FB

FA

FB

• In small SN (<32) we use single stage time switch (T) or space switch (S) • In large SN (>32) we use multistage Switching, for example:

• 3 stages STS or TST • 5 stage STSTS or TSTST

• Larger SN = more stages = faster switching rate


Digital Switch Properties

• Single stage space switch has blocking probability • Single stage (fast) time switch has blocking

probability • There is a possibility to create time switch with non-

blocking interconnectivity but with large capacity (memory and channel)

• To provide low blocking probability switch, we can combine time switch and space switch


Time Switch – Space Switch (T-S)

Switch Block of T-S

• Left figure explains interconnection from A2/ts 10 to B1/ts 45

• In T-S block Time Switch acts as the input for every Space Switch line

• Time Switch switches an incoming time slot to an outgoing time slot

• Space Switch switches an incoming bus to an outgoing bus

• This structure still has a blocking probability, due to the space switch

SM-A1

CM-A1

SM-A2

CM-A2

SM-A3

CM-A3

A1

A2

A3

10

1

2

3

CM-B3CM-B2

CM-B1

01045

10

10

45

45

45

B1

B2

B3


Space Switch - Time Switch (S-T)

Switch Block of S-T

• Left figure explains interconnection from A2/ts 10 to B1/ts 45

• This S-T switch block has the same characteristics with T-S, only differ the placement of Time Switch at the output bus

SM-B1

CM-B1

SM-B2

CM-B2

SM-B3

CM-B3

B1

B2

B3

45

CM-A3

CM-A2

CM-A1 00110

10

10

10

45

1

2

3

10

A1

A2

A3


Time Switch – Space Switch (T-S) Explained

A 4 A 3 A 2 A 1

8 bit PCM world

B 4 B 3 B 2 B 1

C 4 C3 C 2 C 1

D 4 D 3 D 2 D1

1A1

2B1

3C1

4D1

5

6

7

8

A 2

B 2

C 2

D 2

9

10

11

12

A 3

B 3

C 3

D 3

A 4 13

B4 14

C4 15

D4 16

Demultiplexer

12

16

13

8

3

1

6

15

7

4

9

11

5

10

14

2

t1t2t3t4

t5t6t7t8

t9t10

t11

t12

t14

t13

t16

t15

A 4 D 4 D 3D 2

A 1B 2C 4 C 1

A 3C3 C 2D1

A 2B 4 B 3B 1

Outgoinghigjways

(n bit/s)

Arbitiarycontroled

read-outData memory

(content/memory location)cyclic

write in

8 bit PCM world

4 n bit/s

8 bit PCM world

4 n bit/s

Multiplexer

Periode s Periode s

Control memory

Control address(no of data memory)

Periode s Periode s

Incominghigjways

(n bit/s)

t1

t2

t3

t4

t5

t6

t7

t8

t9

t10

t11

t12

t13

t14

t15

t16

t1

t2

t3

t4

t5

t6

t7

t8

t9

t10

t11

t12

t13

t14

t15

t16


S-T-S

Above figure explains interconnection from A1/TS10 to C1/TS45

SM-B1

CM-B1

SM-B2

CM-B2

SM-B3

CM-B3

B 1

B 2

B 3

45

CM-A1

CM-A2CM-A101110

10

1

2

3

10

A 1

A 2

A 3

1

2

3

CM-C3CM-C2

CM-C1

01145

45

C 1

C 2

C 3

10

B 1

B 2

10

45

B 3


T-S-T

Above figure explains interconnection from A2/TS10 to C1/TS45.

SM-

A1

CM-

A1SM-

A2

CM-

A2SM-

A3

CM-

A3

SM-

C1

CM-

C1

SM-

C2

CM-

C2

SM-

C3

CM-

C3

A

1

A

2

A

3

C 1

C 2

C 3

45

10

CM-

B3

CM-

B2

CM-

B1

010124

1010

124

124

124

124

45

45

1

2

3


Comparison

• Single stage Space (S) switch is inapplicable due to its high blocking probability

• Single stage Time (T) switch may be used as non-blocking switch block with low capacity (250 lines)

• T-S or S-T configuration may be used in small to medium capacity, due to its blocking probability increases with the Time Switch size

• The size of Space Switch increases in square function with the number of input/output bus, while the size of time switch increases in linear with the increment of time slot number

• For exchanges with large capacity, we may use from SSTSS, TSST, to TSSST configuration


See you on next class

Pilsung Taegyun AB A - kn-OWL-edge EWSD (Electronic Wahler System Digital), NEAX-61E ... • This...

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