Pico Blaze Intro

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Introducción al Picoblaze


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Por que un micro empotrado yno una FSM maquina de estados?

Micropocessor (a “Programmable FSM”)Sequential execution

SlowerBetter for complexflow diagramBetter for Large FSMEasier to make

changes in algorithm

“Regular” FSMParallel executionFaster

Better for simpleflow diagram (butcan be used for

everything)More difficult tomake changes in

algorithm


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Introducción. Múltiplesaplicaciones

There are literally dozens of 8-bit microcontrollerarchitectures and instruction sets. Modern FPGAs canefficiently implement practically any 8-bit microcontroller,and available FPGA soft cores support popular instructionsets such as the PIC, 8051, AVR, 6502, 8080, and Z80microcontrollers .


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The Xilinx PicoBlaze microcontroller is specificallydesigned and optimized for the Virtex and Spartanseries of FPGAs.


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The PicoBlaze solution consumes considerably lessresources than comparable 8-bit microcontrollerarchitectures.


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La solución paraprocesamiento sencillo

PicoBlaze is a compact, capable, and cost-effectivefully embedded 8-bit RISC microcontroller coreoptimized for the Spartan™-3, Virtex™-II, Virtex-II

Pro™ and Virtex-4 FPGAs and CoolRunner™-IICPLDs.


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La solución paraprocesamiento sencillo: te DA

Free PicoBlaze Macro — The PicoBlazemicrocontroller is delivered as synthesizable VHDLsource code. As a result, the core is future-proof

and can be migrated to future FPGA and CPLDarchitectures.


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Ensamblador Facil de usar — The PicoBlazeassembler is provided as a simple DOS executable.The assembler will compile your program in less

than 3 seconds and generate VHDL, Verilog and anM-file (for Xilinx System Generator) for defining theprogram within a block memory. Otherdevelopment tools include a graphical integrateddevelopment environment (IDE), a graphicalinstruction set simulator (ISS) and VHDL sourcecode and simulation models.


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Alto rendimiento — PicoBlaze delivers 44 to 100million instructions per second (MIPS) dependingon the target FPGA family and speed grade – many

times faster than commercially availablemicrocontroller devices..


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La solución para

procesamiento sencillo

Tamaño Lógico Minimo — PicoBlaze occupies192 logic cells, which represents just 5% of aSpartan-3 XC3S200 device. Because the core only

consumes a small fraction of the FPGA and CPLDresources, many engineers can use multiplePicoBlaze devices for tackling larger tasks or simply

keeping tasks isolated and predictable..


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La solución para

procesamiento sencillo

Empotrable al 100%— The PicoBlazemicrocontroller core is totally embedded within thetarget FPGA or CPLD and requires no external

resources. Its basic functionality is easily extendedand enhanced by connecting additional logic to themicrocontroller’s input and output ports..


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CaracterísticasEs un 8-bit fully embedded microcontrollerTiene 16 8-bit general purpose registers,Tiene 8-bit ALU with the carry and zero flags64-byte data memory, scratch RAM

10-bit instruction address, which supports aprogram up to 1024 instructions256 input ports and 256 output ports,

Automatic 31-location CALL/RETURNstack


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Características (Cont.)Predictable performance, always two clockcycles per instruction, up to 200 MHz or 100MIPS in a Virtex-4™ FPGA and 88 MHz or 44MIPS in a Spartan-3 FPGA

It also has facility for reset and interruptInstruction size is 16-bitsIt also has facility for reset and interrupt

Fast interrupt response; worst-case 5 clockcycles


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Constant(k) Coded machineKCPSM3 es en muchas formas una maquina basada enconstantesConstant values are specified for use in the following aspects ofa program:

Constant data value for use in an ALU operationConstant port address to access a specific piece of information orcontrol logic external to the PicoBlaze moduleConstant address values for controlling the execution sequence ofthe program

Constant Cycles All instructions under all conditions execute over two clock cycles.

Constant Program LengthThe program length is 256 instructions


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Estructura

3 parts:

• ALU• Reg file

• Controlunit


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Estructura. DetallesRegisters

16 8-bit registers labelled from s0 to sF ALU

Takes two operands of 8-bits and returns theresult to the first register

Add, Subtract with and without a carry aresupportedLOAD, AND, OR and XOR

Flow ControlZero and Carry flags are set by the ALU operationsCALL/RETURN used for subroutine facilities


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Estructura. Detalles (cont.)

ResetProcessor goes back to initial stateStarts executing from address 00Everything except the registers is reinitialized

Input/OutputDuring an input the value on the indicated port istransferred to one of the registersDuring an output the value from one of theregisters is written on an output port

Interrupt A single interrupt is allowed


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Porque uso un Microcontroladordentro de una FPGA?

Aplicaciones de control y maquinas de

estado son mas difícil de programarRecursos lógicos crece con el

incremento de la complejidad

Ejecución secuencial

El rendimiento se degrada con el incrementode la complejidadLos requerimientos de memoria incrementa

con la complejidadRespuesta lenta a estímulos simultáneos

Debilidades

Significativamente mucho masrendimientoExcelente para operaciones en

paraleloSecuential vs. parallelo La

implementación secuencial frente aparalela sacrifica rendimiento optimo ocosteRespuesta rápida a entradas

simultaneas

Fácil para programar aplicaciones de control ymaquinas de estadosLos requerimientos de recursos se mantienen

constante dentro aún cuando incrementa lacomplejidadRe-uses recursos lógicos, excelente para

funciones de baja rendimiento

Fortalezas

FPGA LogicPicoBlaze Microcontroller


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Usando el Microcontrolador

PicoBlaze en una FPGA Flujo de diseño en VHDL

El componente (macro o módulo ) es suministrado en VHDL(KCPSM3.vhd) y su declaración es la siguiente

component KCPSM3port (

address : out std_logic_vector( 9 downto 0);instruction : in std_logic_vector(17 downto 0);port_id : out std_logic_vector( 7 downto 0);write_strobe : out std_logic;out_port : out std_logic_vector( 7 downto 0);read_strobe : out std_logic;in_port : in std_logic_vector( 7 downto 0);interrupt : in std_logic;interrupt_ack : out std_logic;reset : in std_logic;clk : in std_logic );

end component ;);


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El componente (macro ) es suministrado en VHDL(KCPSM3.vhd) y su instanciación en un diseño es la siguiente

processor: kcpsm3port map (address => address_signal,instruction => instruction_signal,port_id => port_id_signal,write_strobe => write_strobe_signal,out_port => out_port_signal,read_strobe => read_strobe_signal,in_port => in_port_signal,interrupt => interrupt_signal,interrupt_ack => interrupt_ack_signal,reset => reset_signal,clk => clk_signal );


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La memoria de programa (ROM). ThePicoBlaze program ROM is used within a

VHDL design flow.The PicoBlaze assembler generates a VHDLfile in which a block RAM and its initialcontents are defined. This VHDL file can be

used for both logic synthesis andsimulation of the processor


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PicoBlaze en una FPGA

Flujo de diseño en VHDLDeclaración del componente (ROM).component prog_romport ( address : in std_logic_vector( 9 downto 0);

instruction : out std_logic_vector(17 downto 0);clk : in std_logic);end component ;

El nombre del componente deriva de nombre del

fichero con el programa en ensamblador. Por ejemplosi tu programa se llama reloj.psm la memoria(componente) en vhdl se llama reloj.vhd . Esteproceso resulta de aplicar el compilador suministrado


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Diagrama de bloques del Micro +

ROM. Poniendo todo junto

signal instruction : std_logic_vector(17 downto 0);

signal address : std_logic_vector(9 downto 0);


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PicoBlaze Herramientas de

desarrollo Existen 3 herramientas de desarrollo

Xilinx KCPSM3Mediatronix pBlazIDE

Xilinx System Generator


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desarrollo

SiSiN/A Memory Viewer

SiSiN/A Register Viewer

SiSiN/A SimulatorBreakpoints

Grafico/InteractivoGrafico/Interactivo VHDLInstruction Set Simulator

KCPSM3PBlazIDEKCPSM3Sintaxisinstruciones

Linea de comandodentro de

System Generator

GraficoLínea de comando enDos Wiindow

Ensamblador

Windows 2000 y XPWindows 98, 2000,NT, ME, XP

WindowsPlataforma

Xilinx System

Generator

Mediatronix

pBlazIDE

Xilinx KCPSM3


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desarrollo Xilinx KCPSM3

The KCPSM3 Assembler is provided as a simple DOSexecutable file together with three template files.Importante Crear un directorio de trabajo. Copy all thefiles KCPSM3.EXE, ROM_form.vhd, ROM_form.v, and ROM_form.coe dentro del directorio de trabajo.Los programas pueden ser escritos con el wordpad .Salvar con extensión psm

Abre un cmd DOS.kcpsm3 [.psm]

El ensamblador da salida de errores por pantalla (peor muyrápida) usar un fichero de salida para depurar errores:kcpsm3 [.psm] > screen_dump.txt


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desarrollo Compilación. Ficheros de entrada y salida.

l d l ll


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Ejemplo de una Plantilla

de un programa ( KCPSM3 )

NAMEREG sX, ; Rename register sX with CONSTANT , 00 ; Define constant , assign value

; ROM output file es siempre llamado ; .vhd

ADDRESS 000 ; Programs always start at reset vector 0 ENABLE INTERRUPT ; If using interrupts, be sure to enable

; the INTERRUPT input BEGIN:

; > JUMP BEGIN ; Embedded applications never end

ISR: ; An Interrupt Service Routine (ISR) is ; required if using interrupts ; Interrupts are automatically disabled ; when an interrupt is recognized ; Never re-enable interrupts during the ISR

RETURNI ENABLE ; Return from interrupt service routine ; Use RETURNI DISABLE to leave interrupts ; disabled

ADDRESS 3FF ; Interrupt vector is located at highest ; instruction address

JUMP ISR ; Jump to interrupt service routine, IS

Ej l d Pl ill d


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Ejemplo de una Plantilla de

un programa ( pBlazIDE ) EQU sX ; Rename register sX with EQU $00 ; Define constant , assign value

; name ROM output file generated by pBlazIDE assembler VHDL “template.vhd”, “target.vhd”, “entity_name” DSIN ; Create input port, assign port address DSOUT ; Create output port, assign port address DSIO ; Create readable output port,

; assign port address ORG 0 ; Programs always start at reset vector 0

EINT ; If using interrupts, be sure to enable the INTERRUPT input

BEGIN: ; >

JUMP BEGIN ; Embedded applications never end ISR: ; An Interrupt Service Routine (ISR) is

; required if using interrupts ; Interrupts are automatically disabled ; when an interrupt is recognized ; Never re-enable interrupts during the ISR RETI ENABLE ; Return from interrupt service routine

; Use RETURNI DISABLE to leave interrupts ; disabled

ORG $3FF ; Interrupt vector is located at highest ; instruction address JUMP ISR ; Jump to interrupt service routine, ISR


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Conjunto de instruccionesProgram Control Group (jump, call y return)

Jump Instruction – Both conditional andunconditional


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Conjunto de instruccionesProgram Control Group (jump, call y return)

Return Instruction


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Logical Group (contd.)OR

XOR


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Grupo aritmético ADD – without carry

ADDC - with carry


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Arithmetic Group (contd.)SUB – without carry

SUBC – with carry


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Shift and Rotate GroupShift right

Shift left


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Shift right


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Shift left


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Input and Output GroupInput

Output


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Individual ModulesOperand Select

Arithmetic GroupLogic GroupShift and Rotate Group

ALU Multiplexer ALU Control

Program CounterStack Counter


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I di id l M d l


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Individual Modules

CPU I t f


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CPU Interface

CPU I t f


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CPU Interface

Picoblaze no tiene Periféricos integradosestos se construyen si se necesitan …Se usan las instrucciones input y

ouput para comunicase con ellos

CPU I t f


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CPU Interface

S


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System Architecture

PicoBlaze

Port ID

In port

Out port

Read Strobe

Write StrobeInterrupt

Instruction

Memory

Device

Address

Instruction

Reset

Clock

Data


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Data

MovementInstruction


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Port Input


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Port Input


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Lectura de un puerto. Formas de


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ondas

Port Output


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Port Output

Clock of output Device is the same as CPU clock


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Write Enable

D Q

QEN


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Example

Port Write Waveform


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Editing PSM file


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Compiling


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Verifying Compilation


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Verifying Compilation


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Identifying an error


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Verifying Everything is OK


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Copy generated verilog file


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Pico Blaze Intro

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