PIC16F877A Intro

Overview Laboratory Introduction

— Learning the architecture of the PIC16F877

— Learning the instruction set of the PIC16F877

� 35 instructions

� same as previous PIC versions (eg 16F74)

— Evaluation of example code

— Experimentation with lab software (today)

— Experimentation with lab hardware (Wednesday)

1

Details of the Architecture PIC 16F877

— 14 bit instructions

— 8 bit data values, byte addressed

— Harvard architecture (separate address/data

memory)

— Storage capacity:

� 8k x 14 Flash EPROM (program storage)

� 256x8 EEPROM

� 368x8 SRAM (data storage)

— Universal Asynch./Synch. Receiver/Transmitter

(UART)

— 8 channel, 1-bit A/D converter.

2 January 24, 2002

16F877 Data Path

PIC16F87X

DS30292B-page 6 1999 Microchip Technology Inc.

FIGURE 1-2: PIC16F874 AND PIC16F877 BLOCK DIAGRAM

FLASH

ProgramMemory

13 Data Bus 8

14ProgramBus

Instruction reg

Program Counter

8 Level Stack(13-bit)

RAMFile

Registers

Direct Addr 7

RAM Addr (1) 9

Addr MUX

IndirectAddr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

InstructionDecode &

Control

TimingGeneration

OSC1/CLKINOSC2/CLKOUT

MCLR VDD, VSS

PORTA

PORTB

PORTC

PORTD

PORTE

RA4/T0CKIRA5/AN4/SS

RC0/T1OSO/T1CKIRC1/T1OSI/CCP2RC2/CCP1RC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX/CKRC7/RX/DT

RD7/PSP7:RD0/PSP0

RE0/AN5/RD

RE1/AN6/WR

RE2/AN7/CS

8

8

Brown-outReset

Note 1: Higher order bits are from the STATUS register.

USARTCCP1,2Synchronous

10-bit A/DTimer0 Timer1 Timer2

Serial Port

RA3/AN3/VREF+RA2/AN2/VREF-RA1/AN1RA0/AN0

Parallel Slave Port

8

3

Data EEPROM

RB0/INTRB1RB2RB3/PGMRB4RB5RB6/PGCRB7/PGD

Device Program FLASH

Data Memory Data EEPROM

PIC16F874 4K 192 Bytes 128 Bytes

PIC16F877 8K 368 Bytes 256 Bytes

In-CircuitDebugger

Low-VoltageProgramming

3 Page 6 - 16F877 data sheet

16F877 Program Memory Map

Figure 2-1 of 16F877 data sheet.

— Location 0 is first instruction executed

(go to Start).

— Interrupt vector aids with spurious actions.

— Eight-deep program stack.

4 Peatman - Chapter 2

16F877 Data Memory and Register Files

1999 Microchip Technology Inc. DS30292B-page 13

PIC16F87X

FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP

Indirect addr.(*)

TMR0PCL

STATUSFSR

PORTAPORTBPORTC

PCLATHINTCON

PIR1

TMR1LTMR1HT1CONTMR2

T2CONSSPBUFSSPCONCCPR1LCCPR1H

CCP1CON

OPTION_REGPCL

STATUSFSR

TRISATRISBTRISC

PCLATHINTCON

PIE1

PCON

PR2SSPADDSSPSTAT

00h01h02h03h04h05h06h07h08h09h0Ah0Bh0Ch0Dh0Eh0Fh10h11h12h13h14h15h16h17h18h19h1Ah1Bh1Ch1Dh1Eh1Fh


20h A0h

7Fh FFhBank 0 Bank 1

Unimplemented data memory locations, read as ’0’. * Not a physical register.

Note 1: These registers are not implemented on 28-pin devices.2: These registers are reserved, maintain these registers clear.

FileAddress

Indirect addr.(*) Indirect addr.(*)

PCLSTATUS

FSR

PCLATHINTCON

PCLSTATUS

FSR

PCLATHINTCON



120h 1A0h

17Fh 1FFhBank 2 Bank 3

Indirect addr.(*)

PORTDPORTE

TRISD

ADRESL

TRISE

TMR0 OPTION_REG

PIR2 PIE2

RCSTATXREGRCREGCCPR2LCCPR2H

CCP2CONADRESHADCON0

TXSTASPBRG

ADCON1

GeneralPurposeRegister




1EFh1F0haccesses

70h - 7Fh

EFhF0haccesses

70h-7Fh

16Fh170haccesses

70h-7Fh



TRISBPORTB

96 Bytes80 Bytes 80 Bytes 80 Bytes

16 Bytes 16 Bytes

(1)

(1)

(1)

(1)

SSPCON2

EEDATAEEADR

EECON1EECON2

EEDATHEEADRH

Reserved(2)

Reserved(2)

5 16F877 data sheet - page 13

16F877 Status Register

PIC16F87X


2.2.2.1 STATUS REGISTER

The STATUS register contains the arithmetic status ofthe ALU, the RESET status and the bank select bits fordata memory.

The STATUS register can be the destination for anyinstruction, as with any other register. If the STATUSregister is the destination for an instruction that affectsthe Z, DC or C bits, then the write to these three bits isdisabled. These bits are set or cleared according to thedevice logic. Furthermore, the TO and PD bits are notwritable, therefore, the result of an instruction with theSTATUS register as destination may be different thanintended.

For example, CLRF STATUS will clear the upper-threebits and set the Z bit. This leaves the STATUS registeras 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,SWAPF and MOVWF instructions are used to alter theSTATUS register, because these instructions do notaffect the Z, C or DC bits from the STATUS register. Forother instructions not affecting any status bits, see the"Instruction Set Summary."

REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

Note 1: The C and DC bits operate as a borrowand digit borrow bit, respectively, in sub-traction. See the SUBLW and SUBWFinstructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bitW = Writable bitU = Unimplemented bit,

read as ‘0’- n= Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh)00 = Bank 0 (00h - 7Fh)Each bank is 128 bytes

bit 4: TO: Time-out bit1 = After power-up, CLRWDT instruction, or SLEEP instruction0 = A WDT time-out occurred

bit 3: PD: Power-down bit1 = After power-up or by the CLRWDT instruction0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit1 = The result of an arithmetic or logic operation is zero0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)1 = A carry-out from the 4th low order bit of the result occurred0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)1 = A carry-out from the most significant bit of the result occurred0 = No carry-out from the most significant bit of the result occurredNote: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement ofthe second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low orderbit of the source register.


16F877 Instruction Set

See Table 13-1 of the 16F877 data sheet.

See Figure 13-1 of the 16F877 data sheet.

3 types of instructions:

— Byte-oriented operations

— Bit-oriented operations

— Literal and control operations



PIC16F87X


TABLE 13-2: PIC16CXXX INSTRUCTION SET Mnemonic,Operands

Description Cycles 14-Bit Opcode StatusAffected

Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWFANDWFCLRFCLRWCOMFDECFDECFSZINCFINCFSZIORWFMOVFMOVWFNOPRLFRRFSUBWFSWAPFXORWF

f, df, df-f, df, df, df, df, df, df, df-f, df, df, df, df, d

Add W and fAND W with fClear fClear WComplement fDecrement fDecrement f, Skip if 0Increment fIncrement f, Skip if 0Inclusive OR W with fMove fMove W to fNo OperationRotate Left f through CarryRotate Right f through CarrySubtract W from fSwap nibbles in fExclusive OR W with f

111111

1(2)1

1(2)111111111

000000000000000000000000000000000000

011101010001000110010011101110101111010010000000000011011100001011100110

dfffdffflfff0xxxdfffdfffdfffdfffdfffdfffdffflfff0xx0dfffdfffdfffdfffdfff

ffffffffffffxxxxffffffffffffffffffffffffffffffff0000ffffffffffffffffffff

C,DC,ZZZZZZ

Z

ZZ

CC

C,DC,Z

Z

1,21,22

1,21,2

1,2,31,2

1,2,31,21,2

1,21,21,21,21,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCFBSFBTFSCBTFSS

f, bf, bf, bf, b

Bit Clear fBit Set fBit Test f, Skip if ClearBit Test f, Skip if Set

11

1 (2)1 (2)

01010101

00bb01bb10bb11bb

bfffbfffbfffbfff

ffffffffffffffff

1,21,233

LITERAL AND CONTROL OPERATIONS

ADDLWANDLWCALLCLRWDTGOTOIORLWMOVLWRETFIERETLWRETURNSLEEPSUBLWXORLW

kkk-kkk-k--kk

Add literal and WAND literal with WCall subroutineClear Watchdog TimerGo to addressInclusive OR literal with WMove literal to WReturn from interruptReturn with literal in W Return from SubroutineGo into standby modeSubtract W from literalExclusive OR literal with W

1121211222111

11111000101111001100001111

111x10010kkk00001kkk100000xx000001xx00000000110x1010

kkkkkkkkkkkk0110kkkkkkkkkkkk0000kkkk00000110kkkkkkkk

kkkkkkkkkkkk0100kkkkkkkkkkkk1001kkkk10000011kkkkkkkk

C,DC,ZZ

TO,PD

Z

TO,PDC,DC,Z

Z

Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ’0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.

Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU FamilyReference Manual (DS33023).



See page 27 of Peatman book.

9 Peatman - page 27


See page 27 of Peatman book.

10 Peatman - page 27

16F877 Development Tools

— A large amount of supplemental documentation

available at www.microchip.com

— Sizable amount of development can be completed

at home.

— MPASM - Assembler for PIC programs

— MPSIM - Simulator for PIC programs

� allows single-stepping.

� allows simulation of analog inputs.

� allows full evaluation of state.

— MPLAB - integrated hardware/software debugger

� front-end interface for MPASM and MPSIM

� configures MPLAD-ICD (hardware)

� allows for in-circuit testing.

11

Reading and Exercises

— 16F877 data sheet - pages 1-18, 26, 137-144

— Peatman book - Chapter 2.

Exercises:

— MPASM - learn to assemble and simulate a

demo program (today)

— MPLAB-ICD - learn to download, single-step,

and debug a program.

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PIC16F877A Intro

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