PI3WVR31310A, PI3WVR31313A and PI3WVR31212A in … · HDMI 2.0 (PI3WVR31310A) or HDMI 1.4b...

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PI3WVR31310A, PI3WVR31313A and PI3WVR31212A in notebook and HDTV By Paul Li

Table of Content

1.0 Introduction 2.0 The advantage of passive MUX over active MUX in notebook design 3.0 Why cascading of “passive MUX + active MUX” is better than “active MUX + active MUX”? 4.0 What is the recommended maximum trace for PIWVR31XXXA in Intel notebook design? 5.0 PI3WVR31XXXA function selection table 6.0 PI3WVR31XXXA in Notebook PC, DP monitor and HDTV applications 7.0 PI3WVR31313A HDMI 1.4b eye compliance test and DP re-driver 6.0Gbps eye test 8.0 Recommendation of system timing 9.0 Power and power de-coupling 10.0 Layout guideline 11.0 Appendix: application Reference Schematics


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1.0 Introduction The PI3WVR31XXXA switch family is developed to achieve high performance in switching high speed signals of DP1.2, DP1.3, HDMI 2.0 (PI3WVR31310A) or HDMI 1.4b (PI3WVR31313A, PI3WVR31212A) in laptop, AIO, PC, switch box, docking station, monitor and HDTV applications.

2.0 The advantage of passive MUX over active MUX in notebook design The market appealing notebooks:

Running for 6-8 hours in battery operation

Boot-up after power-off for 6-8 days

Intel mobile CPU/chipset can now achieve 6W power consumption, thus:

The ~0.4W to ~0.6W power consumption from an active MUX is high.

Especially when compared to the <0.003W power consumption from PI3WVR31310A, which is a 99% power saving compared to

an active MUX.

3.0 Why cascading of “passive MUX + active MUX” is better than “active MUX + active MUX”? If the 1

st MUX in cascading is a passive MUX, it will consume lower power and will not generate the random jitters mostly caused

by re-drivers, while the insertion loss from trace and the 1st passive MUX will be equalized by the 2

nd active MUX.

If both 1st MUX and 2

nd MUX are active, the double active cascading will double power consumption and will double random jitters

as well. Random jitters cannot be equalized by re-drivers thereby may fail the eye compliance test.

4.0 What is the recommended maximum DP trace for passive MUX in Intel notebook design? In Intel Kabylake design guideline, Intel recommends maximum 8” DP1.2 trace without passive MUX and 4.1” with passive MUX as to pass

DP 1.2 compliance test.

Intel deducted 3.9” trace from the 8” DP1.2 trace for the passive MUX, which is conservative for a high performance passive MUX, such as

the PI3WVR3131XA family, as explained in figure 1, figure 2a, figure 2b and in table-1 below.

Based on the DP1.2 eye compliance test results of the Pericom high speed passive switch (with similar performance as equivalent to the

PI3WVR313XA family) in figure 2a and figure 2b, as well the trace data in figure 1 and table-1, it is recommended as below.

Maximum 6.0” trace for DP1.2 (5.4Gbps) path, as:

Intel DP1.2 source PI3WVR3131XA DP connector

Maximum 3.5” trace for DP 1.3 (8Gbps) path, as:

Intel DP1.3 source PI3WVR3131XA DP connector

(Assuming the layout and schematics are as recommended as using 90ohm traces without chokes, etc., and in reasonable system

conditions)

Table 1 the insertion loss of Pericom high speed passive MUX (equivalent to PI3WVR3131XA) versus Intel trace board

Insertion

loss of 3”

trace on

Intel trace

board

Per inch

Pericom high speed passive switch (equivalent to PI3WVR31313A)

Insertion loss Equivalent trace length

(loss of switch/ loss of

1” trace)

Good-maximum DP1.2 trace

in Intel 8” trace topology

Insertion loss at

5.4Gbps (DP1.2)

-2.3db -0.77db -1.5db 1.95”

(1.5db/0.77db)

6.05”

(8”-1.95”)

Table 1 the insertion loss of the 3” FR4 differential trace was measured using Intel trace board and Agilent N5230A 20GHz Network

Analyzer, as setup in figure-1.


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4.1 The insertion loss of 3” differential trace on Intel trace board

Figure 1 the insertion loss of 3” FR4 differential trace on Intel trace board is measured using Agilent N5230A 20GHz Network Analyzer (chart by James Liu)

4.2 The Pericom high speed switch (with similar performance as equivalent to PI3WVR3XXXA) and Intel Haswell MB DP1.2 eye compliance test result


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Figure 2a the eye passed the DP1.2 (5.4Gbps) HBR2 compliance test 3.1 using Tektronix scope at 400mV, 3.5db pre-emphasis. The upper waveform is at T3 with emulation cable in scope. The lower waveform is at T2 without emulation cable (waveform by Jerry Chou). See test setup in figure 2b using Pericom high speed switch equivalent to PI3WVR31XXXA, with Asus H97i Intel Haswell MB and 7” DP trace.


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4.3 The test setup of 4.2

Figure 2b the test setup of Pericom high speed switch (equivalent to PI3WVR31XXXA) with 7” trace (2.8”+3.9”+0.3”) using Intel Haswell DP1.2 source has passed DP1.2 (5.4Gbps) eye compliance test 3.1 as in figure 2a

5.0 PI3WVR31XXXA function selection table

PI3WVR31313A/31310A/31212A function selection table-2a

Output ports Pin control I2C control ESD Package

PI3WVR31313A 2 passive DP ports

1 active HDMI port

Auto (no manual) HPD

priority, 3-EQ settings, 3

PRE_EM settings

HDMI Port 3: 8-EQ,

5 PRE_EM, all

settings, more…

Port 1-2: 2KV/HBM

Port 3: 8KV/contact

60 pin TQFN

package (5x9mm,

0.4mm pitch)

PI3WVR31310A 3 passive DP/HDMI

ports

Priority settings, DP-

HDMI selections,

more…

No I2C control Port 1-2-3: 2KV/HBM 60 pin TQFN

package (5x9mm,

0.4mm pitch)

PI3WVR31212A 1 passive DP port

1 active HDMI port

Auto (no manual) HPD

priority, 3-EQ settings, 3

PRE_EM settings

HDMI port 2: 8-EQ,

5 PRE_EM, all

settings, more…

Port 1: 2KV/HBM

Port 2: 8KV/contact

60 pin TQFN

package (5x9mm,

0.4mm pitch)

PI3WVR31313A/31310A/31212A function selection table-2b

Shutdown DP-channel

Operation power

HDMI-channel

Operation power

DP

Insertion loss/5.4Gbps

HDMI active output

trace (with reasonable

layout-topology)

PI3WVR31313A 70uA 0.002mW

(615uAx3.3V)

264mW

(80mA x 3.3V)

1.5db 4”-6”


(615uAx3.3V)

70uA 1.5db NC


(615uAx3.3V)

264mW

(80mA x 3.3V)

1.5db 4”-6”


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6.0 PI3WVR31XXXA in Notebook PC, DP monitor and HDTV applications

Figure 3, PI3WVR31313A in notebook with docking connector, HDMI connector and WIGIG

Figure 4, PI3WVR31313A in notebook with type-C connector, DP connector and HDMI connector


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Figure 6, PI3WVR31310A in notebook with type-C connector, docking connector and WIGIG


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Figure 8, PI3WVR31212A in notebook with docking connector and HDMI connector


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Figure 9, PI3WVR31310A in HDMI 2.0 HDTV


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Figure 10, PI3WVR31310A and PI3USB30532 in type-C DP monitor

No active DP re-driver needed in type-C MUX (PI3USB30532) or between PI3USB30532 and PI3WVR31310A in

cascading.

o Because there are sufficient total source and sink equalization, as:

Up to 9db output pre-emphasis (equalization) in DP source

Up to 9db input equalization in DP sink scalar

o The total 18db equalization in DP source and DP sink is sufficient to compensate the estimated total insertion loss

from the topology in figure 10:

Max 7.7db from total 10” traces

Max 4db from 2 meter type-Cable

Max 1.5db from PI3USB30532

Max 1.5db from PI3WVR31310A


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Figure 11, PI3WVR31310A in HDMI 2.0 switch box

7.0 PI3WVR31313A HDMI 1.4b eye compliance test and DP re-driver equalized long trace 6.0Gbps eye test


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Figure 12, PI3WVR31313A passed HDMI 1.4b eye compliance test (waveform by Ada Yip)


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Figure 13, the 8.3db equalization in DP re-driver has well compensated the insertion loss from PI3WVR31XXXA and 26” trace (waveform by Nikolay Vitchev)


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8.0 Recommendation of system timing When laptop is power-on at T0 (figure-14), laptop will take 2s - 20s uploading Windows, then, Windows will start to detect HPD-

high at HPD_SRC, at T2.

When laptop powers-on at T0 and sequentially powers-on the VDD of PI3WVR3131XA at T1, PI3WVR3131XA will take ~0.8s to

detect the HPD-high at the 3 DP output port1, port2, port3 of PI3WVR3131XA and then inform the DP source and Windows thru

HPD_SRC.

In order for Windows to correctly detect HPD-high at the 3 DP outputs ports in-time, system EC (MCU) shall control T1 to be >2.0s

earlier than T2.

Figure 14, the recommended system timing for PI3WVR313XA

9.0 Power and power de-coupling

Use 0.1uf in size of 0402 for all the Vdd (any power pins) pins of the IC device, as close to the Vdd pins as possible, within 2-3mm if

feasible.

Use dedicated Vdd and GND planes for to minimize the jitters coupled between channel trough power sources.

10 Layout guideline 10.1 Recommend 90 ohm differential impedance trace for differential DP and USB 3.0 signals


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Figure 15, the trace width and clearance

Use 6-7-6 mils for trace-space-trace for the micro-strip lines (the traces on top and bottom layers) for 90 ohm differential

impedance.

Use 6-5-6 mils for trace-space-trace for the strip-lines (the traces inside layers) for 90 ohm differential impedance.

Use FR4.

Using standard 4 to 8 layers stack-up with 0.062 inch thick PCB.

For micro-strip lines, using ½ OZ Cu plated is ok.

For strip-lines in 6 plus players, using 1 OZ Cu is better.

The trace length miss-matching shall be less than 5 mils for the “+” and “–“ traces in the same pairs

More pair-to-pair spacing for minimal crosstalk

Target differential Zo of 90 ohm ±15%


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10.2 The PCB Layers Stackup

No new PCB technology required. Use FR4 is fine. Using standard 4 to 8 layers stack-up with 0.062 inch thick PCB. For micro strip lines, using ½ OZ Cu plated is ok. For strip line in 6 plus players, using 1 OZ Cu is better.

Figure 16, the stackup

Stack-up Plane Material Thickness (mil)

Solder mask Mask paint 1.2

Signal Copper 1.9

Prepreg 2116 4.4

Vcc Copper 1.4

Core 47

Vss Copper 1.4

Prepreg 2116 4.4

Signal Copper 1.9

Solder mask Mask paint 1.2

Total 62.4

10.3 The Layout Guidance for the Trace Routings


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Figure 17, The layout guidance for the trace routings

Don’t use EMI chokes for passive switch channels, which do have have EMI issues. The differential traces shall be away from the strong EMI source and devices, such as TTL, switching-power traces and

devices, with at least 30mil to 50mil space. No other components shall piggy ride on the differential traces.

11 Appendix: application Reference Schematics


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CAB_SRC

C103

4.7u

HDMI recept

U15

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10111213141516171819

D2+GNDD2-D1+GNDD1-D0+GNDD0-CLK+GNDCLK-CECRSVSCLSDADDC/CEC GND5V PowerHPD

TVS

D2

N3

C99 0.1uf

C97 0.1uf

C95 0.1uf

SCL_CTL D1-B

D0-A

D0N2

D0-B

SDA C920.1uf

D0N1

R78

100K

12

CEC1

HPD2

D0-B

C109

0.1u

+3V3

D2N1

Source I2C

to sink

D0+B

D3N1

D3-B

D0

N3

D1

P3

D2P1

D0+A

D2-B

C105

1uf

CL

KN

3

D1N2

SD

A3

D0-A

D0N2

D3P1

R83

100K

12

D3P1

C87 0.1uf

PI3WVR31313A

U13

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53

52

51

D1N1D2P1D2N1D3P1D3N1

HPD1

D0P2D0N2D1P2D1N2D2P2D2N2D3P2D3N2CEXT

D0

N3

VD

DC

LKP

3

SCL_CTL/EQSDA_CTL/PRI_SELD3ND3PD2ND2PD1ND1PD0ND0P

AU

XN

AU

XP

AU

X2

N/S

DA2

SD

A3

AU

X2

P/S

CL

2D

0P3

D1

N3

D1P1D0N1D0P1

SC

L3

CL

KN

3

PG

ND

OEBSCLSDAVDDHPD_SRCCAB_SRC

I2C_A1/PRE_EMPI2C_A2/ROUT_SELHPD3HPD2

VDD

MS

D1

P3

VD

DD

2N

3D

2P3

CA

B_

2A

UX1

P/S

CL

1A

UX1

N/S

DA1

CA

B_

1

R72NC

12

D2+B

+3V3

D3+A

D0N1

D3P2D3+B

AU

X2

P

D2-A

D0+A

CA

B_

2

D0+B

C91 0.1uf

D1-B

AUXP

C108

0.1u

R73

1M

12

CAB_1

R64

100K

12

AUX2N

R74

5M

12

C111

10uf

D3P

D0-B

D1-A

+3V3

D0+B

AUX2P

D3N2

D1N1

R82

2.2K

12

C90 0.1u

C940.1uf

AU

X2

N

D2N1

C107

0.1uSCL3

C860.1uf

D0P1

C93 0.1uf

D1P

D3+B

D1N2

C980.1uf

D1N

CAB_2

D3N1

D1-B

D1P2

CAB_SRC

R80

NC

12

TVS

D3P2

C1010.1uf D2-B

D1P3

DP port, type-C activeMUX or WIGIG

U14

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D0+GNDD0-D1+GNDD1-D2+GNDD2-D3+GNDD3-CAB_DETCECAUX+GNDAUX-HPDDP_PWR_RTNDP_PWR

R76

100K

12

D2N2

D3-B

R62

1M

12

D3-A

C88 0.1u

AUXN

C1040.1uf

C1000.1uf

C960.1uf

D2N3

D3N2 D3-B

D0P3

R81

2.2K

12

R63

NC

12

CEC2

D3+B

R66

4.7K

12

+3V3

D1P1

D1+B

D2-B

+3V3

D1-A

Contact Diodes local sales for TVS

+3V3DP

D2-A

SC

L3

C110

0.1u

D2P3

AU

X1

N

D0P

R79

100K

12

SCL

D1+A

D2P2

D0P1

D1+B

D2P

R75

5M

12

+5V0

+3V3

CA

B_

1

AU

X1

P

D2N

R77

100K

12

R68100K

12

CLKP3

D2+B

C890.1uf

System

controlS

PI3WVR31313A

thru I2C

CEC3

D2P1

D0N3

D2N2

AUX1P

D0N

+3V3

D0

P3

D1+B

R65

4.7K

12

C106

10u

HPD_SRC

AUX1N

D3+A

D1N3

D2+A

Intel

Dual mode

DP source

HPD_SRC

D2P2D3N

D2

P3

TVSD2+A

SDA_CTL

D1N1

R71NC

12

C1020.1uf

D0P2

CL

KP

3

R67100K

12

+5V0

D1

N3

TVS

SDA3

D1P2

Docking

connector

R70

NC (for I2C)

12

+3V3

D3-A

CLKN3

D0P2

D1+A

D2+B

D1P1

HPD1

R69NC (for I2C)

12

PI3WVR31313A DP++ source reference schematic for Notebook, AIO and PC applications


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D2+B

J 1

CON_DP_Sink_Rec ept

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1413

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ML_Lane 3 (n)GNDML_Lane 3 (p)ML_Lane2 (n)GNDML_Lane 2 (p)ML_Lane 1 (n)GNDML_Lane 1 (p)ML_Lane 0 (n)GNDML_Lane 0 (p)

CECCAB_DET

AUX_CH (p)

DP_PWR_RTN

AUX_CH (n)HPD

DP_PWR

GND

SHE

LL1

SHE

LL2

SHL

D3

SHL

D4

D0-A

CEC

C100.1u

D0+B

D2+A

C300.1u

TVS

D2-C

J 3

CON_DP_Sink_Rec ept

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1413

15

19

1718

20

16

21

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24


CECCAB_DET

AUX_CH (p)

DP_PWR_RTN

AUX_CH (n)HPD

DP_PWR

GND

SHE

LL1

SHE

LL2

SHL

D3

SHL

D4

D2-A

C1

22uf

D0-C

D3+C

R4

1M

HPD

2

C30.1u

D2-B

R15

1M

D1-A

D3+B

R10

100

K

C310.1u

C110.1u

D0-B

D0+B

D3-C

3V3

R2

1M

3V3

TVS

D3+A

D0-A

D0+C

D2+C

C24

0.1u

D3-A

DP sink scalar

R11

1K

C25

0.1u

C70.1u

C90.1u

R16

100

K

D2-A

D1-C

C180.1u

TVS

D1-B

D3+C

R7

1M

D0-C


R12

1M

C80.1u

R6

1M

D3-A D3-B

D1+B

D1+C

D1+BD1-C

C340.1u

C220.1u

C40.1u

C15

22uf

C350.1u

(option)

HPD

1

CEC

HPD3

C23

4.7u

3V3

C160.1u

C320.1u

CEC

3V3

D2-B

D3-B

R3

1M

(option)

D3+B

R8

1M

C28

22uf

SEL0

D1-B

D3-C

C27

0.1u

3V3

TVS

HPD_SRC

R1

1M

R13

1M

TVS

C60.1u

D0+A

D1+C

C210.1u

D1-A

R9

1M

C290.1u

D0-B

D1+A

SEL1

D2+B

D2-C

D2+A

D1+A

(option)

SEL1_0 = 00,01,10 only

(no 11 for auto mode)

C170.1u

C120.1u

J 2

CON_DP_Sink_Rec ept

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1413

15

19

1718

20

16

21

22

23

24


CECCAB_DET

AUX_CH (p)

DP_PWR_RTN

AUX_CH (n)HPD

DP_PWR

GND

SHE

LL1

SHE

LL2

SHL

D3

SHL

D4

C330.1u

TVS

3V3

C140.1u

R14

1M

C200.1u

C50.1u

C20.1u

3V3

D2+C

R5

100

K

C190.1u

C380.1u

PI3WV R31310A

U1

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AUX1P/SCL1

D0P3D0N3D1P3D1N3D2P3D2N3D3P3D3N3VDD

AUX

3P/S

CL

3A

UX

3N/S

DA

3D

P_

HDM

I

DEM UX_MUXHPD3CAB_3CAB_SRCHPD_SRCSEL0SEL1D3ND3PD2N

D0P

1D

0N

1

D2N

1

D1N

1D

2P

1C

AB

_2

HPD

2

D1P2D0N2D0P2

D1P

1

VDD

PG

ND

VDDD0PD0ND1PD1ND2P

AUXPAUXNSCLSDA

VDD

AUX1N/SDA1

AUX

2N/S

DA

2A

UX

2P/S

CL

2C

AB

_1

HPD

1

D3P

1D

3N

1P

RI_

SE

LO

EB

C130.1u

D0+C

C370.1u

D0+A

C360.1u

D3+A

C26

0.1u

PI3WVR31310A DP sink reference schematic for DP monitor applications


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D3N3

D3+C

PI3WVR31310A

U2

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AUX1P/SCL1


AU

X3

P/S

CL

3A

UX

3N

/SD

A3

DP

_H

DM

ICAP_SRCHPD_SRCSEL0SEL1D3ND3PD2ND2PD1ND1P

D0

P1

D0

N1

D2

N1

D1

N1

D2

P1

CA

B_

2H

PD

2

D1P2D0N2D0P2

D1

P1

VD

D

PG

ND

VDDD0PD0N

CAB_3HPD3DEMUX_MUXAUXP

VDD

AUX1N/SDA1

AU

X2

N/S

DA

2A

UX

2P

/SC

L2

CA

B_

1H

PD

1

D3

P1

D3

N1

PR

I_S

EL

OE

B

AUXNSCLSDA

C470.1u

+3V3DP

+3V3

D2P

AUXN

R31

5M

12D3-B

C390.1u


D3N2

D3-C

C41 0.1u

R22

NC

12

D1-C

AUX1P

D3N

D1

N1

D1+B

D1-B

D1P3

D2N2D0-B

D1-C

TVS

CAB_1

C56 0.1u

+3V3DP

D3+B

D0+A

D3-C

D1P1 C420.1u

C62

0.1u

AUX3P

D0+C

D0P3

D0-C

D1N2

D2+B

TVS

+3V3

CAB_SRC

C600.1u

D2-C

C59 0.1u

HPD_SRC

SDA

D1N3

D2-C

D0P1

D0+B

R35

1M

12

+3V3

AUX2N

D2+A

AUX1N

R34100K

12

+3V3

CAB_SRC

D0

P1

D3P

C66 0.1u

D0

N1

C63

0.1u

C68 0.1u

D1N3

HPD2

R33100K

12

D1N1

CAB_2

HPD_SRC

DP port, Type-C active MUX or WIGIG

U3

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1011121314151617181920


CEC1

D2N

R18

100K (Auto)

12

D3+A

D0-B

C71

10uf

D3+A

D2N1

C43 0.1u

D3P3

D3N3

C64

0.1u

D2

P1

D0N1

D3P3

C52 0.1u

R27100K

12

D1+A

D2P2

C480.1u

D1+C

D2P1

C510.1u

CAB_3

C530.1u

D1-A

R21

NC

12

D0+B

TVS

HPD1

D1+B

D3-A

D1-A

R29

1M

12

D2N3

C44 0.1u

R36

5M

12

D1P2

D3P2

D2P3

D2

N1

D2+C

Docking connector

D0P3

R17

100K (Auto)

12

D3P1

D1N

HPD3

D1+C

D3+B

D3N1

D1

P1

R23

100K

12

SCL

D3+B

CEC2

D0+A

TVS

DP source

D3-A

D1-B

D2N3

R26

4.7K

12

D1N2

D2-B

AUXP

AUX3ND1P3

AUX2P

D0-A

R32

5M

12

D2+B

C580.1u

D2P2

D0P

D0+C

R30

1M

12

C65

0.1u

D1+B

D0N3

D2+A

R25

4.7K

12

C46 0.1u

C50 0.1u

D0N

C670.1u

D3-B

C57

10uf

D1+A

D0-B

D1-B

D2P3

D0N3

D2-A

D0-C

D0P2

DP port, Type-C active MUX or WIGIG

U4

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1011121314151617181920


D3-B

D2-B

D0P2

C54 0.1uD2N2

C40 0.1u

D0N2

D0-A

D2+B

C61

10u

D3N2

R24

100K

12

R19

NC

12

D2+C

C550.1u

D0N2

R37

5M1

2

C450.1u

D0+B

D3

P1

+3V3

R20

NC

12

R28100K

12

+3V3

CEC3

D3

N1

C49 0.1u

D2-A

D1P

D1P2

C690.1u

+3V3

C70 0.1u

D3P2

D2-B

D3+C

PI3WVR31310A DP source reference schematic for Notebook, AIO and PC applications


www.pericom.com

of 22 6/8/2017

ANXXX

D1+C

HPD1

R3

91

M

HDP_sink

C73

0.1u

CEC

C74

0.1u

D1+B

R5010K

12

R4

51

0K

D0-B

R4710K

12

3V3

5VHDMI

CLK+B

HDMI recept

U7

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CLK-C

D2+C

D3

BAT54WS

12

D0-A

CLK+A

EEPROM

EDID

CLK-A

CLK-C

D2+A

R4

31

M

R4610K

12

5VHDMI

D0-A

R4010K

12

3V3

CLK+C

D2

BAT54WS

12

D0-C

SEL1,SEL0 = 00,01,10 only

(no 11 for auto mode)

SEL1

D2+B

HPD3

R421K

TVS

TVSD1+C

CECD0-B

+5VHDM I

D2-C

D1+B

CLK+B

C76

0.1u

HDMI recept

U5123456789

10111213141516171819


D2-B

D0-C

D2-A

R4110K

12

R5110K

12

HPD2


D0+A

D2-B

SEL0

R4

41

0K

D1

BAT54WS

12

HDMI recept

U8

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R481K

3V3

CLK+C

C75

0.1u

D2+C

TVSTVS

D0+A

+5VHDM I

D1-A

D1+A

D2+B

D1+A

EEPROM

EDID

+5VHDM I

TVS

D2+A

D1-B

R381K

EEPROM

EDID

TVS

PI3WV R31310A

U6

4645444342

32

414039383736353433

24

23

22

16151413121110987

60

59

55

57

56

25

26

474849

58

21

61

123456

17181920

50

312

72

82

93

0

54

53

52

51


AUX1P/SCL1


AUX

3P

/SCL

3A

UX

3N

/SDA

3D

P_

HD

MI


D0

P1

D0

N1

D2

N1

D1

N1

D2

P1

CA

B_

2H

PD

2

D1P2D0N2D0P2

D1

P1

VDD

PG

ND

VDDD0PD0ND1PD1ND2P

AUXPAUXNSCLSDA

VDD

AUX1N/SDA1A

UX

2N

/SDA

2A

UX

2P

/SCL

2C

AB

_1

HP

D1

D3

P1

D3

N1

PRI_

SE

LO

EB

HDMI sinkscalar

CLK-B

D1-C

D0+B

CLK-B

R4

91

M

CLK-A

D1-BD1-A

D0+B D0+C

C72

4.7u

CLK+A

D1-C

CEC

5VHDMI

D2-A

D2-C

D0+C

PI3WVR31310A HDMI sink reference schematic for HDMI monitor and HDTV applications


www.pericom.com

of 22 6/8/2017

ANXXX

D4

BAT54WS

12

For HDMI source

Ioff test R534.7K

12

D0-A

D2+B

R544.7K

12

R614.7K

12

C83

0.1u

C85

10uf

CLK-C

C84

10uf

5VHDMI

D0+B

CLK-B

CEC

D0+A

+5VHDM I

D1+B

D1-B

D2+C

C77

0.22uf

HDMIsource

+5VHDM I

CLK+B

D2-A

D0+C

D1-A

D2-B

D2+A

SEL1


D2+B

+5VHDM I

TVS

C81

0.1u

CEC

TVS

C79

4.7u

TVS

3V3

D1+A

D2-B

TVS

CLK+A

CLK+C

D1-C

HPD3

C80

0.1u

D1+C

R5233K

12

HDMI recept

U9123456789

10111213141516171819


C82

0.1u

5VHDMI

D0+CD0-B

CLK-A

5VHDMI

HDMI recept

U12

123456789

10111213141516171819


R604.7K

12

R55

10K

D2+C

HPD2

D1-B

D1+B

SEL0

CLK+A

D0-B

C78

10uf

PI3WV R31310A

U10

4645444342

32

414039383736353433

24

23

22

16151413121110987

60

59

55

57

56

25

26

474849

58

21

61

123456

17181920

50

31

27

28

29

30

54

53

52

51


AUX1P/SCL1


AUX

3P/S

CL

3A

UX

3N/S

DA

3D

P_

HDM

I


D0

P1

D0

N1

D2

N1

D1

N1

D2

P1

CAB

_2

HPD

2

D1P2D0N2D0P2

D1

P1

VDD

PG

ND

VDDD0PD0ND1PD1ND2P

AUXPAUXNSCLSDA

VDD

AUX1N/SDA1

AUX

2N/S

DA

2A

UX

2P/S

CL

2C

AB

_1

HPD

1

D3

P1

D3

N1

PRI_

SE

LO

EB

R56

10K

TVS

CEC

HDMI recept

U11

123456789

10111213141516171819


D1-A

3V3

D0-C

HPD

D0+A

CLK-C

D2-A

R574.7K

12

HPD1

CLK-A

D1+C

D2-C

CLK+B

D2+A

D0-C

D0+B

3V3

TVSCLK+C

3V3

R59

10K

D0-A

CLK-B

D2-C

R584.7K

12

D1-C

D1+A

PI3WVR31310A HDMI source reference schematic

PI3WVR31310A, PI3WVR31313A and PI3WVR31212A in … · HDMI 2.0 (PI3WVR31310A) or HDMI 1.4b...

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Transcript of PI3WVR31310A, PI3WVR31313A and PI3WVR31212A in … · HDMI 2.0 (PI3WVR31310A) or HDMI 1.4b...