Physics-based modeling of time-dependent variability in ... … · variability in MOS devices for...
Transcript of Physics-based modeling of time-dependent variability in ... … · variability in MOS devices for...
Physics-based modeling of time-dependent variability in MOS devices for circuit simulation
J. Martín-Martínez, M. Nafría, R. Rodríguez and X. Aymerich
(Figure FEP2. ITRS’09)
New materials and/or device architectures. Reliability challenges.
SOME reliability issues
§ Need for Design for reliability tools
§ New or changed Failure Mechanisms
§ Process variability
(Extracted from Table PIDS1, ITRS’10)
>16nm
<16nm
LG
MOSFET scaling challenges
(Figure FEP2. ITRS’09)
New materials and/or device architectures. Reliability challenges.
SOME reliability issues
§ Need for Design for reliability tools
§ New or changed Failure Mechanisms
§ Process variability
(Extracted from Table PIDS1, ITRS’10)
>16nm
<16nm
LG
MOSFET scaling challenges
Outline
Variability in MOSFETs ‘Time-zero’ variability ‘Time-dependent’ variability
Bias Temperature Instability Device modeling RELAB: Circuit aging estimation
Dielectric breakdown
Conclusions
Outline
Variability in MOSFETs ‘Time-zero’ variability ‘Time-dependent’ variability
Bias Temperature Instability Device modeling RELAB: Circuit aging estimation
Dielectric breakdown
Conclusions
Random Dopant Distribution
Oxide Thickness Fluctuations
Granularity (poly, high-k)
Line Edge Roughness
Asenov, VLSI Symp. 2007
Related to atomic-level intrinsic variations.
DEV
ICE
CIR
CU
IT
VT dispersion
Time-zero variability
Outline
Variability in MOSFETs ‘Time-zero’ variability ‘Time-dependent’ variability (Reliability)
Bias Temperature Instability Device modeling RELAB: Circuit aging estimation
Dielectric breakdown
Conclusions
0V 0V
0V
VG
Interfacial trap generation Time (s)
0
5
10
15
20
25
0 500 1000 1500 2000
ΔV th (
mV)
Stress (High |VG|)
Relaxation (Low |VG|)
Reaction-Diffusion model
Device level -> VT shift
Degradation Recovery
Degradation in circuits
progressive |Vth| increase High Eox
Time-dependent variability (1): Bias Temperature Instability (BTI)
[M. Alam et. al. MR 2005]
Fails in the description of recovery voltage and temperature dependences [Nigam IEEE IRPS 2006]
Time-dependent variability (1): Bias Temperature Instability (BTI)
Small devices:
BTI becomes stochastic
Discrete VT drops
Discharge of individual defects
Time dependent defect spectroscopy (T. Grasser IEEE IRPS 2010)
Two stage model
Probabilistic Deffect Occupancy model [J. Martin-Martinez IEEE IRPS 2011]
New generation of BTI models
(This talk)
New characterization techniques
[T. Grasser IRPS 2010]
Large devices: Continuous recovery
[H. Reisinger IEEE IRPS 2010]
[B. Kazcer IEEE IRPS 2008]
1 10 100 1000 100001E-6
1E-5
HBDSBD
Dynamic
3.8V3.6V
3.4V
3.2V
I (A
)
Stress time (s)
3.0V SBD
0V 0V
0V
VG
Conductive filament
Time (s)
Gat
e cu
rren
t (µA
)
Time to breakdown (tBD)
Loss of the gate oxide insulating properties Time-dependent variability (2): Dielectric Breakdown (BD)
Gate current evolution with time
Percolative model [Suñe Solid State 90]
tBD is weibull distributed
Gate current vs gate voltage
High gate current after BD
Gat
e cu
rren
t (A
)
Gate voltage (V)
Ln(-
Ln(1
-F))
Ln(tBD)
Transistor characteristics after BD
Gate BD current is described by including current sources controlled by voltage
Electrical modelling of dielectric breakdown. SRAM cell
Impact in circuits
Dielectric breakdown Circuit failure
Ex. Ring oscillator
Initial
Several BDs
CMOS inverter
(B. Kazcer. IEEE TED, 2002)
[R. Rodríguez. et al.IEE EDL. 2002]
Time-dependent variability (2): Dielectric Breakdown (BD)
BD deforms transistor characteristics (high dependence of device geometry, BD location…)
[R. Fernandez TED 2008]
[R. Rodríguez. et al. IEEE EDL. 2003]
Nominal design point
1 year 10 years
Delay (a.u.)
Ener
gy (a
.u.)
Time zero variability
Circuit operation point
Process related variability t =0
Nominal design point
1 year 10 years
Delay (a.u.)
Ener
gy (a
.u.)
Time zero variability
Circuit operation point
Process related variability t =0
Nominal design point
1 year 10 years
Delay (a.u.)
Ener
gy (a
.u.)
Time zero variability
Circuit operation point
Time dependent variability
BTI BD
Process related variability
Aging mechanisms (device degradation). t >0
t =0
Nominal design point
1 year 10 years
Delay (a.u.)
Ener
gy (a
.u.)
Time zero variability
Circuit operation point
Time dependent variability
BTI BD
Process related variability
Aging mechanisms (device degradation). t >0
t =0
We should be able to evaluate the time dependent variability effects
in the circuit performance
We need new tools
Outline
Variability in MOSFETs ‘Time-zero’ variability ‘Time-dependent’ variability
Bias Temperature Instability Device modeling RELAB: Circuit aging estimation
Dielectric breakdown
Conclusions
Measured
Simulated
Simulated
100 devices simulated
Stress time (s)
Bias Temperature Instability Failure probability in differential amplifiers
Stress time (s) Vth standard deviation (%) Failu
re p
roba
bilit
y SPICE BSIM4 parameters extraction
(VTH0 and U0)
VTH0 and U0 mean value and standard deviation
New set of VTH0 and U0 generated by montecarlo simulation
Circ
uit s
imul
atio
n
BTI characterization in nMOS and pMOS
Low σ(Vth) (<2%)
High σ(Vth) (>8%)
Medium σ(Vth)
Very reliable circuits
Yield problem
Good yield, bad reliability
Weakness: Different operation conditions of transistors can be very difficult to be considered
Need of physical BTI models [J. Martin-Martinez IEEE TDMR 2009]
BTI: Probability Defect Occupancy Model Model for a single defect
Occupied: emission probability= Δt/τe Empty: capture probability = Δt/τC
Occupancy probability
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛ −−−⎟⎟
⎠
⎞⎜⎜⎝
⎛−
++=
H
iiocc
HcHe
Heioccocc
tttPVV
VtPtPτττ
τ )(exp1·)()()(
)()()(
⎟⎟⎠
⎞⎜⎜⎝
⎛ −−⎟⎟⎠
⎞⎜⎜⎝
⎛
+−+
+=
L
i
LcLe
Leiocc
LcLe
Leocc
ttVV
VtPVV
VtPτττ
τττ
τ )(·exp)()(
)()()()(
)()(
High voltage:
Low voltage:
Capture and emission times (τC, τe) Voltage and temperature dependent Vth shift caused in the defect charge/discharge (η) Defect parameters
Model for a device
Dra
in
Sour
ce
∑=
=ΔN
iiith kV
1
·ηN defects
Occupied Empty
Ki = 1 if occupied
0 if empty
MOSFET top view
[J. Martin-Martinez IEEE IRPS 2011]
BTI: Probability Defect Occupancy Model Experimental verification
(a)
(b)
1E-4 1E-3 0,01 0,1 1
-2
-1
0
1
2
ln(-l
n(1-
F) trelax(s)
tstress = 1900s
|ΔVT| (V)
1E-2 1E-1 1E0 1E1 1E2
relaxation
1E-4 1E-3 0,01 0,1 1
-2
-1
0
1
2
ln(-l
n(1-
F) trelax(s)
tstress = 1900s
|ΔVT| (V)
1E-2 1E-1 1E0 1E1 1E2
relaxation
(a) (b)
(c) (d)
Vth recovery in small devices
ΔVth distributions
Simulation Experimental
Large area devices: DC and AC simulation
Probability Defect Occupancy model works as a virtual experiment
PDO reproduces the BTI phenomenology and its stochastic nature
How can it be used for circuit aging evaluation?
Outline
Variability in MOSFETs ‘Time-zero’ variability ‘Time-dependent’ variability
Bias Temperature Instability Device modeling RELAB: Circuit aging estimation
Dielectric breakdown
Conclusions
BTI: Inclusion in circuit simulators
Netlist
Devices geometryand type
Stress waveforms
Variabilitymodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Netlist
Devices geometryand type
Stress waveforms
Variabilitymodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Netlist
Devices geometryand type
Devices geometryand type
Stress waveformsStress waveforms
Variabilitymodels
Variabilitymodels
Degradationmodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Variability and Reliability Data base
SPICE Transientsim
ulation
Netlist
Devices geometryand type
Stress waveforms
Variabilitymodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Netlist
Devices geometryand type
Stress waveforms
Variabilitymodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Netlist
Devices geometryand type
Devices geometryand type
Stress waveformsStress waveforms
Variabilitymodels
Variabilitymodels
Degradationmodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Variability and Reliability Data base
SPICE Transientsim
ulation
RELAB: Reliability Evaluation tool
BTI: Inclusion in circuit simulators
Netlist
Devices geometryand type
Stress waveforms
Variabilitymodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Netlist
Devices geometryand type
Stress waveforms
Variabilitymodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Netlist
Devices geometryand type
Devices geometryand type
Stress waveformsStress waveforms
Variabilitymodels
Variabilitymodels
Degradationmodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Variability and Reliability Data base
SPICE Transientsim
ulation
Netlist
Devices geometryand type
Stress waveforms
Variabilitymodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Netlist
Devices geometryand type
Stress waveforms
Variabilitymodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Netlist
Devices geometryand type
Devices geometryand type
Stress waveformsStress waveforms
Variabilitymodels
Variabilitymodels
Degradationmodels
Degradationmodels
Modified netlists
Transientsimulation
SPICEsimulation
Analysis
Variability and Reliability Data base
SPICE Transientsim
ulation
RELAB: Reliability Evaluation tool
Channel Width, lengthand transistor type
calculation of ΔVth
Spice file line
modelsChannel Width, lengthand transistor type
calculation of ΔVth
Spice file line
models
Example to include Vth shifts
BTI: Inclusion in circuit simulators
‘Time-zero’ variability Circuit example
Vth shifts due to BTI Sensitivity analysis Circuit performance: Delay time distributions
Detection of weak devices
8,5 9,0 9,5 10,0 10,5 11,0
1
10
40
70
95
99,5
Prob
abili
ty (%
)Delay time (ns)
1µs 100µs 10ms 1s
Extrapolated to 1 year
Pelgrom’s rule is used to account for Vth process variability
BTI is included from PDO model
Circuit performance can be evaluated
[M. Nafria IEEE IEDM 2011]
Pelgrom’s rule: σ(Vth)α(W·L)^-1/2
time
Outline
Variability in MOSFETs ‘Time-zero’ variability ‘Time-dependent’ variability
Bias Temperature Instability Device modeling RELAB: Circuit aging estimation
Dielectric breakdown
Conclusions
3,0 3,2 3,4 3,6 3,8100
101
102
103
104 DC Pulsado V-n
η (s
)
Vestrés (V)
V -32
Dielectric Breakdown in RELAB
-1,5 -1,0 -0,5 0,0 0,5 1,0 1,51E-11
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
1E-4
1E-3
muestra
fres
cas
|I G(A
)|
VGS (v)
Rupturas en las difusionesRupturas en el canal Modelo D-R
RELAB model used for BD (based in QPC [Sune APL 1999]
Gate current variability
(R. Fernández et. al. TED Vol. 55, pp. 997-1004 (2008)
⎥⎥⎦
⎤
⎢⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛−−=
β
η ),(exp1)(
TVttF BD
tBD: Weibull distribution (percolative model)
[Suñe MR 2005]
Model parameters statistically distributed
Weibull parameters dependence of voltage -> lifetime estimation
Gat
e cu
rren
t (A
)
Gate voltage (V)
Examples: 5-stage ring oscilator and digital block
Simulation Experimental oscillation frequency distribution
Ring oscillator operation point after BD
(B. Kazcer. et al. TED. Vol. 49, pp. 500-506, 2002) Δfosc/fosc (%)
Pow
er c
onsu
mpt
ion
(µW
)
Frequency (MHz)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1E-8
1E-7
1E-6 10 years
Pro
babi
lity
of B
D
# of transistor
1 year
Device op. Conditions + BD theory = Identification of weak devices
[J. Martin-Martinez IEEE TDMR 2012]
Cum
ulat
ive
frac
tion
Digital block RO
Random fluctuations + device aging (time-dependent variability) must be propagated to upper levels to predict circuit performance and reliability.
CONCLUSIONS
Key points: § Physical models for aging mechanisms.
Reliability data base (model parameter extraction).
SPICE modeling: § Equivalent electrical circuits connected to the
MOSFET terminals, based on the physical models.
RELAB: Simulation tool, based on the underlying technology and device physics, that evaluates circuit performance and reliability when time-dependent variability is considered.
J. Martín-Martínez, M. Nafría, R. Rodríguez and X. Aymerich
Physics-based modeling of time-dependent variability in MOS devices for circuit simulation