Physical Limits of ComputingPhysical Limits of ComputingDr. Mike FrankDr. Mike Frank

CIS 6930, Sec. #3753X CIS 6930, Sec. #3753XSpring 2002Spring 2002

Lecture #31Lecture #31Reversible Processor ArchitecturesReversible Processor Architectures

Wed., Mar. 27Wed., Mar. 27

Administrivia & OverviewAdministrivia & Overview• Don’t forget to keep up with homework!Don’t forget to keep up with homework!

– We are We are 10 out of 14 weeks into the course.10 out of 14 weeks into the course.• You should have earned You should have earned ~71 points by now.~71 points by now.

• Course outline:Course outline:– Part I&II, Part I&II, BackgroundBackground, , Fundamental LimitsFundamental Limits - done - done– Part III, Part III, Future of Semiconductor TechnologyFuture of Semiconductor Technology - done - done– Part IV, Part IV, Potential Future Computing TechnologiesPotential Future Computing Technologies - done - done– Part V, Part V, Classical Reversible ComputingClassical Reversible Computing

• Fri. 3/22: RevComp theory II: Emulating Irreversible Machines Fri. 3/22: RevComp theory II: Emulating Irreversible Machines RevComp theory II: Bounds on Space-Time OverheadsRevComp theory II: Bounds on Space-Time Overheads

• Mon. 3/25: RevComp scaling analysis I: Cost, energy, area-time.Mon. 3/25: RevComp scaling analysis I: Cost, energy, area-time.• Wed. 3/27: RevComp scaling analysis II: Spacetime and time.Wed. 3/27: RevComp scaling analysis II: Spacetime and time.• Fri. 3/29: Reversible processor architectures.Fri. 3/29: Reversible processor architectures.• Mon. 4/1: Reversible programming languages.Mon. 4/1: Reversible programming languages.• Wed. 4/3: Reversible algorithms.Wed. 4/3: Reversible algorithms.

– Part VI, Part VI, Quantum Computing - starts Fri. 4/5Quantum Computing - starts Fri. 4/5– Part VII, Part VII, Cosmological Limits, Wrap-UpCosmological Limits, Wrap-Up

Why reversible architectures?Why reversible architectures?• What about automatic emulation algorithms?What about automatic emulation algorithms?

– E.g.: Ben73, Ben89, LMT, Frank02.E.g.: Ben73, Ben89, LMT, Frank02.• Transform an irreversible alg. to an equiv. rev’ble one.Transform an irreversible alg. to an equiv. rev’ble one.

– But, these do not yield the most cost-efficient reversible But, these do not yield the most cost-efficient reversible algorithms for all problems!algorithms for all problems!

• E.g.E.g., log(, log(RRE(i./r)E(i./r)//RRon/offon/off) may be only 0.4 rather than 0.5.) may be only 0.4 rather than 0.5.• Finding the best reversible algorithm requires a creative Finding the best reversible algorithm requires a creative

algorithm discovery process!algorithm discovery process!

• An optimally cost-efficient general-purpose An optimally cost-efficient general-purpose architecture must allow the architecture must allow the programmerprogrammer to specify a to specify a custom reversible algorithm that is specific to his custom reversible algorithm that is specific to his problem.problem.

Reversibility Affects All LevelsReversibility Affects All Levels• As As RRon/offon/off increases & cost of device manuf. declines increases & cost of device manuf. declines

(while the cost of energy stays high),(while the cost of energy stays high),– Maximizing overall cost-efficiency requires an Maximizing overall cost-efficiency requires an increasingly increasingly

largelarge fraction of all bit-ops be done adiabatically. fraction of all bit-ops be done adiabatically.

• Maximizing the efficiency of the resulting algorithms, Maximizing the efficiency of the resulting algorithms, in turn, requires reversibility in:in turn, requires reversibility in:– Logic designLogic design– Functional unitsFunctional units– Instruction set architecturesInstruction set architectures– Programming languagesProgramming languages– High-level algorithmsHigh-level algorithms

Increasing requirementfor degree of reversibility

Pro-gram-mingmodel

(unless a perfect emulator is found)

All Known Reversible ArchitecturesAll Known Reversible Architectures• Ed BartonEd Barton (MIT class project, 1978) (MIT class project, 1978)

– Conservative logic, w. garbage stackConservative logic, w. garbage stack• Andrew ResslerAndrew Ressler (MIT bachelor’s thesis, 1979; MIT master’s thesis, 1981) (MIT bachelor’s thesis, 1979; MIT master’s thesis, 1981)

– Like Barton’s, but more detailed. Paired branches.Like Barton’s, but more detailed. Paired branches.• Henry BakerHenry Baker (1992) (1992)

– Reversible pointer automaton machine instructions.Reversible pointer automaton machine instructions.• J. Storrs “JoSH” HallJ. Storrs “JoSH” Hall (1994) (1994)

– Retractile-cascade-based PDP-10-like architecture.Retractile-cascade-based PDP-10-like architecture.• Carlin VieriCarlin Vieri (MIT master’s thesis, 1995) (MIT master’s thesis, 1995)

– Early Pendulum ISA, irrev. impl., full VHDL detail.Early Pendulum ISA, irrev. impl., full VHDL detail.• Frank & RixnerFrank & Rixner (MIT class project, 1996) (MIT class project, 1996)

– Tick: VLSI schematics & layout of Pendulum subset, w. paired branchesTick: VLSI schematics & layout of Pendulum subset, w. paired branches• Frank & LoveFrank & Love (MIT class project, 1996) (MIT class project, 1996)

– FlatTop: Adiabatic VLSI impl. of programmable reversible gate arrayFlatTop: Adiabatic VLSI impl. of programmable reversible gate array• VieriVieri (MIT Ph.D. thesis, 1999) (MIT Ph.D. thesis, 1999)

– Fully adiabatic VLSI implementation of Pendulum w. paired branchesFully adiabatic VLSI implementation of Pendulum w. paired branches

Reversible Programmable Gate-Reversible Programmable Gate-Array ArchitecturesArray Architectures

(as of May ‘99)

Photo of packaged FlatTop chipPhoto of packaged FlatTop chip

A Bouncing BBMCA “Ball”A Bouncing BBMCA “Ball”

A BBMCA Fredkin GateA BBMCA Fredkin Gate

Reversible von Neumann Reversible von Neumann ArchitecturesArchitectures

Reversible Architecture IssuesReversible Architecture Issues• Instruction-Set Architecture (ISA) Issues:Instruction-Set Architecture (ISA) Issues:

– How to define irrev. ops (AND, etc.) reversibly?How to define irrev. ops (AND, etc.) reversibly?– How to do jumps/branches reversibly?How to do jumps/branches reversibly?– What kind of memory interface to have?What kind of memory interface to have?– What about I/O?What about I/O?– How to permit How to permit efficientefficient reversible algorithms? reversible algorithms?– Should the hardware guarantee reversibility?Should the hardware guarantee reversibility?

• Microarchitectural issues:Microarchitectural issues:– Register file interfaceRegister file interface– Reversible ALU operationsReversible ALU operations– Shared busesShared buses– Program counter controlProgram counter control

The Trivial CasesThe Trivial Cases• Many typical instructions Many typical instructions alreadyalready reversible: reversible:

– NOT NOT aa• Set register Set register aa to its bitwise logical complement, to its bitwise logical complement, a a := ~:= ~aa

– NEG NEG aa• Set Set aa to its two’s complement negation to its two’s complement negation

aa := - := -a or a a or a := ~:= ~a + a + 11

– INC INC aa• Increment Increment aa by 1 (modulo 2 by 1 (modulo 2).).

– ADD ADD aa bb• Add register Add register bb into register into register aa ( (aa := ( := (aa + + bb) mod 2) mod 2))

– XOR XOR aa bb• Exclusive-or Exclusive-or bb into into aa ( (aa := := aa bb))

– ROL ROL aa bb• Rotate bits in register Rotate bits in register aa left by # positions given by left by # positions given by bb..

The Nontrivial CasesThe Nontrivial Cases• Other common instructions are not reversible…Other common instructions are not reversible…

– CLR CLR aa• Clear register Clear register aa to 0. to 0.

– LD LD aa bb• Load register Load register aa from addr. pointed to by from addr. pointed to by bb..

– LDI LDI aa 3 3• Load immediate value 3 into register Load immediate value 3 into register aa..

– AND AND aa bb• Set Set aa to the bitwise AND of to the bitwise AND of a a and and bb

– JMP JMP aa• Jump to the instruction pointed to by Jump to the instruction pointed to by aa..

– SLL SLL aa bb• Shift the bits in Shift the bits in aa left by left by bb bits, filling with 0’s on right. bits, filling with 0’s on right.

Irreversible Data OperationsIrreversible Data Operations• How to do expanding ops reversibly?How to do expanding ops reversibly?

– E.g.E.g., AND , AND aa bb - Prior value of - Prior value of aa is lost. is lost.

• Approach #1: “Garbage Stack” approach.Approach #1: “Garbage Stack” approach.– Based on Landauer’s embedding.Based on Landauer’s embedding.– Push all data that would otherwise be destroyed onto a Push all data that would otherwise be destroyed onto a

special “garbage” stack hidden from pgmr.special “garbage” stack hidden from pgmr.– Can unwind computation when finished to recover stack Can unwind computation when finished to recover stack

space. (Lecerf ‘63/Bennett ‘73 approach)space. (Lecerf ‘63/Bennett ‘73 approach)

• Problems: Large garbage stack memory needed.Problems: Large garbage stack memory needed.– Limits computation length.Limits computation length.– Leaves programmer no opportunity to choose a more Leaves programmer no opportunity to choose a more

efficient reversible algorithm!efficient reversible algorithm!

Illustrating Garbage StackIllustrating Garbage Stack• Let “Let “” mean reversible move, “” mean reversible move, “” mean ” mean

reversible copy, “reversible copy, “” a reversible uncopy.” a reversible uncopy.

AND a b implemented by...

1. t a2. a t & b3. t GSM[GSP++]

230

46

17

0

0...Garbage Stack

Memory (GSM)

Garbage StackPointer (GSP)

0

1

2

3

4

3

Programmer-Controlled GarbageProgrammer-Controlled Garbage• Put extra data in a programmer-manipulable location.Put extra data in a programmer-manipulable location.

– What if destination location isn’t empty?What if destination location isn’t empty?• Signal an error, orSignal an error, or• Use an op that does something reversible anywayUse an op that does something reversible anyway

• Provide Provide undoundo operations to accomplish operations to accomplish “unexpanding” inverses of expanding ops.“unexpanding” inverses of expanding ops.

• 1st method: Errors on non-empty destination:1st method: Errors on non-empty destination:– AND AND A B CA B C -If ( -If (AA=0)=0) A ABB&&CC else else errorerror– UNAND UNAND AA BB CC -If ( -If (AA==BB&&CC)) A ABB&&CC else else errorerror

• 2nd method: Use always-reversible store ops.2nd method: Use always-reversible store ops.– ANDX ANDX A B CA B C - - AA AA ( (BB & & CC) (self-undoing!)) (self-undoing!)

Pendulum - packaged chip photoPendulum - packaged chip photo