Pheripheral interface

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UNIT – III PERIPHERAL INTERFACE IC’S PREPARED BY, MANIKANDAN S AP / EEE JCT CET JCT College of Engineering and Technology, Coimbatore

Transcript of Pheripheral interface

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UNIT – III

PERIPHERAL INTERFACE IC’S

PREPARED BY,MANIKANDAN SAP / EEEJCT CET

JCT College of Engineering and Technology, Coimbatore

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8253/8254 Modes of Operation

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Mode 0: Interrupt on Terminal Count

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Mode 1: Programmable One Shot

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Mode 2: Rate Generator

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Mode 3: Square Wave Generator

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Mode 4: Soft Triggered Strobe

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Mode 5: Hardware Triggered Strobe

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Analog to Digital Converter

Types:

Counting Type A/D Converter

Successive Approximation ADC

Parallel or Flash Converter

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Specification of ADC

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Schematic Diagram of ADC

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Logic Diagram of ADC 0800

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Interfacing of ADC 0800

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Interfacing of ADC 0800 and Multiplexer with 8255

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Interfacing of 12 Bit ADC 0800

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Digital to Analog Converter

Types: Binary Weighted DAC R – 2R Ladder Circuit

Specification: Resolution Accuracy Offset/Zero Scale Error Linearity Settling Time Temperature Sensitivity

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8 Bit DAC 0800

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Program

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Interfacing of DAC 0800

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Interfacing of DAC 0800

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Interfacing of DAC 0800 Bipolar Operation

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Interfacing of DAC 0800 Bipolar Operation

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Programmable Interrupt Controller IC 8259

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Pin Diagram of IC 8259

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Schematic Pin Diagram of IC 8259

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Functional Block Diagram of IC 8259

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Interfacing with Microprocessor

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Initialization Command Word 1

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Initialization Command Word 2

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Initialization Command Word 3

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Initialization Command Word 3

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Initialization Command Word 4

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Initialization Sequence

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FULLY NESTED MODE

• It is a default mode of 8259 after initialization.

• IR0 – High Priority

• IR7 – Lowest Priority

• When the interrupt is acknowledged, it set thecorresponding ISR bit.

• This bit will inhibit all interrupts of the same orlower level, however it will accept highestpriority interrupt request.

• ISR will remain set until an EOI command issuedby microprocessor.

• But if AEOI bit is set, the bit in the ISR resets.JCT College of Engineering and Technology,

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SPECIAL FULLY NESTED MODE

• In FNM, on the acknowledgement of an interrupt,further interrupts from the same level is disabled.

• Consider large system – cascading method used –interrupt level within each slave to be considered.

• Interrupt request to Slave – it places the interruptrequest to Master.

• Further interrupts to the slave will case the slaveto place request to the master on the same input tothe master, but these will not be recognizedbecause further interrupts on the same input levelare disabled by the Master.

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• The SFNM is used to avoid this problem. It is set the

ICW4 during Initialization.

• Similar to FNM except the following.

– Interrupt Request from slave is serviced

– Slave allowed further request of a higher priority

than the request currently being serviced.

– Interrupt are recognize by the Master and it

initiates Interrupt request.

• Before existing from the service routine , a non

specific EOI must sent to the slave and its ISR

must be read to determine if it was only interrupt

to the slave

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Keyboard and Display Interfacing IC 8279

(Features)

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Pin Diagram of IC 8279

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Pin Diagram of IC 8279

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Operating Mode of IC 8279

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Operating Mode of IC 8279

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Operating Mode of IC 8279

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Display Mode of IC 8279

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Interfacing of 8279 with Microprocessor

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Interfacing of Key Board

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Interfacing of Display

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