Pheripheral interface
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Transcript of Pheripheral interface
UNIT – III
PERIPHERAL INTERFACE IC’S
PREPARED BY,MANIKANDAN SAP / EEEJCT CET
JCT College of Engineering and Technology, Coimbatore
8253/8254 Modes of Operation
JCT College of Engineering and Technology, Coimbatore
Mode 0: Interrupt on Terminal Count
JCT College of Engineering and Technology, Coimbatore
Mode 1: Programmable One Shot
JCT College of Engineering and Technology, Coimbatore
Mode 2: Rate Generator
JCT College of Engineering and Technology, Coimbatore
Mode 3: Square Wave Generator
JCT College of Engineering and Technology, Coimbatore
Mode 4: Soft Triggered Strobe
JCT College of Engineering and Technology, Coimbatore
Mode 5: Hardware Triggered Strobe
JCT College of Engineering and Technology, Coimbatore
Analog to Digital Converter
Types:
Counting Type A/D Converter
Successive Approximation ADC
Parallel or Flash Converter
JCT College of Engineering and Technology, Coimbatore
Specification of ADC
JCT College of Engineering and Technology, Coimbatore
Schematic Diagram of ADC
JCT College of Engineering and Technology, Coimbatore
Logic Diagram of ADC 0800
JCT College of Engineering and Technology, Coimbatore
Interfacing of ADC 0800
JCT College of Engineering and Technology, Coimbatore
Interfacing of ADC 0800 and Multiplexer with 8255
JCT College of Engineering and Technology, Coimbatore
Interfacing of 12 Bit ADC 0800
JCT College of Engineering and Technology, Coimbatore
Digital to Analog Converter
Types: Binary Weighted DAC R – 2R Ladder Circuit
Specification: Resolution Accuracy Offset/Zero Scale Error Linearity Settling Time Temperature Sensitivity
JCT College of Engineering and Technology, Coimbatore
8 Bit DAC 0800
JCT College of Engineering and Technology, Coimbatore
Program
JCT College of Engineering and Technology, Coimbatore
Interfacing of DAC 0800
JCT College of Engineering and Technology, Coimbatore
Interfacing of DAC 0800
JCT College of Engineering and Technology, Coimbatore
Interfacing of DAC 0800 Bipolar Operation
JCT College of Engineering and Technology, Coimbatore
Interfacing of DAC 0800 Bipolar Operation
JCT College of Engineering and Technology, Coimbatore
Programmable Interrupt Controller IC 8259
JCT College of Engineering and Technology, Coimbatore
Pin Diagram of IC 8259
JCT College of Engineering and Technology, Coimbatore
Schematic Pin Diagram of IC 8259
JCT College of Engineering and Technology, Coimbatore
Functional Block Diagram of IC 8259
JCT College of Engineering and Technology, Coimbatore
Interfacing with Microprocessor
JCT College of Engineering and Technology, Coimbatore
Initialization Command Word 1
JCT College of Engineering and Technology, Coimbatore
Initialization Command Word 2
JCT College of Engineering and Technology, Coimbatore
Initialization Command Word 3
JCT College of Engineering and Technology, Coimbatore
Initialization Command Word 3
JCT College of Engineering and Technology, Coimbatore
Initialization Command Word 4
JCT College of Engineering and Technology, Coimbatore
Initialization Sequence
JCT College of Engineering and Technology, Coimbatore
FULLY NESTED MODE
• It is a default mode of 8259 after initialization.
• IR0 – High Priority
• IR7 – Lowest Priority
• When the interrupt is acknowledged, it set thecorresponding ISR bit.
• This bit will inhibit all interrupts of the same orlower level, however it will accept highestpriority interrupt request.
• ISR will remain set until an EOI command issuedby microprocessor.
• But if AEOI bit is set, the bit in the ISR resets.JCT College of Engineering and Technology,
Coimbatore
SPECIAL FULLY NESTED MODE
• In FNM, on the acknowledgement of an interrupt,further interrupts from the same level is disabled.
• Consider large system – cascading method used –interrupt level within each slave to be considered.
• Interrupt request to Slave – it places the interruptrequest to Master.
• Further interrupts to the slave will case the slaveto place request to the master on the same input tothe master, but these will not be recognizedbecause further interrupts on the same input levelare disabled by the Master.
JCT College of Engineering and Technology, Coimbatore
• The SFNM is used to avoid this problem. It is set the
ICW4 during Initialization.
• Similar to FNM except the following.
– Interrupt Request from slave is serviced
– Slave allowed further request of a higher priority
than the request currently being serviced.
– Interrupt are recognize by the Master and it
initiates Interrupt request.
• Before existing from the service routine , a non
specific EOI must sent to the slave and its ISR
must be read to determine if it was only interrupt
to the slave
JCT College of Engineering and Technology, Coimbatore
Keyboard and Display Interfacing IC 8279
(Features)
JCT College of Engineering and Technology, Coimbatore
Pin Diagram of IC 8279
JCT College of Engineering and Technology, Coimbatore
Pin Diagram of IC 8279
JCT College of Engineering and Technology, Coimbatore
Operating Mode of IC 8279
JCT College of Engineering and Technology, Coimbatore
Operating Mode of IC 8279
JCT College of Engineering and Technology, Coimbatore
Operating Mode of IC 8279
JCT College of Engineering and Technology, Coimbatore
Display Mode of IC 8279
JCT College of Engineering and Technology, Coimbatore
Interfacing of 8279 with Microprocessor
JCT College of Engineering and Technology, Coimbatore
Interfacing of Key Board
JCT College of Engineering and Technology, Coimbatore
Interfacing of Display
JCT College of Engineering and Technology, Coimbatore