phelma reliability rev2009chamilo2.grenet.fr/.../phelma_reliability_rev2010_-_part_1.pdf · –...

WAFER-LEVEL RELIABILITY

Emmanuel VINCENT

[email protected]

2

Acknowledgments� Some figures/slides presented in this course have been taken from

works of– STMicroelectronics

� S. Bruyère, C. Guérin, J. -P. Carrère, M. Denais, V. Girault, F. Giroux, R. Gonella, V. Huard, D. Lopez, F. Monsieur, D. Ney, C. R. Parthasarathy, N. Revil, G. Ribes, M. Rien, D. Roy

– Philips� X. Federspiel

– Freescale� P. Abramowitz� J. W. Miller

– IBM� D. J. DiMaria, T. D. Sullivan

– IMEC� R. Degraeve, G. Groeseneken

– ISEN-Toulon/L2MP� Alain Bravaix

– Sandia Technologies� D. Pierce, E. Snyder

– Sematech� G. Bersuker

– Texas Instruments� B. Hunter, T. Rost, J. McPherson

– Stanford University� J. C. Bravman, J. C. Doan

– JEDEC

3

INTRODUCTION

Objectives of this Course

� Reliability context in microelectronics industry

� Recall of reliability basics : reliability analysis basic concepts & tools for microelectronics reliability

� Focus on the main failure modes in modern IC's– Phenomenological and physical description– Test methodologies and structures– Wafer-Level Reliability strategy - most adapted

methodologies and structures for WLR testing

4

OUTLINE

Introduction and Generalities

� Introduction

� Basics reliability concepts

� What is Wafer-Level Reliability ?� Wafer-level failure modes� Wafer-Level Reliability evaluation needs

5

INTRODUCTION

What Is Reliability ?

� Any good, e.g. Integrated Circuits, supplied to customershave to meet adequate functionality performances and adequate reliability

� Reliability – Ability of a component to fullfil its function during all the

application life in a given environment– Probability that a component meets a determined mission, in a

determined environment, for a determined period of time

6

Of course, our chip willlast more than 10 yearsat normal use conditions

10 years ?!?!Damned ! How can we be

sure about that?

INTRODUCTION

What Is a Reliability Engineer ?

7

BASICS RELIABILITY CONCEPTS

Bath Tub Shape Curve

λ(t)

Infant Mortality Wearout

time

USEFUL LIFE

Steady state

WLR

� That’s life…

� WLR = Wafer-Level Reliability

8

INTRODUCTION

Why is IC Reliability so Critical ?

– Accelerating field in a CRT tube ~ 2.5kV/25cm = 0.1kV/cm In ICs : more than 2000X more !

� Aggressive interconnections– Operating current density in the metal lines/vias J ~ 2-10 mA/µm²(0.2 MA/cm²)

5.0

4.7

3.3

2.8

Vertical electricField (MV/cm)

2392.5V6nm0.25µm

2643.3V7nm0.35µm

1853.3V10nm0.5µm

2555.0V17.5nm0.7µm

Lateral electricfield (kV/cm)

Supplyvoltage

Oxidethickness

Technologynode

� Aggressive devices

– In the wires in this room, J ~ 100A/cm²In ICs : more than 2000X more !

9

INTRODUCTION

Why is IC Reliability so Critical ? (cont’d)

� Very various applications with potential extremenvironmental conditions

� Temperature– From high (150°C) down to low temperature (-40°C) accor ding to

the region of use + IC self-heating

� Humidity– From 100% relative humidity in tropical countries down to 0% in

deserts

� Others : Radiations, shocks, …

10

INTRODUCTION

The Different IC Reliability Aspects

� Specific reliability approach– Design-In Reliability– Wafer-Level Reliability– Package Reliability

� Reliability interactions approach– Wafer/Package– Process/Design– Design/Package– Wafer/Design/package

IC = DESIGN + WAFER + PACKAGE

11

OUTLINE

Introduction and Generalities

� Introduction� Basics reliability concepts

� Definitions� Distribution models

12


Probabilities

Number of good parts at time tNumber of good parts at t=0

� Reliability function R(t)– Survival rate at time t : R(t) =

� Cumulative failure probability function F(t)– Probability that a good part at t=0 is defective at t : F(t) = 1 - R(t)

dF(t)dt

� Failure probability density function f(t)– Probability that a good part at t is defective at t+dt : f(t) =

f(t)1-F(t)

� Failure rate λ(t)– Failure probability between t and t+dt for a good part at t : λ(t) =

� MTTF– Mean Time To Failure

13


Definitions

� Intrinsic defects– Defects inherent to the materials and/or process

Examples :� Defects related to the as-grown or as-deposited material properties� Think about : Any material on the earth degrades...

=> Associated to wearout phenomena

� Extrinsic defects– Defects originated by external causes to the process

Examples :� Particules, impurities� Structural weaknesses, pinholes

=>Associated to infant mortality, early failures

14


Distribution Functions

ln(µ) ln(x)ln(µ) ln(x)

σσ

µ x

σσ

µ x

Normalµ xµ x

Log-Normal

ln(x)

Weibull

15


Distribution Models

� Normal distribution

– Cumulative failure probabilityF(x,µ,σ) :

⌠⌠⌠⌠⌡⌡⌡⌡

e

ζ ζ ζ ζ −−−− µµµµσσσσ

12

2

−−−−∞∞∞∞

x

1σ σ σ σ √√√√2π2π2π2π

dζζζζ

% C

umul

ativ

e F

ailu

re

99

90

75

50

25

10

1

Parameter x− µ : mean– σ : standard deviation

16

% C

umul

ativ

e F

ailu

re

99

90

75

25

10

1

Parameter log(t)

50


Distribution Models (cont’d)

� Log-normal distribution

– Cumulative failure probabilityF(t,µ,σ) :

−−−−∞∞∞∞

⌠⌠⌠⌠⌡⌡⌡⌡

e

ln (ζ(ζ(ζ(ζ) ) ) ) −−−− ln (µ(µ(µ(µ))))σσσσ

12

2t

1σ σ σ σ √√√√2π2π2π2π

dζζζζζζζζ

− µ : mean– σ : standard deviation

� Mainly used for –Electromigration, stress voiding–Hot-Carrier injection...

17

% C

umul

ativ

e F

ailu

re

99

90

75

25

10

1

Parameter log(t)

5

50

ββββ


Distribution Models (cont’d)

� Weibull distribution– Cumulative failure probability

F(t,t63%,β) :

1 - e t63%

ββββt

– t63% : t at 63%− β : shape parameter

�β = 1 : λ(t) = constant�β < 1 : λ(t) ��β > 1 : λ(t) �

� Mainly used for– Oxide breakdown

18

INTRODUCTION

Reliability Exercise

– Determine the number of cycles that a paper clip canbe bent before breaking for various angles

– Determine median lifetime and standard deviation– Identily relevant repartition function– Characterize acceleration and assume fatigue model– Predict a lifetime

1 cycle = bent up & back

� Paper Clip Fatigue

19

INTRODUCTION

Reliability Exercise : Practical details

� 3 groups

– Team 1 : x persons => 135°bending

– Team 2 : 2x persons => 90°bending

– Team 3 : 5x persons => 45°bending

Carrying the experiments and reporting the results

20

INTRODUCTION

What Is Wafer-Level Reliability ?

� Characterization of each identified failure mode (occurrence, acceleration…)…

� Wafer-Level Reliability– Reliability associated to the wafer's modules– On the contrary to product reliability, wafer-level

reliability is an analytical approach :

� … To determine/predict lifetime associatedto each failure mode

21

INTRODUCTION

Reliability Criteria

� Reliability depends on environment conditions– Electrical stress (current, voltage)– Temperature– Humidity– Radiations– …

� And required lifetime– Different requirements according the market place

� Standard : 10 years, but� Telecom applications : 25 years� Mobile applications : 7 years� Computer : less severe…

22

INTRODUCTION

Reliability Approach

– Provide demonstration of the (10 year) reliability of a given process

� Technology reliability evaluation needs to

– In the context of an industrial activity in particularserving the consumer marketplace

� No way to wait for 10 years to demonstrate the reliability� Necessity to accelerate the wear-out phenomena

– Increasing the environment conditions (temperature, stress voltage…)

– Valid approach if same phenomena are triggered… if test structures are relevant…

� Necessity to extrapolate the reliability at nominal conditions from the accelerated experimental data throughreliability prediction models

23

INTRODUCTION

Wafer-Level Reliability Evaluation Needs

Process Reliability QualificationEvaluate and assess that reliability performances are in line

with internal and external customer expectations before release in production

� Reliability monitoring (WLRC)–Process drift–Accidental events– ...

............Development ....…...Industrialization ...Production

� Reliability evaluation–Process (equipment, material, recipe...)

–Device architecture– ...

24

INTRODUCTION

Wafer-Level Failure Modes

Metal 3:Al-Cu ILD3

ILD2

W plugs

Metal 3:Al-Cu

Oxide integrity Hot-carrier injection

Electromigration

Plasma-induceddamage

Mobile ion contamination

Latch-upESD

Corrosion Delamination Stress voiding

Negative BiasTemp Instabilities

25

OUTLINE

Brief Dielectric Physics Basics

� The MOS structure

� Charges in SiO2

� Conduction in SiO2

26

BRIEF DIELECTRIC PHYSICS BASICS

Oxide Atomic Structure

� Bonds are strained and weakened (structural defects)

Tox

27


SiO2 Band Energy Structure

Si9eV

ε=3.43.2eV

4.7eV

Si

SiO2

• SiO2 is amorphous (no periodical structure) but band gap approximation works well (8.9eV).

28


MOS Structure Band Diagram

p-SiSiO2Gate

Eg,Si

Eg,SiO2

Vox

φφφφBVG

EF

EF

Ene

rgy/

Pot

entia

l

X-axis

Barrier

29


Oxide Defects – Oxide Traps

� Bond broken– Si-O– Si-Si– Si-H

� Ability to capture– Negative charge (electron)– Positive charge (hole)

30

SiSiO 2Gate


Charges in the Fresh Si/SiO 2 System

+

++

+

++

+

+

+

++

++

+

++

+

+

+

++

++

+

+

++

+

+

+

++

++

+

++

+

+

+

+++

� Fixed charges (+)– Si, N atoms excess at the interfaces +

+

+

+

+

� Mobile charges (+)– Impurity contamination (Na+, K+)

during the process

XXXXXXXXXXXX

� Interface state charges (+/-)– Perturbation of the Si crystalline

structure at the interface(s)

-

+

-

-

-

-

+

+

+

� Bulk oxide trapped charges (+/-)– Defects in the as-grown oxide layer– Process-induced defects

� 4 types of charges :

31

C

V

VFB =


Charges’ Effect on the MOS Parameters

φφφφMS

Ideal C(V)

QFCox

-

Fixed charges

1Cox

xtox

tox⌠⌠⌠⌠⌡⌡⌡⌡

0

- ρρρρOT(x) dx

Bulk oxide trapped charges

⌠⌠⌠⌠⌡⌡⌡⌡

1

Cox

xtox

tox

0

- ρρρρM(x) dx

Mobile charges

QIT(φφφφs)Cox

-

Interface state charges

32


Conduction through the Si/SiO 2 System

Hot-Carrier injectione-

Si SiO2 Si

Thick oxide or high field

Fowler-Nordheimtunneling

e-

HC injectione-

Si SiO2 Si

Thin oxide or low field

Direct tunnelinge-

33


Intrinsic Tunneling Current

� In spite of these defects SiO2 is the best insulator available for microelectronics.

� Though insulating, the gate oxide shows an increased direct tunneling probability when it is getting thinner.

Poly-Si

Si substrate

Gat

eox

ide

1.E-13

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

1.E+01

1.E+01

0 1 2 3 4 5 6Vg (V)

Gat

ecu

rren

t(A

)

Oxidethickness

32Å

26Å

16Å

Tox

34


Fowler-Nordheim Injection

� Classical injection : Fowler-Nordheim injection

JFN = A Eox ² exp BEox

• Eox is the oxide electric field

• A and B depend on the Si/SiO2

energy barrier height φB

0 4 8 12 16E (MV/cm)

1E-91E-81E-71E-61E-51E-41E-31E-21E-1

1E+0

J (

A/c

m²)

0.06 0.09 0.12 0.15

1/E (cm/MV)

1E-26

1E-25

1E-24

1E-23

1E-22

1E-21

1E-20

1E-19

1E-18

1E-17

J/E

² (

A/V

²)

35

OUTLINE

Mobile Ion Contamination

� Generalities

� Ion transport model

� Test methodologies

� WLR strategy

36

MOBILE ION CONTAMINATION

Generalities� Mobile ion contamination : one of the most serious issues

encountered in early MOS development– Negative shift of MOS flat-band voltage w.r.t. theoretical– Large flat-band voltage instabilities under bias and temperature

� Positive mobile ionic contamination drift - likely candidate– Electrical measurements consistent with positive charge drift in oxide– Alkali ion drift in crystalline silica (quartz) known for many years– Positive mobile ionic contaminants abundant in the environment

� Sodium Na+� Potassium K+� (Lithium Li+)

� Product reliability concern :– Mobile ion drift under bias/temperature– MOS parameter shift ⇒ IddQ/Burn-In fails

early oxide breakdown

37


MOS Instabilities

� Mobile ions can migrate under bias and high temperature, leading to serious MOS device instabilities

t=0VFB

Gat

e

Sili

con

+

+

+

+

++

+

Eox

Field & TemperatureIons are pushed

towards one interface

Gat

e

Sili

con

++

+

++

++

Eox

+

t1

∆∆∆∆VFB = -QM/Cox

Gat

e

Sili

con

+

+

+

+

++

+

Eox

38


Strategies to Reduce Mobile Ion Contamination� Avoid contaminant sources : rigorous clean concept

– Improved purity of chemicals, gas– Improved equipments (automation) and cleaning techniques– Cleaner processes (oxidation furnaces, metallization...)

� Neutralize contaminants : Chlorine introduction– Chlorine introduced during oxide growth can help to trap Na+ ions

at the Si/SiO2 interface– Trade-off not obvious to find

� Trap contaminants : mobile ion gettering– Phosphorous doped Silicon Glass (PSG)

Gettering efficiency attributed to� P2O5 more likely � (P2O)

39


Ion Transport Model : observations� Ions do not leave the oxide

– Si/SiO2 interfaces = blocking layers for ion motion

� Mobile ions may theoretically be either negative (ion motion in the opposite direction)

– Gettering effect indicates that associated charges are positive charges

0 0.2 0.4 0.6 0.8 10E+0

5E+11

1E+12

2E+12

2E+12

3E+12

3E+12

160°C140°C

120°C

100°C

80°C

time 1/2 (hour 1/2)

N

(cm

)

M-2 tox = 200nm

VG = 10V

0 10 20 30 40 500

4

8

12

16

20

246.5MV/cm

6MV/cm5.5MV/cm

5MV/cm

4.5MV/cm

4MV/cm

time 1/2 (hour 1/2)

V

shi

ft (V

)F

B

T = 25°C

40


Ion Transport Model

GATE SiO 2 Si

E

E0

Ed

++++

++

+

� Ions are thermallyexcited out of deepinterface traps

++

� Ions are retrappedat opposite interface

� Thermal detrapping from interface traps (limiting phenomenon)� Drift and diffusion through SiO2

+

� Ions drift throughshallow traps inbulk SiO2

++

41


Na+ and K + Mobility in SiO 2

� Ion mobility in the SiO2 :

µ(T) = µ0 exp(-Ed/kT)– Ed depth of the bulk oxide trap

�Na+ :– µ0 = 1.0 cm2.V-1.sec-1

– Ed = 0.66eV

�K+ :– µ0 = 0.03 cm2.V-1.sec-1

– Ed = 1.09eV

250 300 350 400 450 500 550 600

Temperature (K)

1E-5

1E-4

1E-3

1E-2

1E-1

1E+0

1E+1

1E+2

Tra

nsit

time

(sec

)

K+

Na+

tox = 10nmEox = 1MV/cm

42


Thermal Bias Stress (TBS)� Structures

– Active/parasitic MOS transistors ⇒ VTH

– Active/parasitic MOS capacitors ⇒ VFB

�Procedure

E

T

t

t

-3E-12

0 -0.5 -1 -1.5 -2 -2.5Gate voltage (V)

E-3

E-4

E-5

E-6

E-7

E-8

E-9

Dra

in c

urre

nt (

A)

E-10

E-11

ox

– Heat the wafer (T ~ 200°C)

– Apply VG+ during some minutes

(Eox ~ 1-2MV/cm, 5-30min typical time)

– Cool down the wafer under bias

– Heat the wafer– Apply VG

- during some minutes

– Cool down under bias, then remove it

⇒ NM = Cox . ∆∆∆∆VFB / q

+FBV

– Measure VFB+ /VTH

+

+

FB -V

– Measure VFB- /VTH

-

-– Remove bias

43


Triangular Voltage Sweep (TVS)

� Test structures– Large active/parasitic

MOS capacitors– Perimeter emphasis

� Procedure

Eox

T

t

tI

t

– Heat the wafer (~ 300°C)

– Bias temperature stress• Collect all ions at one interface

– Constant voltage ramp ~ 10mV/s• As field changes, ions drift

– Displacement current/capacitancemeasurement (I=C.dV/dt ∝ C)

� NM ∝ area under the I peak– Possibility to discriminate the types of contaminants (≠ µ)

Na+K+

44


Thermally Stimulated Ionic Current� Test structures

– Large active/parasiticMOS capacitors

– Perimeter emphasis

� Procedure

Eox

T

t

tI

tNa+ K+

– Thermal bias stress– Cool down the wafer (T ~ -20°C)

– To deeply trap the ions

– Constant temp. ramp ~ 0.5°C/s

– As temp. increases, ions aredetrapped

– Displacement current measure

� NM ∝ area under the I peak– Possibility to discriminate the types of contaminants (≠ Ea)

45


WLR Strategy

� Self-heating structures ("micro-chuck" approach)– Joule heating of polysilicon to heat the oxide

� Advantage : no need of temperature controlled chuck with associated heat/cool time constants

� Drawback : temperature uniformity across the oxide layer not warrantied

⇒⇒⇒⇒ May be a relative quantification of the mobile ioncontamination

Process Development

Process Reliability Qualification WLRC

TVS (TBS) TVS (TBS)TBS on

self-heating structures

46

OUTLINE

Gate Oxide Integrity

� Oxide degradation

� Oxide breakdown models

� Oxide breakdown acceleration

� Test methodologies & structures

� WLR strategy

47

OXIDE INTEGRITY

How to Age a MOS structure

� Carrier injection into the Si/SiO2 system may degrade the MOS structure

– High electric field and/or energetic carriers– Carriers fill pre-existing traps– Carriers generate defects in the Si/SiO2 system which behave as

traps for the incident carriers

=> Even at low electric fields, oxide degrades, but time-dependent

� Needs to accelerate the degradation in order to be able to observe degradation/failure

– Use of high current/voltage/temperature– Use of high-efficiency injection mechanisms

48

OXIDE INTEGRITY

Stress-Induced Defects

� Interface traps – Located near the Si/SiO2 interface– Can exchange charge with Si substrate within a time constant

(picoseconds - hours)– Effect on MOS transconductance, leakage current, noise

� Bulk oxide traps– Distributed across the whole oxide thickness– Effect on the MOS parameters depends on the density and

centroid w.r.t. the Si/SiO2 interface– Can trap carriers– No significant exchange with Si substrate (time constant → ∞)– No significant exchange with SiO2 (deep traps)– Effect on the long term stability (MOS parameters' shift,

device failure...)

49

OXIDE INTEGRITY

Oxide Degradation Mechanisms

1E-2 1E-1 1E+0 1E+1 1E+2-150

-120

-90

-60

-30

0

Qinj (C/cm²)

∆∆ ∆∆Q

(n

C/c

m²)

ox

1E-2 1E-1 1E+0 1E+1 1E+20.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

Qinj (C/cm²)

(×× ××10

eV

/c

m )

D it

11-1

2

�Trap creation�Dominant bulk oxide electron trapping

�Interface state creation

50

Si SiO2 Si

e-

OXIDE INTEGRITY

Oxide Degradation Mechanisms (cont’d)

� For thin oxides :– Stress-Induced Leakage Currents

(SILC) Conduction electrons use bulkoxide stress-induced traps as"stepping stones" to reach the anode

0 1 2 3 4 5 6 7

Gate Voltage (V)

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

Gat

e cu

rren

t den

sity

(A

/cm

²)

stress

51

OXIDE INTEGRITY

Oxide Breakdown : What is it ?

� Ultimate stage of the oxide degradation– Sudden and irreversible loss of the SiO2 insulator properties– Local (unscalable leakage current)

1E-14

1E-12

1E-10

1E-8

1E-6

1E-4

1E-2

1E+0

I (A

mps

)

0 2 4 6 8 10E (MV/cm)

Fowler-Nordheim

Breakdown

Conduction splot observed with Light Emission Microscopy

52

OXIDE INTEGRITY

Soft-Breakdown : What is it ? A

B

C

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

0 20 40 60 80

Stress time (s)

Ig(t

) - Ig

(0)

& S

tdev

(t) (

A) Ig(t) - Ig(0)

Standard Deviation

Continuous degradation

B.Currentincrease

A.Noise

C. BD isreached

� Occurs for oxides < ~ 2.5nm

53

== initial current

OXIDE INTEGRITY

Wear-Out Current

+ wear-out current

Wear-out currentBD

Time (s)

Cur

rent

s (A

)

1E -07

1E -06

1E -05

1E -04

1E -03

1 10 100

measured current

BD

measured Current

54

Ig

tI1

I2

OXIDE INTEGRITY

Hard vs. Soft Breakdown

I2

Ig

tI1

� Progressivity ~ instantaneous� Physical breakdown event

leads to catastrophic fail in circuit

� Long progressivity� Even with a soft-breakdown

event the circuit cancontinue to operate (no instantaneous failure)

� �Lifetime extension

55

OXIDE INTEGRITY

Main Degradation ModelsOxide degradation driven by...

electron flow through the oxide... local electric field...

...releasing H atoms drifting towards the

cathode...

...creating hot holes back tunneling towards

the cathode...

...breaking weak bonds by dipolar coupling...

creating defects

56

Cathode

Anode

Cluster formation

Cathode

Anode

OXIDE INTEGRITY

Percolation Model [e- flow induced BD]Trap creation

WEAR-OUT

Anode

Cathode

BREAKDOWN=

57

OXIDE INTEGRITY

Hydrogen Location

�Hydrogen is present everywhere in many process steps.�Hydrogen is mainly localized at Si-SiO2 interface to passivate dangling bonds induced by mismatch between both crystalline and amorphous materials.

O

Si

H

58

Si

SiO2

Si

e-electron heating

2eV

H hydrogen release

• These energetic (3eV+2eV) carriers interact with Hydrogen atoms which may be released from the anode/ SiO2

interface

H

hydrogen-induceddamage

• These atoms create oxide/ interface defects

• Breakdown occurs as soon as a critical number of defects is reached

electron injection

• The electrons enter the oxide conduction band by Fowler-Nordheimtunneling mechanism, drift towards the anode gaining energy

H

hydrogen diffusion• These atoms drift towards the cathode

OXIDE INTEGRITY

Hydrogen Release Model

59

OXIDE INTEGRITY

Hydrogen Desorption Yield vs Defect Generation Rate

� Hydrogen desorption Yield induced by STM shows a behavior similar to Pgen

� Energy thresholds are comparable

1E-07

1E-04

1E-01

1E+02

1E+05

1 2 3 4 5 6 7 8 9 10

Gate Voltage (V)

Pge

n (a

.u)

60

SiO2

OXIDE INTEGRITY

Anode Hole Injection Model

� These holes create oxide defects which behaveas neutral electron traps

� Electrons enter the oxide conduction band by Fowler-Nordheim tunneling mechanism, drift towards the anode gaining energy

� A fraction of these incident electrons canbe thermalized giving their energy to deepvalence band electrons which are promotedto the anode conduction band and creatinghot-holes which can tunnel back into the oxide

61

OXIDE INTEGRITY

Anode Hole Injection Model (cont’d)

1E15 1E16 1E17 1E181E17

1E18

1E19

Hole fluence

Critical trap density

Critical holefluenceE

lect

ron

trap

den

sity

(cm

-3)

1E15 1E16 1E17 1E181E17

1E18

1E19

Hole fluence (cm -2)

Critical holefluence

– a critical hole fluence is reached

Critical trap density

– a critical neutral trap density is reached

� Oxide breakdown occurs as soon as

62

OXIDE INTEGRITY

Thermochemical Model

� Degradation due to interaction of local electric field with weak bonds in the oxide, inducing dipolar coupling of defects

� Breakdown = bond breakage due to electric field & thermal excitation

Oxygen vacancy

+++

Bond breakage

120°-180°120°-180°

Thetrahedral SiO2

63

OXIDE INTEGRITY

Breakdown Electric Field Acceleration

1E+1534510 8 620

E (MV/cm)

1E+0

1E+3

1E+6

1E+9

1E+12

Tim

e to

bre

akdo

wn

(sec

)

0.05 0.1 0.15 0.2 0.25 0.3 0.35

1/E (cm/MV)

1/E

E

� Anode hole injection model :– Linked to F-N injection – "1/E" model : tBD ∝∝∝∝ exp(G/Eox)– Prevails at high fields

� Thermochemical model :– "E" model : tBD ∝∝∝∝ exp(-γ.γ.γ.γ.Eox)– Prevails at low fields

�"E" model is largely adoptedby reliability engineers

– Nominal conditions = low fields– Pessimistic model⇒ worst-case analysis

64

OXIDE INTEGRITY

New Tendencies for Advanced Nodes

� Experiments ataccelerated stress conditions (T,V,(J))

VDDnom

1.E-03

1.E-01

1.E+01

1.E+03

1.E+05

1.E+07

1.E+09

1 1.5 2 2.5 3.5 4

Gate Voltage (V)

Tim

e to

Bre

akdo

wn

50%

(s)

« E » « V^n »

« V^n »« E »16A

10 y30 mnPch

� Prediction throughextrapolation modelat operating conditions

� Model is crucial : great impact !

– Impossible to verifyat nominal stress conditions (too long)

– Need to get the conviction that the model applies, facts based(facts = accelerated experimental data + physical understanding)

65

OXIDE INTEGRITY

Power Law Model

� Ultrathin oxides : opportunity to discriminate origin of the oxide degradation phenomena

– Ultrathin oxide : high fields = low voltage� Possibility to discriminate between carrier energy and electric field

– Demonstrated on ultrathin oxides (< 2nm)

� Power law model :– Linked to hydrogen release model

– Power law model : tBD ∝∝∝∝ V-n

– n ~ 40– Make nowodays technologies usable (i.e. demonstrated as reliable)

66

OXIDE INTEGRITY

Vibrational Excitation

� Hydrogen release if Si-H bond is excited by Edes/σexcitations in a time below the relaxation time τ

Bonding Energy (Edes)

Energy quantum (σ) = bond stretching

Quantum number= Edes/σ

Si H

W =(τrelax)-1

67

OXIDE INTEGRITY

Oxide Breakdown Thermal Activation

� Time to breakdown dependson temperature through aclassical Arrhenius law

tBD = t0 . exp(-E A/kT)

� Activation energy depends onelectric field

– 0.3-0.5eV at high fields

– higher activation energy at low fields2.6 2.8 3 3.2 3.4 3.6 3.8

1000/T (1/K)

1E+1

1E+2

1E+3

1E+4

1E+5

Tim

e to

bre

akdo

wn

(s)

68

OXIDE INTEGRITY

Probability Concept of Area Scaling� Defect density DA

� Oxide area A = N . δA� Probability that an δA area capacitor does not fail is

1-FδA = (1-DA . δA)� Probability that an A area capacitor does not fail is

1-FA = (1 - DA . δA)N → exp(-DA . A)

1 - FA1 = (1 - FA2)A1/A2

tbdA1 = tbd

A2 (A2/A1)1/beta

δA

� Capacitor with large area has greater probability of containing a breakdown site⇒ Larger TBD for smaller oxide capacitor

69

1E+0 1E+2 1E+4 1E+6 1E+8 1E+10

Time to breakdown (sec)

-6

-5

-4

-3

-2

-1

0

1

2

ln(-

ln(1

-F))

99

90

63

25

10

5

1

%

OXIDE INTEGRITY

Oxide Breakdown Data ProcessingWeibull repartition

function : ln(-ln(1-F)),

F = cumulative failureprobability

V2,A1V1,A1

Weibull slope related

to the critical number

of defects to trigger

oxide breakdown

ββββ

Electric field (and T°)

accelerations :

Horizontal shift

Vnom,A1

Vnom,Achip

Area dependence :

Vertical shift of

ln(A1/A2)

70

-1.E+01

-8.E+00

-6.E+00

-4.E+00

-2.E+00

0.E+00

2.E+00

0.01 0.1 1 10 100 1000

TBD(s)

% C

um. F

ail (

Wei

bull)

7000um

1m

OXIDE INTEGRITY

But It Is Not So Simple…

� Intrinsic – Same Weibull slope on

7000um/1m structure– Same V-acceleration

� Extrinsic– Higher level on 1m structure

71

OXIDE INTEGRITY

Test MethodologiesI

t

Constant Voltage Stress

tbd

V

t

Constant Current Stress

tbd

Qbd = J(t).dt⌠⌠⌠⌠

⌡⌡⌡⌡0

tbd

Vbd

I

V(t)

Ramp Voltage Stress

V(t)=R.t

V

I(t)

Ramp Current Stress

Ibd

I(t)=J o exp(R.t)

72

OXIDE INTEGRITY

Main Breakdown Relevant Parameters

� Time to breakdown tBD (sec)– Constant Voltage Stress, Constant Current Stress– (Linear Ramp Voltage Stress, Exponential Ramp Current Stress)

� Charge to breakdown QBD (C/cm²)– Constant Voltage Stress, Constant Current Stress– Linear Ramp Voltage Stress, Exponential Ramp Current Stress

� Voltage/electric field to breakdown VBD (V)/EBD (MV/cm)– Linear Ramp Voltage Stress– (Exponential Ramp Current Stress)

� Current/current density to breakdown IBD (A)/JBD (A/cm²)– Exponential Ramp Current Stress– (Linear Ramp Voltage Stress)

73

OXIDE INTEGRITY

Test Structures

plate

poly fingers

active fingers

Field oxide islands Active islands

74

OXIDE INTEGRITY

WLR Strategy� Classical oxide breakdown-related reliability

specs :– Lifetime > 10 years at VDDmax, max temperature

(125°C), 0.01% cumulative failure for a 0.1cm² oxide area (circuit equivalent)

Process Development

Process Reliability Qualification WLRC

LRVS (E BD)CVS (TDDB)

LRVS (E BD)CVS (TDDB)

LRVS (E BD)ERCS (QBD)CCS (QBD)

75

OUTLINE

Hot-Carrier Injection

� Physics of the degradation

� Impact on the MOS parameters

� Drift-time extrapolation

� Main dependencies

� Dynamic hot-carrier degradation

� WLR strategy

76

HOT-CARRIER DEGRADATION

Origin of the Hot-Carrier Generation

Em = ( Vd - Vdsat ) / l

x

y

E

77


What is Hot-Carrier Degradation ?

� Hot-carrier degradation = result of the physical damage induced by the injection of energetic ("hot") carriers (electrons and/or holes) from the channel into the gate oxide

VG

VD

IB

78


Hot-Carrier Monitors� Hot-Carrier degradation conditionned

by 2 processes– Hot-Carrier generation

– Hot-Carrier injection

� Gate current (injection monitor) not systematically measurable

� Substrate current and multiplication coefficient (IB/IS) : key first order monitors for thehot-carrier generation (impact ionization)

0 0.5 1 1.5 2 2.5 3

Gate voltage (V)

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

1E-2

Sub

stra

tecu

rren

t(A

mps

)

NMOS, 0.25µm

VDS = 3.5V

VDS = 3VVDS = 2.5V

79


Lucky Electron Model

IB = C1 ×××× ID ×××× exp ϕ ϕ ϕ ϕ i

q.λλλλ.Em

IG = C2 ×××× ID ×××× exp ϕ ϕ ϕ ϕ B

q.λλλλ.Em

∆∆∆∆NIT = C3 × × × × × × × × exp × × × × Tstress = C4 × × × × × × × × × × × × Tstress ϕ ϕ ϕ ϕ it

q.λλλλ.Em

ID

W

n ID

W IB

ID

ϕϕϕϕ it /ϕ ϕ ϕ ϕ i n

� Substrate current resulting from impact ionization

� λ = electron mean free path

� ϕ i = critical energy for impact ionization ~ 1.2eV

� Gate current resulting for hot-carrier injection :

�ϕ B = Si/SiO2 energetic barrier height ~ 3.1eV

� Hot-electron-induced interface state generation :

�ϕ it = critical energy for interface state creation ~ 3.6eV

80


Hot-Carrier Injection Consequences

� Hot-Carrier injection– Energetic carriers directed toward the gate oxide will break bonds,

creating defects� at the Si/SiO2 interface (interface states)� in the bulk SiO2

� Consequences on the MOSFET's characteristics– Carrier mobility degradation due to coulombic scattering

� Maximum transconductance shift

– Charge trapping in the bulk oxide� Threshold voltage shift

– Interface state generation� change in the substhreshold characteristics

=> Impact on the MOSFET's currents(linear and saturation regions, Ioff…)

81


What Happens on Nowodays CMOS ?

1

10

100

1000

10000

100000

0 1 2 3 4 5

Vg (V)

TT

F (a

.u)

Vd=3.6V

Vd=4V

Vd=4.4V

W/L=10/0.28

Lucky Electron Modeldoes not explain all HCI phenomena, in particularfor devices operating atlow voltage (below Nit creation energy threshold)

82


Different HCI Degradation Modes (cont’d)

� Regime 1 : low drain current, i.e. high energy (low Vg) and long channel lengths

– In this high energy regime, generated hot holes are attracted to the interface due to negative oxide field (~Vg -Vd) with sufficient energy to break interface Si-H bonds

� Regime 2 : moderate drain current, i.e. moderate energy (Vd) and Vg– In this medium energy regime, most of the carriers induced by impact

ionization have not enough energy to break bonds. Nevertheless, through carrier-carrier interactions (Electron-Electron Scattering), some of them can access higher energies and thus being able to break the bonds

� Regime 3 : At high drain current, i.e. low energy and high Vg– In this low energy regime, carriers do not have enough energy to break a Si-H

bond in a single direct excitation (even though they are promoted to higher energy by EES). Besides, their density increases rapidly with Vg close to the interface. Due to confinement, the electron density close to the interface strongly increases, which favors the low-energy interactions between electrons and bonds by Multiple Vibrational Excitation (MVE)

83


Theory vs. Experiments

1

10

100

1000

10000

100000

0 1 2 3 4 5

Vg (V)

TT

F (a

.u)

Vd=3.6V

Vd=4V

Vd=4.4V

W/L=10/0.28

0.01

0.1

1

10

100

0 1 2 3 4 5Vg (V)

τ (a

.u)

Vd=3.6VVd=3.8VVd=4VVd=4.2VVd=4.4V

W/L=10/0.28

84


Physical Damages Generated byHot-Carrier Injection � NMOS

– VGS ~ VTH

⇒ Hot-hole injection� Interface state generation� Positive charge trapping

– VGS ~ VDS/2-VDS/3⇒ Hot-hole and hot-electron

injection (IBMax)� Interface state generation

– VGS ~ VDS⇒ Hot-electron injection

� Negative charge trapping� Interface state generation

� PMOS– VGS ~ VTH⇒ Hot-electron injection (IGMax)

� Negative charge trapping� Interface state generation

– VGS ~ VDS/2-VDS/3⇒ Hot-hole and hot-electron

injection (IBMax)� Negative charge trapping� Interface state generation

– VGS ~ VDS⇒ Hot-hole injection

� Positive charge trapping� Interface state generation

85

HOT-CARRIER INJECTION

Which Conditions to Have HCI ?

[Affect N & P MOSTs]� Needs carriers in the channel

⇒ HCI occurs if MOST is switched « ON » : Vgs > Vth

� Needs high lateral electric field (Impact Ionization)⇒ HCI is significant if Vds is high

� Needs favorable Vds/Vgs bias configuration to impact ionization and carrier injection towards the gate⇒ HCI effects is more likely maximum at Vgs ~ Vds/2–Vds/3

� HCI is a localized degradation mechanism (near the drain)

86

Drain voltage (V)0 1 2 3 4

0

2.5

5

7.5

10

12.5

Dra

in c

urre

nt (

mA

)

freshstress 1 < stress 2 < stress 3


Impact on the N-Channel MOS Characteristics (I B

Max)

1E+0 1E+1 1E+2 1E+3 1E+4 1E+5

Stress time (s)

1E-4

1E-3

1E-2

1E-1

1E+0

Del

ta X

/ X

0

GM ��

VTH ��

VTH ��

Interface state creation⇒⇒⇒⇒ mobility degradation

87

Fresh

Degraded

0 1 2 3 4 5Gate voltage (V)

E-10

E-09

E-08

E-07

E-06

E-05

E-04

E-03

Dra

in c

urre

nt (

A)

freshaged


Impact on the P-Channel MOS Characteristics (IGMax)

1E+0 1E+1 1E+2 1E+3 1E+4 1E+5

Stress time (s)

1E-4

1E-3

1E-2

1E-1

1E+0

Del

ta X

/ X

0

GM ��

VTH ��

electron trapping⇒⇒⇒⇒ channel shortening

Particularity for technologies above 0.35um

88


Consequence of Stress Non-Uniformity

Stress time (s)

Rel

ativ

e Id

sat d

egra

datio

n (%

) Reverse

Forward

VG

VD

VG

VD

VG

VD

Linear current

Saturation current(Reverse mode)

Saturation current(Forward mode)

89


Drift-Time Extrapolation

∆∆∆∆P/P = A ×××× Tstressn

� Drift-time = time necessaryto reach x% (typically 10%)parameter degradation

� Assuming a power lawbehavior (correlated to interface state generation)

� Extrapolation at x%Stress time (s)

Rel

ativ

e de

grad

atio

n

90


Lifetime Extrapolation Models

ττττ ∝∝∝∝ -m ID

W IB

ID

0.01 0.1 1 10 100

IB/W (µA/µm)

1E+1

1E+3

1E+5

1E+7

1E+9

1E+11

1E+13

tau

(s)

ττττ ∝∝∝∝ -m IB

W

0.24 0.28 0.32 0.36 0.4 0.44

1/VD (1/V)

1E+1

1E+3

1E+5

1E+7

1E+9

1E+11

1E+13

tau

(s)

ττττ ∝∝∝∝ e B/VDS

slope = -3slope = -3

0.1 1 10 100

IB/ID (m)

1E-2

1E+0

1E+2

1E+4

1E+6

1E+8

tau

. ID

/ W

(s.

A/µ

m)

91


Channel Length/Width Dependence� Channel length �⇒ Em �⇒ hot-carrier degradation �

� No significant impact from the channel width

0.4µm

0.28µm

0.22µm0.18µm

Stress time (s)

Rel

ativ

e de

grad

atio

n (%

)

0.11E+0

1E+1

1E+2

1E+3

0.2 0.3 0.4Channel length (µm)

Drif

t-tim

e (s

)

ττττ ∝∝∝∝ p(L)

92


Temperature Effect

� Hot-Carrier degradation isone of the rare degradationphenomena to be worseat low temperature

– T � ⇒ scattering �⇒ less e-/Si or h+/Si collisions⇒ channel electrons can gainmore energy⇒ more impact ionization⇒ more hot-carrier injection ⇒ more damages

� Classically, degradation mechanisms are thermally activated

100 101 102 103 104 10510 -3

10 -2

10 -1

10 0

T=25°C

T=70°C

T=125°C

Idlin

/Idlin

Stress time (sec)

∆∆ ∆∆

93


Inverter-Based Ring Oscillator

A B≡≡≡≡A B

Reset RO power supply

Divider/BufferOutput

Divider/buffer power supply

Ground of RO and divider/buffer

NMOSdegradation

PMOSdegradation

94


Dynamic Degradation Impact on Oscillation Frequency

� AC hot-carrier injectiondegrades MOS parameters(VTH, ION...)

– Oscillation frequency �(Propagation time ��)

– Leakage (Ioff) ��3V

3.5V

4V

Fre

quen

cy r

elat

ive

degr

adat

ion

(%) VDD stress :

95


Hot-Carrier Injection History

� ICs live with DC HCI lifetime < 10 years for someparameters…

1.E-031.E-021.E-01

1.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+07

Life

time

(yea

rs)

0.5um0.35um

0.25um

0.18um core

0.18um I/O

0.12um core

0.12um I/O

Technology

Idsat

WC linear

Life

time

(a.u

.)

96

� HCI vs device scaling– ~ Same lateral field vs Vdd…– … but Vdd scales down=> Reduction of HC creation=> Comfortable drift-times for core

devices

� But nowodays technologies have I/O devices to maintain compatibility with5V/3.3V world

– HCI still has to be carefullyaddressed especially for thesedevices


No Longer a Reliability issue ?

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.810-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

@VDD

NMOSFET's W=10µm

HCMOS Generations

LG: Tox (nm):

0.25/ 5

0.18/ 3.2

0.12/ 2.1

Isu

b/(

Id(V

d -

Vd s

at))

1/(Vd - Vdsat) (V-1)

97


WLR Strategy� (Arbitrary) criterion : less than 10% most sensitive MOS

parameter shift in 10 year operation– Sensitivity depends on design– Operation depends on design

� Micronic technologies– Hot-carrier endurance assessment through DC hot-carrier injection

experiments, representing the worst-case w.r.t. circuit operations– Valid approach since drift-times higher than 10 years

� Deep-submicron technologies– DC drift-time not higher than 10 years for the most sensitive MOS

parameter– DC approach not sufficient

� Analysis keeping in mind the design context� Hot-carrier endurance assessment through DC having in mind the

AC operation

98


Case of Digital Designs/Blocks� Factor of merit : speed

– Speed is associated with drive (saturation) current

� HCI occurs during (a part of) switching transitions– HCI is not DC in digital blocks– DC to AC is taken at 50:1 (industry standard)

A B≡≡≡≡A B

NMOSdegradation

PMOSdegradation

=> Qualification criterion : DC drift-time for 10% Idsatshift at Vddmax, wors-case conditions > 0.2 year(10 years / 50)

99


Case of Analog Designs/Blocks

� Statement : some transistors inside analog blocks may need good stability on all parameters duringup to 10 years DC

� Solution : table in the DRM providing minimum channel length to consider in order to have 10 yearworst-case DC drift-time for 10% worst-affectedMOS parameter drift for various (Vds,Vgs)– This (10%, 10 years, Vds/Vgs…) can be refined through

model equations

100


Process Performance vs. Design

PROCESS QUALIFICATIONDIGITAL CRITERION

DIGITAL CIRCUITS/BLOCKS

DIGITAL CRITERION+ UTILIZATION RULES

ANALOG CIRCUITS/BLOCKS

HOT CARRIER DEGRADATION IMPACTON MOS TRANSISTORS

RELIABLE DESIGN

101

OUTLINE

Negative Bias Temperature Instabilities

� Description of the phenomenon

� Impact on the MOS parameters

� Physics of the degradation & process impact

� Impact on design

� Reliability simulation

102

NEGATIVE BIAS TEMPERATURE INSTABILITIES

What is NBTI ?

� NBTI : PMOS parameters’degradation in presence of holesclose to the interface at hightemperature (> 80°C) and low gatevoltage

VDD VDD

VDD

103


Which MOST Conditions to Have NBTI ?

[NBTI affects P-channel MOSTs]

� PMOST needs to be inverted– but does not need current flow in the channel

� Needs (negative) electric field across the oxidelayer– Enhanced at « relatively » high negative Vgs

� Thermally activated– Enhanced at high temperature (typically 0.5-0.6eV)

104

� HCI depends on the channel electric field and consequently the Vds, while NBTI arises due to oxide field and consequently depends primarily on Vgs/Vgd.

� Conventionally, hot-carrier is present in both NMOS as well as PMOS, while NBTI is pre-dominant in PMOS

� HCI needs current flow, while NBTI does not.

� Consequently, NBTI occurs in static condition, while HCI occurs in (digital) circuits (only) during switching activity.

� NBTI (Ion degradation) is almost constant vs. channel lengths. In contrast, HCI can be drastically reduced by increasing channel lengths


NBTI vs. HCI

105


Buildup of a Concern

� Known since the late sixties, but not considered as an important reliability concern (except for some nonvolatilememories)

� However, BTI issues inadvertently enhanced up to a major reliability concern due to several processing and scaling changes :

– Introduction of CMOS in early 80’s that has made pMOS and nMOS devices equally important for IC designs

– Introduction of dual poly-process that has allowed replacement of buried channel pMOS devices with surface channel devices

– Slower scaling of operating voltages for analog circuits comparedto more aggressive scaling of oxide thickness has graduallyincreased the effective field across the oxide

– Thinner oxides have brought the poly-silicon gate closer to the Si/SiO2 interface

106


Degradation of Electrical Parameters

� Threshold voltage shift

� Decrease of saturation current

1,E-12

1,E-10

1,E-08

1,E-06

1,E-04

-1,5 -1 -0,5 0 0,5 1

Gate voltage (V)

Dra

in c

urre

nt(A

)

Idsat reduction

Vth shift

2nm-thick pMOSFETstressed at –2.5V

107

0,01

0,1

1

10

100

1 10 100 1000 10000

Stress time (s)Th

resh

old

volta

ge s

hift

(a.u

.)

pMOSVg<0

pMOSVg>0

nMOSVg<0

nMOSVg>0


Bias Temp. Instabilities : Comparison

� Threshold voltage shifts are reported for similar nMOS and pMOS devices stressed underboth positive and negativebias at the same temperature.

� pMOS stressed in inversion (negative bias) is the worstcase.

� That is why BTI primarilyconcerns PMOS undernegative bias (NBTI)

108

NBTI

StressStop &

Meas

NBTI

StressStop &

Meas

[Ershov]


Test Methodology : Conventional

� Conventional approach :– Stress w/ interruptions at desired intervals for

measurements– Easy to implement, but recovery effects induced by

transient effects

109

0

0.1

0.2

0.3

0.4

0 0.02 0.04 0.06 0.08 0.1

Threshold Voltage shift (a.u.)

d(i d

lin/g

m)

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vgs-Vth (V)

K p

aram

eter

Vgsense

0

0.1

0.2

0.3

0.4

0 0.02 0.04 0.06 0.08 0.1

Threshold Voltage shift (a.u.)

d(i d

lin/g

m)

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vgs-Vth (V)

K p

aram

eter

Vgsense

Periodic pulses around VGstress

Stress Time

VD

VG

50mV

VGstress

Periodic pulses around VGstressPeriodic pulses around VGstress

Stress Time

VD

VG

50mV

VGstress

Stress Time

VD

VG

50mV

VGstress

thVtg

dlingm V

ItVg

,

),(

∂∂=

)2

1(1

2

1

dsthgs

dsthgs

dsdlin

VVV

VVVVI

−−+

−−=

θβ

ththdsthgsm

dlin dVKdVVVVg

Id −=−−+−=

))

21

(21( θ

This methodology is independent of mobility change


Test Methodology : On The Fly

110

Si Si Si

Si Si Si

SiSiSi

Si

SiO

Si

O

O

O

Liaison pendante

à l’interface SiO2/Si

Sour

ce

Drain

Gril

le

Lacune d’oxygène

dans l’oxyde

SiO

O

O

OSi

OO

OO

O

O

Si

Si

SiO

O

O

OO

O

Si

O

O

H

+

Charge fixe prochede l’interface SiO2/Si

Si

O

O

O

O

O

O

Si

O

O

O

Si+

E’

Piège de type

« Switching oxide trap »

Si

O

OO

O O

Si Si Si

Si Si Si

SiSiSi

Si

SiO

Si

O

O

O

Liaison pendante


Sour

ce

Drain

Gril

le

Lacune d’oxygène

dans l’oxyde

SiO

O

O

OSi

OO

OO

O

O

Si

Si

SiO

O

O

OO

O

Si

O

O

H

+


Si

O

O

O

O

O

O

Si

O

O

O

Si+

E’

Piège de type


Si

O

OO

O O

Dangling bond at Si/SiO2 interface


Contribution Nr. 1 : Nit Creation

111


Interface State Creation

� NBTI degradation well known to induce interface traps, linked to – Oxide field – Activated in temperature

1.E+09

1.E+10

1.E+11

1.E+12

1 100 10000 1000000Stress time (s)

Inte

rfac

e tr

apde

nsity

shift

T=200°C

T=50°C

apparent activationenergy

0

0.1

0.2

0.3

0.4

0.5

0 0.02 0.04 0.06

kT (eV)

Pow

er la

wex

pone

nt

25°C

125°C

200°C

1.E+09

1.E+10

1.E+11

1.E+12

1 100 10000 1000000Stress time (s)

Inte

rfac

e tr

apde

nsity

shift

T=200°C

T=50°C

apparent activationenergy

2.1nm-thick nitrided oxide

112

Si Si Si

Si Si Si

SiSiSi

Si

SiO

Si

O

O

O

Liaison pendante


Sour

ce

Drain

Gril

le

Lacune d’oxygène

dans l’oxyde

SiO

O

O

OSi

OO

OO

O

O

Si

Si

SiO

O

O

OO

O

Si

O

O

H

+


Si

O

O

O

O

O

O

Si

O

O

O

Si+

E’

Piège de type


Si

O

OO

O O

Si Si Si

Si Si Si

SiSiSi

Si

SiO

Si

O

O

O

Liaison pendante


Sour

ce

Drain

Gril

le

Lacune d’oxygène

dans l’oxyde

SiO

O

O

OSi

OO

OO

O

O

Si

Si

SiO

O

O

OO

O

Si

O

O

H

+


Si

O

O

O

O

O

O

Si

O

O

O

Si+

E’

Piège de type


Si

O

OO

O O

Dangling bond

at Si/SiO2 interfacePositive fixed charge

close to Si/SiO2 interface


Contribution Nr. 2 : Nf Creation

113

1

10

100

1000

1 10 100 1000 10000

Stress time (s)

Vol

tage

shi

fts (a

.u.)

0

2

4

6

8

10

dVth /dV

mg ratio

0

0.2

0.4

0.6

0.8

1

1.2

-2 -1 0 1 2

Gate voltage (V)

Cap

acita

nce

(µF

cm-2

)

Stress

Vth, Vmg shifts

No Vfb shift

Vth shift

Vmg shift

1

10

100

1000

1 10 100 1000 10000

Stress time (s)

Vol

tage

shi

fts (a

.u.)

0

2

4

6

8

10

dVth /dV

mg ratio

0

0.2

0.4

0.6

0.8

1

1.2

-2 -1 0 1 2

Gate voltage (V)

Cap

acita

nce

(µF

cm-2

)

Stress

Vth, Vmg shifts

No Vfb shift

1

10

100

1000

1 10 100 1000 10000

Stress time (s)

Vol

tage

shi

fts (a

.u.)

0

2

4

6

8

10

dVth /dV

mg ratio

0

0.2

0.4

0.6

0.8

1

1.2

-2 -1 0 1 2

Gate voltage (V)

Cap

acita

nce

(µF

cm-2

)

Stress

Vth, Vmg shifts

No Vfb shift

Vth shift

Vmg shift

Amphoteric nature of interface traps

No Flatband voltage (V FB) shift

Midgap voltage (V midgap ) shift

Threshold voltage shift (V th) two

times larger than V midgap one

NBTI degradation also induced positive oxide fixed charges in an equal amount than interface traps

1.8nm-thick nitrided oxide


Fixed Charge Creation

114

Si Si Si

Si Si Si

SiSiSi

Si

SiO

Si

O

O

O

Liaison pendanteà l’interface SiO2/Si

Sour

ce

Drain

Gril

le

Lacune d’oxygène

dans l’oxyde

SiO

O

O

OSi

OO

OO

O

O

Si

Si

SiO

O

O

OO

O

Si

O

O

H

+


Si

O

O

O

O

O

O

Si

O

O

O

Si+

E’

Piège de type


Si

O

OO

O O

Si Si Si

Si Si Si

SiSiSi

Si

SiO

Si

O

O

O

Liaison pendanteà l’interface SiO2/Si

Sour

ce

Drain

Gril

le

Lacune d’oxygène

dans l’oxyde

SiO

O

O

OSi

OO

OO

O

O

Si

Si

SiO

O

O

OO

O

Si

O

O

H

+


Si

O

O

O

O

O

O

Si

O

O

O

Si+

E’

Piège de type


Si

O

OO

O O

Dangling bond

at Si/SiO2 interfacePositive fixed charge

close to Si/SiO2 interface

Oxygen vacancy or

Nitrogen-related

trap

Switching trap


CONTRIBUTION Nr. 3 : Hole Trapping

115

25 30 35 40

1/kbT (eV-1)

Thr

esho

ld v

olta

ge s

hift

(a.u

.)

1,E+10

1,E+11

1,E+12Interface density shift

Ea (Vth ) = 0.063 eV

Ea (N it) = 0.156 eV

1 10 100 1000 10000

Stress time (s)

Thre

shol

d vo

ltage

shi

ft (a

.u.)

1,E+10

1,E+11

1,E+12

Interface trap density (cm-2eV

-1)

45°C

85°C

125°C

45°C

85°C

125°C


Recovery : Temperature Dependence

� Threshold voltage shift and interface traps creation have different activation energies . This result implies that another process has to be taken into account in order to explain the threshold voltage shift => hole trapping

Different Ea more than one mechanism

116

0

0,2

0,4

0,6

0,8

1

1,2

0 1000 2000 3000 4000

Stress time (s)

Rel

ativ

e ��

Vth

shi

ft

0

0,2

0,4

0,6

0,8

1

1,2

Relative ��

Nit shift

NBTI stressVg < 0 Vg > 0

T=125°C


Recovery Effect� Reasonable to think that

this second component of Vth in addition to Nit is related to positive charges trapped into the oxide.

� Applying a positive gate bias consecutively to a negative bias stress is known to neutralize both trapped holes and/or positively charged slow states.

� Holes are trapped/detrapped at the vicinity of the interface

� The interface trap density remains almost unchanged.

Holes aredetrapped

117

EF0

EV

ECqεotox

tox

qεtoxEF0

EV

ECqεotox

Trapped holes

Prestress Stress Poststress

x 0

Et

EF0

EV

ECqεotox

tox

qεtoxEF0

EV

ECqεotox

Trapped holes

Prestress Stress Poststress

x 0

Et


Hole Trapping/Detrapping Model

� Based on elastic tunnelling from valence band states to traps and vice-versa

� Allows to predict Vth shift as function of density of traps

118


Synthesis : Physics of the Degradation� The NBTI degradation of electrical parameters such as the

threshold voltage or the drive current finds its origin in both the creation of interface traps and fixed charge on one side, and the trapping of holes into the oxide on the other side.

� For the latter component, the oxide defects related to the trapping phenomenon seems to be preexistent to the stress.

� For the former component, both the oxide field and the temperature dependences play a key role.

� The physical mechanism behind the release of hydrogen species at the interface remains so far unknown but seems to be strongly correlated to the presence of channel holes, though their density is not a limiting factor.

119

∆D = ∆Dp + ∆Dr

Degradation :

total Permanent Recoverable

Relaxation : ∆R

1) Stop of the stress 2) AC case (freq., df %)

Del

ta V

T

AC stress

∆D

1 101 102 103 104

delta

VT

Time (s)

relaxation

Permanent =

Recoverable =

Stop of the stress

degradation

0

1

Hole trapping

Interface traps + Fixed chargeshole

de-trapping


Activity Dependence

120

0

0,01

0,02

0,03

0,04

1 10 100 1000 10000 100000

Stress time (s)

Thr

esho

ld v

olta

ge s

hift

(a.u

.)

0

0,01

0,02

0,03

0,04

1 10 100 1000 10000 100000

Stress time (s)

Thr

esho

ld v

olta

ge s

hift

(a.u

.)

Duty cycle 50%

10Hz

100kHz

Frequency 100kHz

90%Duty cycle70%

50%30%

10%

frequency dependence duty cycle dependence


Activity Dependence

121


Process and Design Reliability Strategy

MAKE IT AS GOOD AS POSSIBLEFOR LINEAR PARAMETERS (Vth)

MAKE IT SAFE FOR DIGITALBY PROCESS CONSTRUCTION

OPTIMIZE THE PROCESS ANALYZE THE DESIGN AND ADAPT

HOW TO TACKLE NBTI ?

RELIABLE DESIGN

ReliabilitySimulation

122


WLR Strategy : case of Digital Blocks� Factor of merit : speed

– Speed is associated with drive (saturation) current

� NBTI occurs during « 0 » output stages– DC to AC is taken at 2:1 (NBTI during 50% of the period)

A B≡≡≡≡A B

PMOSdegradation

=> Qualification criterion : DC drift-time for 10% Idsatshift at Vddmax, wors-case conditions > 5 years(10 years / 2) – but relaxation !

123


NBTI Impact on Circuits

VS

VB

VDVG

ImpactThreshold Voltage

Carrier MobilityCurrents

DEVICE LEVEL

+

-

OP AMP

SRAMs

Logic

IMPACT

?

CIRCUIT LEVEL

NBTI impact on circuits is a function of �operating modes of circuits, �operating conditions faced by devices as a combination of these modes and the various input stimuli

o both for stress and impact�sensitivity of the performance of the circuit in the context of its place in design hierarchy

E.g., a small shift in differential pair could could be felt by the product, while a big shift in transistors in a power-down control block may affect nothing

124


Possible Impact on Circuits� Propagation delays – increase� Rise/fall times – change� Duty cycle of signals – change� Setup and hold times for latch/flip-flop – change� Current consumption – decrease� Leakage – change� Switching threshold – change� Drive currents – decrease� Offset voltage for a differential input if the voltages are

very asymmetrical – increase� Operating points in an analog circuit – change� Signal Noise Margin in SRAM cells – decrease

125


Digital Operation

� Characteristics– Unavoidable NBTI condition

� During switching or stable signal levels, the NBTI is present during the time any PMOST is biased to a digital ‘0’

� Favourable factors– NBTI degradation is seen to reduce with operating

frequency

126


Analog Operation – Impact Due to NBTI

� Characteristics– Higher sensitivity to changes in linear MOS parameters

� Possible requirement for all the MOS parameters to fulfill 10yrs dc-drifttime

– Higher impact due to a given stress � Due to typically low Vgs-Vt operating conditions

� Favourable factors– Low operating Vds/Vgs (significantly below Vdd)– In general, difficult to have NBTI conditions in linear

analog circuits– Feedback and gain also usually stabilize the circuits

with respect to drifts

127


Simple Guidelines to Minimize NBTI

� Having critical PMOSTs in non-conducting mode (e.g., this would mean a ‘1’ at the input of an inverter), so that Vgs or Vgd is not negative(e.g., with a pull-up).

� Shutting down the block completely during power-down (no supply)

� Limiting the operating Vgs

� Reducing asymmetry between stresses of matched devices

� Using NMOS instead of PMOS where NBTI problem exists

� Ensuring that the devices operating at low vgs conditions are not exposed to VDD during other modes of operation

128


The Solution : Reliability Simulation� Detect the degradation conditions different MOSTs are

exposed to in one or more modes of operation– E.g., power down, start up, input low, output low, normal operation

– Each of the modes could have different NBTI stress levels on the same set of transistors

Reliability Analysis = Stress detection + Performance impact assessment

� Assess the sensitivity of the circuit in the same or another mode of operation

– A given NBTI stress could impact a transistor in different ways depending on its operating mode

� Delay sensitivity – e.g., critical paths

� Vgs-Vth sensitivity – e.g., bias points or offsets in analog circuits� Circuit threshold sensitivity – e.g., noise margins

129

Buffer - Delay Increase

IO Input threshold change


Example of Reliability Simulation

130

OUTLINE

Plasma-induced damages

� Physical phenomena

� Test structures

� Test methods

� WLR strategy

131

PLASMA-INDUCED DAMAGES

Generalities� Multilevel technologies� Increasing use of plasma-assisted process� Sub-100Å gate oxides

Oxide deposition

Metal Etch

Oxide Etch(vias or contacts)

MOSFET's Degradation

132


Plasma Non-Uniformity

� Plasma = collection of– Charged particules– Neutral particules

� Plasma is globally neutral

� Localized plasma non-uniformity

antennaantenna

PLASMA

J ion J ionJe Je

degradationsdegradations

J+

J -

– Residual net charge on metal/via/contact to be evacuated

– Easiest way = gate oxide– Fowler-Nordheim injection– Gate oxide degradation/breakdown

133


Electro-Shading

� Ions can penetrate in depth between lines

� Electrons are trappedin the resist

⇒ Metal line charged⇒ Electron current flow through the gate oxide

� Electric field– Accelerates ions– Slows down electrons

E

--

-

- --

- -

- - -

-------

---------

---------

----------

- -------

-+ + + + +

+ +++ + + + + + + +

+ +

+ + ++

FN current

� Species flux

ions

– Ions ~ anisotropic

e-

– Electrons ~ isotropic

134


Test Structures

� Reference device : no charging– protection by diode as soon as

possible in the process

pad

metal (x) Antenna

Transistor

Vias (x)

metal (x)

Antenna

Transistor

Antenna Ratio = Antenna area / MOSFET area

Transistor

Diode

LIL

metal (x)

Antenna

Transistor

� Specific test structures to enhancethe charging effect with antenna atback-end level(s)

135


Manifestations of the Degradation

PROTECTED

POLY COMB 30

010

00

POLY+CT C

OMB 100

M1 COMB 30

010

0030

00

M1+V1 C

OMB 1000

M2 COMB 30

010

00

3000

0

M2+V2 C

OMB 1000

M2 PLATE 18

30

M3 COMB 30

010

0030

00

M4 COMB 30

010

0030

00

M5 PLA

TE 1830

0

20

40

60

80

100

Leak

age

(%)

10-999pA ~ 1nA > 7nA

Antenna

PROTECTED

POLY COMB 30

010

00

POLY+C

T COMB 10

00

M1 COMB 30

010

0030

00

M1+V1 C

OMB 1000

M2 COMB 30

010

0030

00

M2+V2 C

OMB 100

0

M2 PLA

TE 1830

M3 COMB 30

010

0030

00

M4 COMB 30

010

0030

00

M5 PLATE 18

30

0.60

0.61

0.62

0.63

0.64

0.65

0.66

0.67

Vth

(V

)Antenna

136


Main Causes of the Degradation

� Electron tunneling current flow through the gate oxide layer– Trap generation & electron trapping

� Flat band, threshold voltage shift

– Trap generation (thin oxides)� Low electric field gate leakage currents

– Destructive failure� Quasi-Breakdown� Hard Breakdown

� But damages may be not detected at time-zero– Thermal budget may induce electron detrapping ⇒ no VTH shift– ...⇒ Needs of ways to reveal the damages

137


Latent Defect Revealing

� Fowler-Nordheim stress– A relevant way to

reveal plasma-inducedlatent damages

– Initial Electron Trapping Slope method

0 1000 2000 3000

Comb Antenna Ratio

0

2

4

6

8

10

12

( V

TH/V

THo)

/ (

VTH

/VT

Ho)

ante

nna

p

rote

cted

Poly M1

M2 M3

M4

∆∆

2

0 50 100 150 200 250 3000.5

1

1.5

Thr

esho

ld v

olta

ge (

V)

tstress (s)

Protected

M1/AR=300

138


WLR Strategy

� Set of test structures devoted to the quantification of charging effects at each relevant process step

� In-line (parametric test) :– Threshold voltage measurement– Low electric field gate leakage current measurement– Threshold voltage shift after (short) Fowler-Nordheim injection

� But needs minimum calibration (choice of stress/time conditions)

� Off-line :– QBD after Fowler-Nordheim injection– Threshold voltage shift after (short) Fowler-Nordheim injection

139

OUTLINE

Electromigration

� Physics of the phenomenon

� Main dependencies

� Test methodology

� Test structures

� WLR strategy

140

ELECTROMIGRATION

Definitions

� Interconnects : distribution of potential by electron current flow

– Circuit power supply– Connection of the different active and passive devices

141

ELECTROMIGRATION

A Movie of the Failure…

142

ELECTROMIGRATION

Definitions� Electromigration : displacement fo metal activated by

current flow and temperature� Physical origin : Momenta exchange between the current-

carrying electrons and the host metal lattice� Observation : Due to divergence centers along the

interconnect disturbing the material flow– Void growth ⇒ signal opens– Extrusion growth ⇒ shorts

e- e- e-

e- e-

MEB Observations

143

ELECTROMIGRATION

Typical Failures

144

ELECTROMIGRATION

Physics of the Phenomenon�Forces acting on metal ions

– Electric field –induced force :

– Electron-ion collision induced friction force :

jeZEeZF ionionfieldelectric

rrrρ==_

ElenpnF eeecollisionfriction

rrrσ−=∆−= .

( ) jeZEleneZFFF eeeionfrictionfieldelectrictotal

rrrrrρσ *_ =−=+=

E

e- +

+

frictionFr

directeFr

eeecollision nn σν ⋅⋅=

e

eljep

νρ ⋅⋅⋅=∆

145

ELECTROMIGRATION

Physics of the Phenomenon (cont’d)

�Net electromigration flux (Nerst-Einstein) :

�In metal, Z* is negative (-10 < Z* < 0)=> material flux in the same direction as the electronic flux

jlneZekT

DNJ eeeionionEM ⋅⋅⋅⋅⋅−⋅⋅⋅= ρσ )(

E

e- +

+

frictionFr

directeFr

jZekT

DNJ ionEM ⋅⋅⋅⋅⋅= ρ*)(

146

ELECTROMIGRATION

Observation

W

Cu

e-

MEB Observation

147

ELECTROMIGRATION

Potential Diffusion Mechanisms

≠≠≠≠ activation energies

- +

�Grain boundary diffusion�Grain boundary/volume diffusion�Volume diffusion�Surface diffusion�Dislocation diffusion�Interface diffusion

148

ELECTROMIGRATION

Cause of the Phenomenon� Atoms diffusion cannot alone be responsible for

electromigration- induced failures⇒ Need of flux divergence at the grain boundary

intersection to provoke– saturation of vacancies (voids)– saturation of interstitials (hillocks)

� Temperature gradient– Affects diffusivity of some grain boundaries more than others

� Current crowding– Void or hillock growth changes the local conduction section

� Stress gradient– Atoms preferentially diffuse down the stress gradient, raising

the diffusivity in grain boundaries along the stress gradient

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