Peter Göttlicher , DESY For CALICE collaboration TWEPP 2012 Oxford , September 20 th , 2012

Peter Göttlicher | TWEPP 2012 | Oxford, September 20th 2012 |

Peter Göttlicher, DESYFor CALICE collaboration

TWEPP 2012Oxford , September 20th, 2012

Simulations and Measurements for a Concept of Powering CALICE-AHCALat a Train-cycled Accelerator


Outline

> Introduction: ILC, ILD, AHCAL for CALICE

>Motivation for power cycling

> Building blocks for power cycling

> Summary


ILD: International Large Detector e+e- needs precise detectors Concept:Particle flow algorithm

Accelerator and Detector for e+e-

Bunches arrives as trains 1ms long trains, 199ms break, …. bunch to bunch 337ns

ILC: International Linear Collider e+e- collider with 0.5 -1 TeV

e+

e-Collision pointwith detectors

Technology:- High granularity calorimeters- e.g. CALICE-AHCAL-barrel

NeedOption: For factor 100by switching off the fast analogue electronics for 99.5% of the time

Low power per channel: 40µW/channel can be reached by power cycling

Introduction

60000 h𝑐 𝑎𝑛𝑛𝑒𝑙𝑠1𝑚3


Interconnects with flex foils for signals, GND and power

AHCAL: Analog-Hadron- CALorimeter for ILD

Scintillator tileswith SiPM readout

Plugged to the back of a

Readout board

12 x 12 tiles36x36 cm2

Cassette: 2.2m long structures: 864 channels

Control electronicsand power connections

ASIC’s for- analogue signals,- local storage while train- ADC’s - data transfer

Layer:composed out of 3 cassettes: 2600 channels

Sampling sandwich with 48 layers each 3 mm scintillator + 2.5 mm electronics, infrastructure +12 mm stainless steel3cm

Introduction


Motivation: Power Cycling to avoid active Cooling

Heat Electronics with 1% power cycle 25µW/channelSiPM Idark +15µW/channel

Þ NeedPower cyclingTo keep heat up below 0.50C

Mechanical design constraint:- No cooling within calorimeter for homogeneity and simplicity- Cooling only at service end

Solution:Parabel + Fourier terms

0.0 0.5 1.0 1.5 2.0 z = Position along beam axis [m]

Tem

pera

ture

incr

ease

[K]

0.00.1

0.2

0.3Z=0m

Z0=2.2m

Motivation

𝜕𝑇𝜕𝑡 =

1h𝑒𝑎𝑡 .𝑐𝑎𝑝 ./𝑎𝑟𝑒𝑎

𝑝𝑜𝑤𝑒𝑟𝑎𝑟𝑒𝑎 ]

𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑛𝑖𝑐𝑠+h𝑒𝑎𝑡 .𝑐𝑜𝑛𝑑 . 𝜕 𝑇❑

2

𝜕 𝑧 2

𝑇 (𝑧 ,𝑡 )=𝑇 𝑖𝑛𝑓 ( 𝑧2−𝑧 0❑2 )+∑𝑛=1

𝑖𝑛𝑓

𝑇𝑛𝑒−𝑡 /𝜏𝑛cos (𝑘𝑛 𝑧 )

Tn and tn scales with the second power of the length

No dependence on r: bad conduction in a sandwich j : symmetry


Building Blocks for the Power System

1. Planes with scintillators and SiPM’s, ASIC’s and PCB’s

without cooling

4. Power supply

2. End of layer electronics

with cooling

DAQ is Optical:No issue for EMI

3. cable

Building blocks


ASIC for fast SiPM Signals consuming Low Power

Bunches from collider (ILC/CLIC): A train every 200ms

L. Raux et al., SPIROC Measurement: Silicon Photomultiplier Integrated Readout Chips for ILC, Proc. 2008 IEEE Nuclear Science Symposium (NSS08)

Functional tasks of the ASIC:- Amplify signals from 36 SiPM’s and generate self trigger- Store identified signals: 16 per train and SiPM: capacitor pipeline- Digitize - Multiplexed data transfer, daisy-chained ASIC’s

0.5%needed

ADC Digital data transfer

RAM ASIC: SPIROC-2b

SiPM

Amp.

Fast amplifiers: 1msADC’s 3.2ms

Common analogue parts, e.g. DAC’s, C-pipelineDigital control: 150ms

>20µs ON before train

1µs

Building blocks

Algorithm for power cycling:The ASIC switches the current of the functional blocks OFF.

until now no control of the slope.ASIC gets supplied all the time with voltage …. No dis-/charge of C’sPCB electronics and instruments stabilize the voltage all the time


Cur

rent

/pin

[mA

/pin

]

Time after switch [µs]

ASIC as current switchMeasurements:- Inductive current probes Slow: DC – 5MHz

Fast: 30MHz-3GHz

- Setup: ASIC+ capacitors on a PCB - Expectation is ~ 1mA/channel ~40mA/ASIC, summed over all pins 13mA/pin, OK.

Voltage pin (1 of 3) for preamplifier

-20 0 20 40 60 [ns] timeSystem has to deal with: EMI: electromagnetic interference - 5Hz from train repetition to few 100MHz- 2.2A for a layer, 3.4kA for AHCAL-barrel

30mA/pin

Building blocks

One of the GND-pinsFast probe

Slow probe at1 of 3 pins

Measured currents at the pre-amplifier-supply of ASIC


Current loops

To do:- Controlling return currents- Keeping loops small- Avoid overlapping with foreign components.

Capacitive coupling

To do:- Keep common mode voltage stable- Guide induces currents to source- Keep GND-reference closer than foreigns

Electro Magnetic Interference in a Power Cycled System

Reference ground:- Need good definition- Any induced/applied current produces voltage drops- Separation between reference / power return / safety or controlling currents and keeping currents within “own” volume and instrumentation

Guideline: Avoiding emission avoids in most cases picking up of noise

reference return Safety. PE

Building blocks


GND dPCB= 50-60µm Vsupply

GND

Keeping the high Frequencies local

36 x 36 cm PCBwith scintillators, SiPM’s, LED

144mA switched current

Part of a thin cassette between absorber layer of HCAL

Layer structure of PCB:

Simulation model:“two diomensional delay line”

Building blocks

1cm2

0.7ns

Well known by geometry:Capacitance: parallel plates

Inductivity: 1-dim. delay-line

One gets- A thin PCB- A good high frequency capacitor 60pF/cm2

Short traces to via to maintain the performance


Tantal

Voltage for ASIC stabilized by local discrete Capacitors

Total:12 Tantal/4 ASIC’s+ 17 ceramics+ PCB

PCB, alone

Tantalum, AVX, 33µF

Murata, 100nf

Murata, 10nf

Murata, 2.2nf

Murata, 1nf

Ceramics X7R

1kHz 1MHz 1GHz

Impe

danc

e Z

=|U

|/|I|

Frequency

900

-900U to

I ph

ase

shift

00

ASIC is supported overwide frequency rangewith Z< 0.1W144mA generates <20mV

Oscillations are dumpedfor wide frequency range with phase ¹ ±900

Trust in simulation:- <1.5GHz=(1/10) granularity- No resistive behavior of ASIC is included. That over estimates the resonances at high frequencies

Result:- Locally good for > 10kHz- Additional effort < 10kHz

0.1 W

1 W

10 W

100 W

0.01 W

Capacitors mounted to the 36x36cm2 PCBSimulation of voltage induced by current

ceramicPCB-layer

Dominated by:

Capacitor like

Coil like

Building blocks


Resistor can dumpresonant behavior

Simulation 16 ´ 1.6W Each AC-coupled with real 100nF

Reality - Not on the boards - No negative effects seen - ASIC’s do it themselves? - Easy for next generation

to be safe.

Phase variations 100MHz-1GHzBuilding blocks

VCC

Real C: 100nFSimulation: L-R-C

1.6W

GranularityLimit ofsimulation

phas

e

+900

-900

Frequency [Hz]

Impe

danc

e [O

hm]

110

0.10.01

00

Only PCB and C’sAdditional R-C’s

G


Low frequency charge storage for < 10kHz

At end of layer,there is a bit of - space- cooling

Concept:- Charge for the train stored in a capacitor C2

- Voltage drop allowed ~ 0.6V- Fast voltage regulator - Charge for faster reaction is within the distributed capacitors + C3

C2 = 3.4mF bank of few Tantala voltage regulator with external FET > 2AC3+distributed = 2mF

C2C3

Building blocks


Voltage step: - Measured 4mV, 400ns- Extrapolate to full system

< 80mV at far endOK for operation, over-,undervoltage, time, …

Induces current into GNDPE, if step is on GNDelectronics

< 2 mA per layer Large amount of steel

Definition of GND-point: - good for keeping sensitive SiPM’s stable - single connection to reduce currents in GNDPE system

Voltage at ASIC: Measurement

Control electronicsfor layer

Reduced test setup: Control board, 1 interconnect, 1 board

Tantalum taken away

Default setup

Tantalum moved to control board

Power onCommand,step in IASIC

Sup

ply

volta

ge o

f AS

IC (A

C-c

ompo

nent

)

[

mV

]

GNDelectronics

2m2/Layer1.3mm distance

4mV

Stainless steel absorber= GNDPE

Þ OK, even with extrapolation to 1500 layers low?Investigations of reason and improvements possible, to be watched

Time [ns]

Building blocks

parasiticC=13nF


Integrating to Infrastructure70pF/m from cable to support

ASICasswitchedcurrent sink

50m cable, 1mm2, on a cable support

0 1 2 3 4 5 [ms] 6time

nA0

-40

-80

-120

-160

Cur

rent

per

laye

r

Current induced into GNDPE

𝜏=0.1𝑚𝑠

𝜏=1𝑚𝑠𝜏=10𝑚𝑠

𝜏=100𝑚𝑠

Simulation of cable

𝜏=𝑅𝐶

Impact of cable is a combination of choices:- Input filter: R=10W, C=1mF reasonable mechanical size EMI better t=100ms- Power supply behavior here

- no capacitance to PE - ideal V-source- Mechanical integration and

galvanic isolation per (group or) layer and pair of wires for it

With 1500 layers of AHCAL: IPE=120mA Really small, but not all parasitic effects! Don’t be too reluctant in EMI-rules

Building blocks

Not simulated


0

0.5m0

-10µ-0.5m

Cur

rent

in P

E [A

]

0µs 50µs 0ms 1ms

Current switch Current switch16µs

Integration of parasitic parameters of infrastructureBuilding blocks

Real Tantalum-C’sPower supply: C to chassis(Toellner)

Cable above metal support Inductance to support

Parasitic LC (only return):2𝜋√𝐿𝐶=21µ 𝑠

Parasitic elements

increases currentpp

a factor 5000

Need: - Reasonably done infrastructure, e.g. small L’s, C’s - Electronics (e.g. p-filter) reducing sensitivity

Time after current switch

1cm

Slope isdis-/rechargeduring train Very small amplitudeoscillation


Current in Supply Cable

Control electronicsfor layer

Reduced test setup: Control board, 1 interconnect, 1 board, Short cable to laboratory supply

Cur

rent

per

1/1

8 la

yer

in s

uppl

y ca

ble

[m

A] Preamplifiers ON ADC’s ON

Work bench settings

Without input filter with input filter t=10ms

Input filter important tolower amplitude fluctuationsand remaining frequencies within cableImportant: EMI-crosstalk to others

Frequencies are lowElectronics like to have larger tto smoothen further ÛMechanics easier in service-hall

Building blocks


Consequences per power supply

Multichannel systems - to keep supply/return currents near, not using metal infrastructure to distribute - Floating per channel: Individual voltage drops- Low ripple: 5-10(20) mVpp

It is not too exotic,- But for 1500 layers , best individual, or in small geometrical nearby groupsNeed a well adopted system.

On the market are developments (partially) driven by research CAEN, ISEG, WIENER and ??????

?DC/DC-converters- Floating- Magnetic field- Low ripple.- Pulsed load

AHCAL - has less stringent cable requirements, - not really needed.- Multi-wire cables are an option

Others might profit To far in the futurefor a survey or dedicateddevelopments


Status

Work with single board and not 6 in a chain

WithoutPower pulsing

WithPower pulsing

Performance check with single photon detections in SiPM’s

- Resolution is maintained

To be worked on:- Baseline shift, but seen also at other

operations (next generation of ASIC)- Longer time to stabilize than

expected: ~200µsec - PCB or ASIC? - Voltages are settling faster - Wouldn’t be great factor in power

0 1 2 3photons

0 1 2 3photons


Summary Detectors for Linear Colliders requires many channels with low power Train structure allows 99% time to be OFF: Factor 100 in critical regions Coherent fast switching ON/OFF of high current: CALICE-AHCAL: 2.2A*layers : 3.4kA for the barrel

5Hz to few 100MHz System aspects at local design - Local defined return-paths for current - Local charge storage for wide frequency ranges that keeps

- impedances small- currents leaving a defined volume small and slowly rising/falling

System aspects within the infrastructure Lower frequency part is partially on the cables and power supplies. Good integration of power supplies and cables needed. Simulation leaves many parasitic effects out – first integrations done That usually underestimates the high frequency EMI-disturbance

…. Therefore planning a conservative approach. Experimental setups, integration, wishlists into ILD to be continued

Peter Göttlicher , DESY For CALICE collaboration TWEPP 2012 Oxford , September 20 th , 2012

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