public

1

Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks

IMEC: Amita Rawat, Philippe Matagne, Bjorn Vermeersch, Geert Hellings, Julien Ryckaert

Huawei: Krishna Bhuwalka, Wu Hao, Changze LiuBelgium

rawat67@imec.com

public

Motivation and Introduction

TCAD deck calibration

Circuit delay and RO frequency estimation methodology

RO performance comparison and design space study

Self-heating performance comparison

Conclusion

2

Outline

public

3

Motivation

Reduced stress control with introduced inner spacers

-2000

-1500

-1000

-500

0

500

1000

Top

Middle

Bottom

Str

ess

alo

ng

ch

an

nel (M

Pa)

Air-gap

horiz.

Top wire

Middle wire

Bottom wire

Air-

gap

vert.

Air-

gap

lateral

Air-gap

hor.+

vert+

lateral

(1nm)

Ref:no

air-

gap

Channel stress at end of process

Verti

cal

Cross-section

The ‘vertical’ interface is the most critical to maintain channel stress: stress is lost completely when epi from neighboring gates doesn’t join properly

public

4

Introduction

SD

With Inner Spacer

SD

WithoutInner Spacer

W ISP W/O ISP

Stress engineering No Yes

Parasitic cap. Low High

Parasitic res. High Low

Self-heating High Low

Considered cases for electrical performance comparison▪ Option I: With inner spacer and 100 % stress▪ Option II: With inner spacer and 0 % stress▪ Option III: Without inner spacer and 100 % stress

𝜿 = 𝟕. 𝟓 𝜿 = 𝟏𝟏. 𝟗

TCAD Deck Calibration

public

6

NMOS: Width = 11 nm, Str: 100 %

Without With

Vths (V) 0.188 0.180

Ion-lin (uA) 15.96 16.45

Ion-sat (uA) 46.3 49.2

SS (mV/dec) 75.5 71.05

DIBL (mV/V) 35.3 30.7

PMOS: Width = 11 nm; Str = 100 %

Without With

Vths (V) -0.185 -0.178

Ion-lin (uA) 19.6 18.64

Ion-sat (uA) 54.8 55.4

SS (mV/dec) 68.8 65.98

DIBL (mV/V) 29.23 40

DOPING CONCENTRATION PROFILE

Parameters NMOS PMOS

L (nm) 15 15

TNS (nm) 11 11

HNS (nm) 5 5

Spacer (nm) 5 5

100 % Stress (GPa)

0.7 -1.7

NSD (𝐜𝐦−𝟑) 1e21 1e21

NSD ext (𝐜𝐦−𝟑) 1e17 1e17

Nchannel (𝐜𝐦−𝟑) 1e15 1e15

w/ ISP w/o ISP

public

7

ISP removal decreases NMOS on-current

𝑲𝒐𝒖𝒕 = 4𝑲𝒊𝒏 = 7.5

Stress = 0 GPa

NMOS PMOS

Vd = 0.7 V Vd = -0.7 V

public

8

ISP Removal increases carrier scattering

45 𝝁A

64 𝝁A

40 𝝁A

68 𝝁A

𝑲𝒐𝒖𝒕 = 4𝑲𝒊𝒏 = 7.5

Stress = 0 GPa

w/o ISPw ISP

Scattering: Carrier-carrier and carrier-ion

Without scattering

With scattering

x

x

Methodology to estimate RO performance using device parasitcs

public

Simplified RC network of device

10

D

G

S

Ceff1/Aeff

𝐶𝐷𝐺 = 𝐶𝑆𝐺𝐴𝐷𝐺 = 𝐴𝑆𝐺

In on state, D and G terminals are shorted

Effect parasitic network in on-state𝐶𝑒𝑓𝑓 = 𝐶𝑆𝐺 + 𝐶𝐷𝑆𝐴𝑒𝑓𝑓 = 𝐴𝑆𝐺 + 𝐴𝐷𝑆

D

G

S

CSG

1/ASG

CDS1/ADS

D

G

S

CDG

1/ADG

CSG

1/ASG

CDS1/ADS

public

11

RO frequency estimation

𝑫𝑰𝒏𝒗 𝑭 =𝟏

𝟐 × 𝟗 × 𝑫𝑰𝒏𝒗

𝑶𝒖𝒕

Charging

𝐂𝐞𝐟𝐟−𝐧

𝟏/𝐀

𝐞𝐟𝐟−𝐧

𝐂𝐞𝐟𝐟−𝐩

𝟏/𝐀

𝐞𝐟𝐟−𝐩

𝑮𝑵𝑫

𝑽𝑫𝑫

Load

𝐂𝐞𝐟𝐟−𝐧

𝟏/𝐀

𝐞𝐟𝐟−𝐧

𝐂𝐞𝐟𝐟−𝐩

𝟏/𝐀

𝐞𝐟𝐟−𝐩

𝑮𝑵𝑫

𝑽𝑫𝑫

Discharging

Load

Charging delay of inverter:

𝐷𝑝 = 𝐶𝑒𝑓𝑓−𝑝/𝐴𝑒𝑓𝑓−𝑝 Discharging delay of inverter: 𝐷𝑛 = 𝐶𝑒𝑓𝑓−𝑛/𝐴𝑒𝑓𝑓−𝑛

Inverter stage delay, 𝑫𝑰𝒏𝒗 = 𝑫𝒑 +𝑫𝒏

On state capacitance and admittance

public

13

ISP removal increases parasitic capacitance by 40 %

𝑲𝒐𝒖𝒕 = 4𝑲𝒊𝒏 = 7.5𝑲𝑺𝒊 = 11.9

~ 40 %

~ 38 %Opt. III: w/o ISP; Stress = 0.7 GPa

Opt. II: w ISP; Stress = 0.0 GPa

Opt. 1: w ISP;Stress = 0.7

GPa

Opt. III: w/o ISP; Stress = -1.7 GPa

Opt. II: w ISP;

Stress = 0.0 GPa

Opt. I: w ISP; Stress = -1.7 GPa

NMOS versus PMOS: D-G Terminals

NMOS PMOS

public

14

ISP removal significantly increases admittance (thanks to max. stress)

NMOS PMOS

~ 6 %

~ 8

2 %

Opt. III: w/o ISP; Stress = 0.7 GPa

Opt. II: w ISP; Stress = 0.0 GPa

Opt. I: w ISP; Stress = 0.7 GPa

Opt. III: w/o ISP; Stress = -1.7 GPa

Opt. II: w ISP;

Stress = 0.0 GPa

Opt. I: w ISP; Stress = -1.7 GPa

NMOS versus PMOS: D-S Terminals

Impact of stress and device architecture on delay performance

public

16

ISP removal increases NMOS effective delay by 15 %

Opt. II: w ISP

Opt. I: w ISP

Opt. III: w/o ISP

Process Advantage: w/o ISP

~15 %

13

5%

10

0 %

0 %

Discharging delay (𝐷𝑛): with and without inner spacer

public

17

ISP removal lowers PMOS effective delay by 36 %

Opt. II: w ISP

Opt. I: w ISP

Opt. III: w/o ISP

Process Advantage: w/o ISP

~36 %

13

5%

10

0 %

0 %

Charging delay (𝐷𝑝): with and without inner spacer

Estimation of 9-stage RO frequency using individual device delay information

𝑫𝑰𝒏𝒗 𝑭 =𝟏

𝟐 × 𝟗 × 𝑫𝑰𝒏𝒗

𝑶𝒖𝒕

Inverter stage delay, 𝑫𝑰𝒏𝒗 = 𝑫𝒑 +𝑫𝒏

public

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6N

orm

. Freq

uen

cy

Opt. II:w ISP

Str. = 0 %

Opt. I:w ISP

Str. = 100 %

Opt. III:w/o ISP

Str. = 100 %19

ISP removal increases RO frequency by 11 % (at realistic stress)

(143.5 GHz)

~50 %

~11 %

public

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6N

orm

. Freq

uen

cy

Opt. II:w ISP

Str. = 0 %

Opt. I:w ISP

Str. = 100 %

Opt. V:w/o ISP

Str. = 135 %20

Applying extra stress can further boost RO frequency

~18 %(143.5 GHz)

public

21

Reducing 𝜅 of ISP offer minor RO frequency improvement

Normalisation Frequency = 143.5 GHz

▪ The RO frequency is less sensitive to inner spacer 𝜿 variation

~4 %

Stress = 0 %

Opt. II: w ISP

Self-heating performance comparison

public23

ISP Removal facilitates heat removal towards substrate

IDEAL HEAT SINK IDEAL HEAT SINK IDEAL HEAT SINK

IDEAL HEAT SINK IDEAL HEAT SINK IDEAL HEAT SINK

2 200 uW/um220

Si SiGe TiN SiN lowK highK W Ru

NS regular

NS w/o inner spacer

finFET (iN3 dim.)

10 1005 50Heat flux

Continuous Si path(inner spacer removed)allows increased heatremoval to substrate

Vertical streaks in fin= ballistic transport

100 nm100 nm100 nm100 nm100 nm100 nm

NS regular

NS w/o inner spacer

finFET (iN3 dim.)

public

24

ISP removal lowers self-heating: NS thermal performance becomes competitive with FinFET

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

-105 -35 35 105

Longitudinal position x [nm]

Finger 1

Finger 2 Finger 3

Finger 4

NMOS side

NS regular

NS w/o inner spacer

finFET

Tem

pera

ture

ris

e [°

C/u

W]

NSregular

NS withoutinner spacer

finFET(iN3 dim.)

A A’ A A’ AA’

A A’

IDEAL HEAT SINK IDEAL HEAT SINK IDEAL HEAT SINK

IDEAL HEAT SINK IDEAL HEAT SINK IDEAL HEAT SINK

public

25

Conclusion

Parasitic capacitance

Admittance

Delay

RO Frequency

RO Frequency (extra stress)

ISP Dielectric

Self-heating

Effects of ISP removal

+40 %

N: +6 % P: +82 %

N: +15 % P: -36 %

+11 %

+18 %

+4 %

-7 %

(Due to increased stress)

(Due to carrier scattering)

(Due to increased stress)

(Due to improved heat removal)

public

Bae, Geumjong, et al. "3nm GAA technology featuring multi-bridge-channel FET for low power and high-performance

applications." 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 2018.

Barraud, S., et al. "Performance and design considerations for gate-all-around stacked-NanoWires FETs." 2017 IEEE

international electron devices meeting (IEDM). IEEE, 2017.

Loubet, N., et al. "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET." 2017 Symposium on VLSI

Technology. IEEE, 2017.

Bardon, M. Garcia, et al. "Power-performance trade-offs for lateral nanosheets on ultra-scaled standard cells." 2018 IEEE

Symposium on VLSI Technology. IEEE, 2018.

Ritzenthaler, R., et al. "Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced vertical nanowires

separation, new work function metal gate solutions, and DC/AC performance optimization." 2018 IEEE International

Electron Devices Meeting (IEDM). IEEE, 2018.

Zhang, Jingyun, et al. "High-k metal gate fundamental learning and multi-V t options for stacked nanosheet gate-all-around

transistor." 2017 IEEE International Electron Devices Meeting (IEDM). IEEE, 2017.

Eneman, Geert, et al. "Stress Simulations of Fins, Wires, and Nanosheets." ECS Transactions 98.5 (2020): 253.

Sentaurus TCAD Design Suite [online]. Available: http://www.synopsys.com.

Ohishi, Yuji, et al. "Thermoelectric properties of heavily boron-and phosphorus-doped silicon." Japanese journal of applied

physics 54.7 (2015): 071301.

26

References

Thank you