Performance of vertical power devices with contact-level copper metallization

Performance of vertical power devices with contact-levelcopper metallization

Jeffrey Cooka,*, Misbahul Azamb, Pak Leungc, Melissa Grupena

aMotorola Advanced Interconnect Systems Laboratory, 2100 E. Elliot Road, Tempe, AZ 85284, USAbMotorola Transportation Systems Group, 2200 W. Broadway Road, Mesa, AZ 85202, USA

cMotorola Advanced Custom Technologies, 2200 W. Broadway Road, Mesa, AZ 85202, USA

Received 17 June 1998; accepted 5 December 1998

Abstract

Vertical power devices have been used to characterize device performance with contact-level copper interconnects. Rdson (device resistance

in the ``on'' state) measurements were obtained using three different probe con®gurations for various aluminum and copper metallizations.

These measurements were used to make qualitative comparisons between aluminum and copper in terms of metal-to-silicon contact

resistance and bondpad spreading resistance. Results indicate that contact resistance can be achieved with TiW/copper-based interconnects

which is comparable to that of the standard Al-to-Si contact. Results also suggest a signi®cant decrease in bondpad spreading resistance with

2 mm copper. q 1999 Published by Elsevier Science Ltd. All rights reserved.

Keywords: Copper; Electrical properties and measurements; Metallization; Resistivity

1. Introduction

1.1. Copper interconnects

The feasibility of using copper as a replacement for

aluminum in semiconductor device interconnects has been

a subject of great interest in recent years. The lower bulk

resistivity, greater electromigration resistance, and better

thermal transport properties of copper offer considerable

potential bene®ts in a wide variety of device technologies

[1±5]. In technologies in which line resistance is a signi®-

cant fraction of the total device resistance, the lower resis-

tivity of copper can reduce the total resistance of the device,

provided the barrier thickness does not exceed a critical

fraction of the line dimensions. In high-power devices,

where current density is limited by electromigration consid-

erations, copper may again prove to be an enabling technol-

ogy for future generations [6±13].

However, there are several major technical challenges

which have hampered the introduction of copper-based

devices. First is the need for effective diffusion barriers.

Copper diffuses readily through conventional dielectrics

and acts as a deep-level dopant in silicon, and can therefore

have a detrimental effect on line-to-line, transistor, and

diode leakage, as well as decreasing carrier lifetimes

[4,14±17]. Barrier materials are needed which block the

diffusion of copper without adding unduly to the total resis-

tance or otherwise diminishing the performance of the inter-

connect. Optimum barrier properties, such as bulk

resistivity and required thickness, are different for different

interconnect designs; ®ne-geometry designs in which line

resistance is critical may require the thinnest possible

barrier, regardless of its bulk resistivity, while larger devices

in which resistance of the contact is dominant would bene®t

more from thicker but lower-resistivity barrier materials.

The second challenge is in copper etching. Dry etching

techniques have been sought for copper for a number of

years, and are still only in the development stage [18±25].

Because copper etch byproducts are non-volatile and non-

soluble, effective removal of these byproducts from the

wafer surface has not yet been proved to be manufacturable.

The use of copper has therefore required either wet etching

techniques, which severely limit geometries and aspect

ratios, or damascene designs using chemical-mechanical

polishing (CMP).

The third challenge is in wirebonding. Because copper

does not form a self-limiting oxide, reliable wirebonding

to copper and subsequent passivation must be addressed

before widespread use of copper in the semiconductor

Thin Solid Films 348 (1999) 14±21

0040-6090/99/$ - see front matter q 1999 Published by Elsevier Science Ltd. All rights reserved.

PII: S0040-6090(99)00165-0

* Corresponding author.

E-mail address: [email protected] (J. Cook)

industry can be realized. Several package-level interconnect

techniques exist which could be applied to copper intercon-

nects, particularly solder bump or ¯ip-chip approaches.

Bump techniques eliminate the effects of bondpad spreading

resistance, but are not always the best solution for all

devices. The development of a direct copper wirebonding

technique is therefore highly desirable. The evaluation of

some copper bonding techniques will be the focus of a later

publication.

1.2. Copper for vertical power devices

In vertical power devices such as Motorola's Wave-

FETTM, the lower bulk resistivity of copper is not necessa-

rily expected to yield any bene®t in terms of reduced series

resistance; nor is there a critical need at this time for

increased electromigration resistance. However, the use of

copper for such devices should theoretically lead to lower

spreading resistance beneath the wirebonds, thus potentially

lowering the overall resistance of the device in the ON state.

To accomplish this reduction, two additional conditions

must be met. First, the contact resistance of copper to barrier

and barrier to silicon must be comparable to that in tradi-

tional aluminum-based devices. In the devices used for

these experiments, the normal con®guration uses an alumi-

num alloy in direct contact with silicon. Second, a means of

bonding the lead wires to the die in such a way that the

majority of current spreading still takes place within the

copper layer, but so that the increased resistance of the

wirebond does not negate the bene®cial properties of the

copper. Furthermore, all this must be possible without an

excessive increase in cost per ®nished device.

The purpose of this work is not to prove the feasibility of

copper for WaveFETTM devices, but rather to make use of

the properties of the device to characterize the barrier

performance, contact, and spreading resistance properties

of copper interconnects.

1.3. Test vehicle selection

Considerable work has been performed to attempt to

characterize the performance of copper barriers and inter-

connects using analytical techniques or actual device

measurements. The former has proven very useful in the

evaluation of barrier stability [26±29]; but the best way to

evaluate copper-based devices, strangely enough, is to actu-

ally evaluate copper-based devices. WaveFETTM type

power devices such as those manufactured by Motorola

provided a relatively simple device, with fast process

cycle times and simple test procedures. In addition, the

device is expected to be very sensitive to the properties

and failure mechanisms of interest to this work.

The major performance marker for these power devices is

Rdson, the resistance of the device in the ``on'' state. This

resistance is the sum of several individual resistances, the

most signi®cant of these being the bondpad spreading resis-

tance, the metal-to-silicon contact resistance, and the chan-

nel resistance. If the use of copper in place of aluminum

reduces the ®rst source of resistance more than it increases

the second, then the use of copper may be justi®ed in such

devices. Contact resistance, of course, is directly related to

the contact metal work function and the quality of the inter-

faces. The devices used in this study differed in area from

the WaveFETTM product, and therefore the Rdson values

obtained are not representative of the product devices.

The devices are also sensitive to copper contamination in

terms of drain to source leakage (Idss), gate to source leakage

(Igss), and ®eld breakdown voltage (Vbd) due to copper diffu-

sion into the active regions, oxide spacers, and ®eld oxide,

respectively. The device can therefore be used to character-

ize the effectiveness of the barrier material against copper

diffusion.

The current evaluation included, ®rst, a comparison of

Rdson using copper and aluminum to determine the effects

of copper on contact and spreading resistance. Secondly,

device performance was measured before and after thermal

exposure to verify the effectiveness of the TiW barrier

against copper diffusion.

2. Experimental procedure

WaveFETTM type vertical power devices were fabricated

using a standard process ¯ow up to and including contact

etch. For subsequent process steps, the following processes

and test procedures were used.

2.1. Experimental splits at metallization

Four experimental splits were made at metal deposition to

determine the differences in Rdson between aluminum-based

and copper-based metallization. These splits, consisting of

J. Cook et al. / Thin Solid Films 348 (1999) 14±21 15

Table 1

Experimental splits

Process Split (1) Split (2) Split (3) Split (4)

Pre-Sputter Clean HF dip 100 AÊ Sputter etch (Process A) 100 AÊ Sputter etch (Process A) 100 AÊ Sputter etch (Process B)

Barrier None 2000 AÊ TiW (Process A) 2000 AÊ TiW (Process A) 1

Vacuum break

2000 AÊ TiW (Process B)

PVD Metal 2 mm Al-Si 2 mm Al-Si 1000 AÊ Cu (Process B) 1000 AÊ Cu (Process B)

Plated Metal None None 2 mm Copper 2 mm Copper

Metal Etch RIE RIE Wet etchback Wet etchback

three complete wafers each, are summarized in Table 1. A

standard photolithographically-de®ned copper plating tech-

nique was used in the copper splits, with 2000 AÊ TiW barrier

plus 1000 AÊ Cu seed deposited by PVD (physical vapor

deposition) prior to photolithography and subsequent Cu

plating through the resist. Seed Cu and barrier etchback

were then performed to isolate the lines and pads in the

copper splits.

Each split contained three wafers. Split (1) was a `Stan-

dard' split, similar to the WaveFETTM product except for the

use of 2 mm of aluminum instead of thicker metal, and the

use of an RIE (reactive ion etch) metal etch instead of a wet

etch. The numerical results reported below for Split (1) are

therefore not necessarily representative of any current

Motorola product. Split (2) was identical to Split (1) except

for a 2000 AÊ TiW barrier between the aluminum and silicon.

Split (3) used 2 mm copper on a 2000 AÊ TiW barrier. A

break in vacuum was included between the barrier and seed

depositions to evaluate the effect of atmospheric exposure

on contact performance. Split (4) was identical to Split (3),

except that the TiW and copper seed were both deposited in

a single pass without breaking vacuum. After metal etch, all

wafers were hand-probed using a Tektronix 575 Curve

Tracer to estimate breakdown voltage (Vbd), threshold

voltage (Vt), and leakage (Idss). The wafers were then

processed through back grind and back metal processes as

normal for these devices. This consisted of mechanical thin-

ning to a thickness of 380 mm, followed by sputter deposi-

tion of Ti/Ni/Ag alloy on the back side, which in these

devices functions as the source. The drain and gate struc-

tures are located on the front of the die.

2.2. Electrical probing

Each wafer used in this study contained 32 die, with a

number of devices of varying geometry on each die; only

selected devices were used in electrical measurements.

Following back grind and back metal, an HP 9472 Auto-

matic Testing System was used to measure Rdson for the

selected devices. Measurements were made on all 32 die

per wafer on all wafers. Probing was performed by three

different techniques:

1. Standard probe (Fig. 1), using multiple current probes on

the source to minimize the effects of spreading resis-

tance, and separate sense probes to characterize the inter-

nal device resistance only. The current probes were

distributed more or less evenly over the surface of the

pad.

2. A true four-point probe (Fig. 2), using only one probe to

force current at the source and with maximum force-

sense separation.

3. A three-point probe (Fig. 3) with the source current probe

being used as the source voltage probe, used to include

the effects of spreading resistance at the source bondpad

in the Rdson measurement.

The single source current probe in (2) and (3) was placed

at the probe location which was farthest from the sense

probe, in order to maximize the effect of spreading resis-

tance. Resistance in all three techniques was calculated from

source/drain voltage measurements at gate voltages ranging

from 2.5 to 10 V.

2.3. Metal thickness measurement

The thickness of the copper pads could not be measured

directly by scanning electron microscopy (SEM) due to the

considerable deformation that occurs when copper is

cleaved to produce cross-sections, even at reduced tempera-

tures; nor could a focused ion beam (FIB) technique be used

for sectioning due to the erosion of copper by the ion beam.

Therefore, following probe, atomic force microscopy

(AFM) was performed on one wafer from each split for

step height measurement at the edge of three different

metal pads on the center die. One wafer from Split (4)

was measured at ®ve different locations to evaluate

across-wafer variation in plated Cu thickness. The same

pad/die combinations were then measured in SEM to deter-

mine the height of the lower copper interface above the

bottom of the etch trench. The thicknesses of the copper

and aluminum layers were determined by subtracting this

latter value from the AFM step height measurements.

2.4. Effects of thermal exposure

Four additional wafers which received the same proces-

sing as Split (4) (Wafers (13)±(16)) were probed, Wafers

(13) and (14) as processed and Wafers (15) and (16) after

annealing, to test the integrity of the 2000 AÊ TiW barrier

J. Cook et al. / Thin Solid Films 348 (1999) 14±2116

Fig. 1. Standard four-point Rdson measurement technique using multiple

current force probes.

Fig. 2. True four-point Rdson measurement technique using a single current

force probe.

against copper diffusion into the contact and gate dielectric.

The annealing was performed at 4008C for 3 h, and was

conducted under high vacuum (#1027 Torr) to prevent

excessive oxidation of the copper surface. Heating and cool-

ing rates were very high, on the order of 1008C/s.

3. Results and discussion

3.1. Hand-probe results

Hand probing revealed similar characteristics for Splits

(1), (3), and (4), with reverse-bias breakdown voltages (Vbd)

from 30 to 36 V, threshold voltages (Vt) of about 2.2 V, and

drain-to-source leakage currents (Idss) of under 30 nA. Vt and

Idss values were not obtained for Split (2), as these wafers

displayed such severe snapback that the devices burned out

while measuring Vbd. Split (3) also revealed some snapback,

but the devices remained intact. Splits (1) and (4) showed no

snapback at all. Snapback refers to an abnormal current/

voltage response during reverse bias breakdown which is

caused by high series resistance in the conductive pathway

[30]. In these devices, it can result from either high resis-

tance in the doped region due to incorrect doping, or high

metal-to-silicon contact resistance. Since all the wafers in

the experiment were processed through the implant steps in

a single batch, the metal-to-silicon contact resistance is

believed to be the cause of the snapback found in Splits

(2) and (3).

Results from previous lots had shown that a good TiW/Si

interface would have roughly the same contact resistance as

the Al/Si interface used in the standard WaveFETTM

product; this and the absence of snapback in Split (4)

suggested that the contact resistance problem in Splits (2)

and (3) was associated with the pre-TiW sputter clean used

for those splits, not the TiW itself. It has also been suggested

that high Cu to TiW contact resistance can result from an air

break between the two layers; this would explain the snap-

back in Split (3), but not in Split (2), where the aluminum

was deposited directly on top of the TiW without an air

break. The non-optimized sputter etch is therefore believed

to be the primary source of the high resistance.

3.2. Final probing: standard technique

All wafers were back-ground to 380 mm thickness after

hand-probing, including those in Split (2). These wafers

were sent on for ®nal processing and testing in spite of the

severe snapback found during hand probing, because the

®nal automatic probing is much more delicate than the

hand-probe, using millisecond-duration current pulses to

avoid resistive heating. Rdson measurements on Split (2)

wafers were therefore still expected to provide useful infor-

mation.

The results of the ®rst (standard multi-pin) probe pass are

shown in Figs. 4 and 5; all resistance values are in mV . The

overall behavior is very similar for all four splits. The

devices turn on at a gate voltage of 3.5±4 V. Fig. 5 shows

the expanded curves in the `On' range. This plot shows that

the Rdson behavior of Splits (1) and (4) is essentially identi-

cal.

This result suggests comparable performance at the

device level between the `standard' split, with direct Al/Si

contact, and copper-based devices. No signi®cant advantage


Fig. 3. Three-point Rdson technique capturing source probe contact and

spreading resistance.

Fig. 4. Semilog plot of Rdson (mV ) for WaveFETTM devices as a function of

gate voltage (Standard multi-pin technique).

Fig. 5. Linear plot showing the ``on'' range of Rdson (in mV ) for Wave-

FETTM devices as a function of gate voltage (Standard multi-pin technique).

was expected at this level with copper, for the following

reasons:

1. The Al/Si interface has a slightly lower theoretical

Schottky barrier height than TiW/Si, due to the larger

work function for the latter (roughly 4.5 eV for W, the

major component in TiW, versus 4.3 for Al) [31]. While

barrier height could not be measured directly on these

devices, the contact clean for the standard split, which

removes native oxide and organic contamination from

the silicon prior to metal deposition, had already been

optimized for minimum contact resistance.

2. The Cu/TiW/Si stack has an additional interface between

the Cu and TiW, which contributes an additional contact

resistance term to the resistance equation.

3. Resistance in these devices is dominated by the metal/

silicon contact resistance and the resistance of the silicon

device itself, with metal bulk resistance playing only a

minor role.

4. The series resistance of 2 mm Cu on 2000 AÊ TiW is

actually more than twice that of 2 mm of Al-Si, so if

metal resistance were a factor the copper would be

distinctively worse with any TiW barrier over 500 AÊ in

thickness.

5. The copper process module was not optimized.

For these reasons, similar performance between the two

splits was the best result that could have been expected.

Splits (2) and (3), as expected from the snapback found

during hand probing, had higher Rdson than the other two

splits. However, while Split (2) (the Al/TiW split) appeared

to have a more serious problem during hand probing, the

Rdson resistance of Split (3) is actually very much higher. The

high Rdson in Split (3) suggests that the air break between the

TiW barrier deposition and the seed copper deposition may

have resulted in a poor quality interface between those two

layers.

3.3. Final probing: true four-point and three-point

techniques

Any measurable bene®t of copper in WaveFETTM type

devices was expected to be in the reduction of bond pad

spreading resistance, which is a signi®cant factor in the

overall resistance of the packaged device, and which

depends strongly on the wirebond and packaging technique

employed. The standard, multi-probe measurement techni-

que, using nine current force probes evenly distributed over

the surface, is used to minimize the effect of spreading

resistance. This allows the most accurate possible measure-

ment of device resistance in the absence of spreading resis-

tance effects.

The purpose of performing the three-point probe was to

isolate as much as possible the spreading resistance effect. A

single source-current pin was used in the three-point tech-

nique rather than the multi-pin approach used in the stan-

dard four-point technique, because the multi-pin approach

would have defeated this purpose. A true single-current-pin

four-point technique served as a point of reference and a

sanity check between the standard and three-point techni-

ques. These results are shown in Fig. 6.

The results of the three-point probe are shown in Fig. 7.

Average Rdson for Split (4) (copper) was found to be 30%

lower than that for Split (1) (standard aluminum). The stan-

dard deviations associated with each point on the graph have

also increased, from typically 5 to 8% in the four-point

techniques to as much as 20 to 30% in the Aluminum splits.

Greater variation is typically expected in two or three-point

techniques, because such measurements include not only

spreading resistance beneath the probe, but the probe-to-

pad contact resistance as well. Both of these properties are

affected by the quality and area of contact between the probe

and the metal pad, which in turn is strongly in¯uenced by

the condition of the oxide on the metal surface.

In the copper splits, there is considerable variation in Rdson

from one wafer to the next, as can be seen by comparing

Wafers (11) and (12) in Table 2, but the standard deviation

within wafers is still very low. In fact, the Rdson standard

deviation within Wafer 12 (Cu) is about the same in the


Fig. 6. On-Resistance (mV) of WaveFETTM devices as a function of gate

voltage (True four-point technique).

Fig. 7. On-Resistance (mV) of WaveFETTM devices as a function of gate

voltage (three-point technique).

three-point test (3.54%) as in the standard test (3.73%),

which suggests that on copper, unlike aluminum, the

probe-to-pad contact resistance is very consistent from

one die to the next.

The Rdson values in three-point testing (Fig. 7) are much

higher than in four-point testing (Figs. 4 and 5) due to the

contribution of spreading resistance and the aforementioned

probe to pad contact resistance. The average increase in

Rdson at 10 V for Splits (1)±(4) are 25.31, 44.33, 18.26,

and 17.05 mV , respectively, when changing from the stan-

dard to the three-point technique. These increases, which are

summarized in Table 2, include the effects of both spreading

resistance and probe to pad contact resistance. While these

two effects could not be separated using the available

measurement techniques, two additional facts appear to

suggest signi®cantly lower spreading resistance with

copper, as predicted by theory.

First, comparison of Wafers (2) (Split (1)) and (12) (Split

(4)), as can be seen in Table 2, reveals average Rdson values

of 39.36 and 26.99 mV , respectively. A Student's t-test

using this data results in a t-value of 2.69, which for the

sample size corresponds to a 98.6% level of con®dence that

the two samples are statistically different. This result would

be highly unlikely if the difference were due primarily to

probe-to-pad contact resistance, with comparable spreading

resistance behavior.

It can also be seen from the histograms in Fig. 8 that the

lowest measured Rdson for Wafer (2) (Split (1)) is greater than

the highest Rdson die from Wafer (12) (Split (4)), which, along

with the t-test results, again strongly implies a real improve-

ment in spreading resistance with copper for 2 mm thick

metal. These results also suggest that copper-based devices

could potentially be packaged using fewer wires or even a

single wire bond per device instead of multiple wires without

a resistance penalty, thus reducing the cost of the assembly

process. A larger statistical sample is needed, along with

properly packaged devices, to con®rm and quantify the

decrease in spreading resistance with copper.

3.4. Metal thickness measurement

AFM and SEM measurements were made as described in

Section 2.3 to determine whether the lower spreading resis-

tance might be due to a metal thickness effect. The results

are summarized in Table 2. Wafers (11) and (12) represent

the Split (4) wafers with the worst and best Rdson, respec-

tively. As can be seen from the table, the thickness of the

copper at the center die on these two wafers is in fact

comparable to the thickness of the aluminum in Splits (1)

and (2). It was also found that the variation in three-point

Rdson across wafer 12 was much less than the variation in

copper thickness across the wafer (3.5% standard deviation

versus 12%), and that there was no correlation between the

two. This indicates that differences in metal thickness were

not the cause of the observed differences in Rdson measure-

ments. Similarly, the large difference in Rdson between

Wafers (11) and (12), both from Split (4), is believed to

be the result of increased contact resistance, as described

previously, rather than a metal thickness effect.


Table 2

Calculated thicknesses of aluminum and copper interconnects based on AFM and SEM measurements, and corresponding Rdson values. Metal thicknesses are

measured at wafer center

Split no. Wafer no. Metal

thickness

(mm)

Rdson

(Std.,

mV )

Rdson (four-

point, mV)

D from

Standard

(mV )

Rdson (three-

point, mV )

D from

Standard

(mV )

1 2 1.48 14.05 12.97 21.08 39.36 25.31

2 4 1.68 14.80 13.90 20.90 59.13 44.33

3 7, 8, 9 ± 20.27 17.81 22.46 38.53 18.26

4 10 ± 14.26 12.03 22.23 27.94 13.68

4 11 1.21 14.68 11.66 23.02 38.65 23.97

4 12 1.54 13.84 11.52 22.32 26.99 13.49

Fig. 8. Histograms of Rdson values (mV ) for Wafers (2) (Split (1)) and (12)

(Split (4)) (three-point probe technique).

Table 3

Electrical performance of as-processed and annealed devices with copper

metallization

Split Wafer no. Rdson (mV) Vt (V) Vbd (V) Igss (nA)

As Processed 4 13 4.88 11.93 21.72 55.21

4 14* 5.87 11.02 27.58 52.95

Annealed 4 15* 8.18 13.18 20.82 53.21

4 16 5.90 13.16 20.70 52.39

3.5. Barrier thermal stability

Wafer-average values for Rdson, threshold voltage (Vt),

reverse-bias breakdown voltage (Vbd), and gate-to-source

leakage current Igss are shown in Table 3 for the as-

processed and annealed Split (4) type wafers. The Rdson

values re¯ect the snapback which was present in Wafers

(14) and (15). Because of the unknown degree to which

Rdson was affected by high contact resistance in these wafers,

measured Rdson can not be used as an indicator of the effects

of annealing on barrier integrity. The Vt data, on the other

hand, appears to indicate that annealing at 4008C for 3 h

increased Vt by 15 to 20%. Drain-to-source breakdown

voltage and gate-to-source leakage do not appear to have

been affected by the thermal exposure, indicating that no

diffusion of copper through TiW and into the active region

occurred. The data presented in this section in no way repre-

sent the reliability performance of the barrier ®lm, but do

indicate that the TiW barrier provides adequate protection

against thermal diffusion of copper into the device under the

above conditions.

4. Conclusions

Because the devices used in this experiment were tested in

an unpackaged condition, the lower measured Rdson values for

copper-based devices when spreading resistance is included

in the measurement does not necessarily imply any cost or

performance bene®t of using copper for WaveFETTM-type

devices. For the conditions studied, however, comparable

performance has been demonstrated at the device level

between vertical power devices fabricated with aluminum

and copper metallization, indicating that good TiW/Si and

Cu/TiW contacts have been achieved. An air break between

the TiW barrier and the seed copper, while not causing any

macroscopic adhesion problems, appears from the high Rdson

found in Split (3) to have an adverse effect on the contact

resistance between those two layers. It is also believed that

the pre-metal contact clean is an important factor in achiev-

ing good TiW contact to silicon.

While the probe techniques utilized in this study do not

allow the effects of spreading resistance and probe-to-pad

contact resistance to be separated, signi®cantly lower on-

resistance appears to have been demonstrated for Cu-based

devices compared to aluminum for 2 mm thick metal when

bond pad spreading resistance is included in the measure-

ment technique. The bene®cial effects of copper on device

performance are expected to be somewhat less for thicker

metal due to the decreased contribution of spreading resis-

tance. However, these results may be applicable to device

structures with metallization in the # 2 mm range.

Acknowledgements

The authors would like to thank the following individuals

for their contributions toward the completion of this work:

Jaynal Molla and Shun-Meen Kuo of Motorola Advanced

Interconnect Systems Laboratory, Nancy Waters of Motor-

ola Advanced Custom Technologies, and Chandra Ramiah

of Motorola Wireless Subscriber Systems Group for their

discussion and assistance in copper processing; Edouard

deFresart, Jeff Pearse, and Lydia Casillas of Motorola

Transportation Systems Group for providing WaveFETTM

device expertise and process ¯ows, and for assisting in the

planning and analysis of electrical probe data. Motorola

Advanced Custom Technologies for front-end and alumi-

num back-end processing; Motorola Advanced Interconnect

Systems Laboratories for back-end copper processing; Bill

Marlin of Motorola Bipolar-1 for TiW barrier and Cu seed

deposition; Pat Shaner of Motorola Advanced Custom

Technologies for devising probe set-ups for four- and

three-point probing, and for performing all ®nal probes;

Motorola MOS4 for performing back grind and back

metal deposition; and David Theodore, Wei Chen, Rod

Stradling, Brian Wajdyk, and Kathy Monarch of Motorola

Materials Testing and Characterization Group for perform-

ing AFM and SEM.

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Performance of vertical power devices with contact-level copper metallization

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