Performance of a high-throughput tracking processor ... · FPGA Switch FPGA Switch FPGA Engine FPGA...
1
Performance of a high-throughput tracking processor implemented on Stratix-V FPGA Federico Lazzari Università di Pisa & INFN Sezione di Pisa • Mathematically related to “Hough transform” [2] • Map tracks parameters space into an matrix of cells • In hadronic colliders at high luminosity (>10 34 cm −2 s −1 ) a heavy flavor particle will be produced at every beam crossing • It is not possible to trigger events efficiently using simple parameters • It is necessary to reconstruct high quality tracks at beam crossing rate (30 MHz @ LHC) WHY - Tracking at very high rate HOW - The "Arti fi cial Retina" Architecture [1] FUNCTIONAL PROTOTYPE HIGH-SPEED PROTOTYPE RESULTS • High event rate > 30 MHz with occupancy < 0.5% [5] • Very low latency, < 500 ns • Multi-board implementation with optical fibers has the same event rate as single-device configuration • This tracking processor has been included in the recent LHCb Expression of Interest for future upgrades presented to LHCC [6] TRACKER CONFIGURATION [3] 14th Pisa Meeting on Advanced Detectors, La Biodola (Italy), May 27 - June 02, 2018 • Generic tracker with 6 layers • Single coordinate layers (x silicon strip) • Layers grouped in 3 stations • Track parameters: first and last layer coordinate • Typical number of track @ LHCb SciFi: 200 [4] • Number of cells in the parameters space: 80k • Occupancy (track/cell): 0.25% Data flow from Detector Custom Switch delivers hits only to appropriate cells For each cell, the corresponding Engine performs a weighted sum of hits near the track trajectory Parameters are obtained interpolating responses of nearby cells Engines work in a fully parallel way Track are forwarded to DAQ system • 5 Altera Stratix III FPGA • 200K LE per FPGA • Maximum clock 350 MHz • 2 Altera Stratix V FPGA • 952K LE per FPGA • Maximum clock 650 MHz • 48 external 12.5 Gbps serial lines per FPGA Two boards connected with LVDS lines • Demonstrate system functionality FPGAs connected with LVDS lines • Test performances improvement after porting to newer FPGAs Single FPGA design • Measure the maximum reachable event rate FPGAs connected with optical fibers • Demonstrate the possibility of multi-board implementation PROJECT DETAILS Results achieved by “Retina”, a 3-year project funded by INFN, Division of technological research experiments R. Cenci 1,2 , F. Lazzari 1,2 , P. Marino 2,3 , M.J. Morello 2,3 , G. Punzi 1,2 , L.F. Ristori 4 , F. Spinella 2 , S. Stracka 2 , J. Walsh 2 1 Università di Pisa, 2 INFN Pisa, 3 Scuola Normale Superiore di Pisa, 4 FNAL REFERENCES [1] A. Abba, F. Bedeschi, M. Citterio, F. Caponio, A. Cusimano, A. Geraci et al., A specialized track processor for the LHCb upgrade, Tech. Rep. LHCb-PUB-2014-026, CERN, Geneva, Mar, 2014 [2] P. Hough, Machine analysis of Bubble Chamber Pictures, Proc. Int. Conf. High Energy Accelerators and Instrumentation C590914, 1959 [3] R. Cenci, F. Bedeschi, P. Marino, M. Morello, D. Ninci, A. Piucci et al., First Results of an "Artificial Retina" Processor Prototype, EPJ Web Conf.127 (2016) 00005 [4] LHCb Collaboration, LHCb Tracker Upgrade Technical Design Report, CERN-LHCC-2014-001; LHCB-TDR-015 [5] R. Cenci, F. Lazzari, P. Marino, M.J. Morello, G. Punzi, L.F. Ristori, F. Spinella, S. Stracka, J. Walsh, Development of a High-Throughput Tracking Processor on FPGA Boards, PoS(TWEPP-17) 136 [6] LHCb collaboration, Expression of Interest for a Phase-II LHCb Upgrade: Opportunities in flavour physics, and beyond, in the HL-LHC era, Tech. Rep. CERN-LHCC-2017-003, CERN, Geneva, Feb, 2017
Transcript of Performance of a high-throughput tracking processor ... · FPGA Switch FPGA Switch FPGA Engine FPGA...
h2
Latency measurementHigh-Speed Prototype (optical fibers)
Switchboard
LVDS
Switch EngineInternal
LVDS
Engineboard
EngineFPGA
SwitchFPGA
Switch FPGA
Engine FPGA
Switch
Engine
Detector layers
To DAQ
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
track / cell (%)
0
10
20
30
40
50
60
even
t rat
e (M
Hz) Functional Prototype
High-Speed Prot. (LVDS lines)High-Speed Prot. (single FPGA)High-Speed Prot. (optical fibers)
Exp
ect
ed
occ
up
ancy Target event rate
z
x
U
V
Performance of a high-throughput tracking processor implemented on Stratix-V FPGAFederico Lazzari Università di Pisa & INFN Sezione di Pisa
• Mathematically related to “Hough transform”[2]
• Map tracks parameters space into an matrix of cells
• In hadronic colliders at high luminosity (>1034 cm−2s−1) a heavy flavor particle will be produced at every beam crossing• It is not possible to trigger events efficiently using simple parameters• It is necessary to reconstruct high quality tracks at beam crossing rate (30 MHz @ LHC)
WHY - Tracking at very high rate HOW - The "Artificial Retina" Architecture[1]
FUNCTIONAL PROTOTYPE
HIGH-SPEED PROTOTYPE
RESULTS
• High event rate > 30 MHz with occupancy < 0.5%[5]
• Very low latency, < 500 ns
• Multi-board implementation with optical fibers has the same event rate as single-device configuration
• This tracking processor has been included in the recent LHCb Expression of Interest for future upgrades presented to LHCC[6]
TRACKER CONFIGURATION[3]
14th Pisa Meeting on Advanced Detectors, La Biodola (Italy), May 27 - June 02, 2018
• Generic tracker with 6 layers• Single coordinate layers (x silicon strip)• Layers grouped in 3 stations• Track parameters: first and last layer coordinate• Typical number of track @ LHCb SciFi: 200[4]
• Number of cells in the parameters space: 80k• Occupancy (track/cell): 0.25%
Data flow from Detector
Custom Switch delivers hits only toappropriate cells
For each cell, the correspondingEngine performs a weighted sum ofhits near the track trajectory
Parameters are obtained interpolatingresponses of nearby cells
Engines work in a fully parallel way
Track are forwarded to DAQ system
• 5 Altera Stratix III FPGA• 200K LE per FPGA• Maximum clock 350 MHz
• 2 Altera Stratix V FPGA• 952K LE per FPGA• Maximum clock 650 MHz• 48 external 12.5 Gbps serial lines per FPGA
Two boards connectedwith LVDS lines• Demonstrate system functionality
FPGAs connectedwith LVDS lines• Test performances improvement after porting to newer FPGAs
Single FPGA design• Measure the maximum reachable event rate
FPGAs connected with optical fibers• Demonstrate the possibility of multi-board implementation
PROJECT DETAILS
Results achieved by “Retina”, a 3-year project funded by INFN, Division of technological research experiments R. Cenci1,2, F. Lazzari1,2, P. Marino2,3, M.J. Morello2,3, G. Punzi1,2, L.F. Ristori4,
F. Spinella2, S. Stracka2, J. Walsh2
1Università di Pisa, 2INFN Pisa, 3Scuola Normale Superiore di Pisa, 4FNAL
REFERENCES[1] A. Abba, F. Bedeschi, M. Citterio, F. Caponio, A. Cusimano, A. Geraci et al., A specialized track processor for the LHCb upgrade, Tech. Rep. LHCb-PUB-2014-026, CERN, Geneva, Mar, 2014[2] P. Hough, Machine analysis of Bubble Chamber Pictures, Proc. Int. Conf. High Energy Accelerators and Instrumentation C590914, 1959
[3] R. Cenci, F. Bedeschi, P. Marino, M. Morello, D. Ninci, A. Piucci et al., First Results of an "Artificial Retina" Processor Prototype, EPJ Web Conf.127 (2016) 00005[4] LHCb Collaboration, LHCb Tracker Upgrade Technical Design Report, CERN-LHCC-2014-001; LHCB-TDR-015
[5] R. Cenci, F. Lazzari, P. Marino, M.J. Morello, G. Punzi, L.F. Ristori, F. Spinella, S. Stracka, J. Walsh, Development of a High-Throughput Tracking Processor on FPGA Boards, PoS(TWEPP-17) 136[6] LHCb collaboration, Expression of Interest for a Phase-II LHCb Upgrade: Opportunities in flavour physics, and beyond, in the HL-LHC era, Tech. Rep. CERN-LHCC-2017-003, CERN, Geneva, Feb, 2017
