Penn ESE535 Spring 2013 -- DeHon 1 ESE535: Electronic Design Automation Day 24: April 22, 2015...
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Transcript of Penn ESE535 Spring 2013 -- DeHon 1 ESE535: Electronic Design Automation Day 24: April 22, 2015...
![Page 1: Penn ESE535 Spring 2013 -- DeHon 1 ESE535: Electronic Design Automation Day 24: April 22, 2015 Statistical Static Timing Analysis.](https://reader034.fdocuments.in/reader034/viewer/2022051401/56649f395503460f94c55cdc/html5/thumbnails/1.jpg)
1Penn ESE535 Spring 2013 -- DeHon
ESE535:Electronic Design Automation
Day 24: April 22, 2015
Statistical Static Timing Analysis
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2
Delay PDFs? (2a)
Penn ESE535 Spring 2013 -- DeHon
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3Penn ESE535 Spring 2013 -- DeHon
Today
• Sources of Variation• Limits of Worst Case• Optimization for Parametric Yield• Statistical Analysis
Behavioral (C, MATLAB, …)
RTL
Gate Netlist
Layout
Masks
Arch. SelectSchedule
FSM assign
Two-levelMultilevel opt.CoveringRetiming
PlacementRouting
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4Penn ESE535 Spring 2013 -- DeHon
Central Problem
• As our devices approach the atomic scale, we must deal with statistical effects governing the placement and behavior of individual atoms and electrons.
10
100
1000
10000
1000 500 250 130 65 32 16
Technology Node (nm)
Mea
n N
um
ber
of
Do
pan
t A
tom
s
• Transistor critical dimensions• Atomic discreteness• Subwavelength litho• Etch/polish rates• Focus
• Number of dopants• Dopant Placement
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5Penn ESE535 Spring 2013 -- DeHon
Oxide Thickness
[Asenov et al. TRED 2002]
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6Penn ESE535 Spring 2013 -- DeHon
Line Edge Roughness
• 1.2mm and 2.4mm lines
From:http://www.microtechweb.com/2d/lw_pict.htm
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7
Light
• What is wavelength of visible light?
Penn ESE535 Spring 2013 -- DeHon
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8Penn ESE535 Spring 2013 -- DeHon
Phase Shift Masking
Sourcehttp://www.synopsys.com/Tools/Manufacturing/MaskSynthesis/PSMCreate/Pages/default.aspx
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9Penn ESE535 Spring 2013 -- DeHon
Line Edges (PSM)
Source:http://www.solid-state.com/display_article/122066/5/none/none/Feat/Developments-in-materials-for-157nm-photoresists
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10Penn ESE535 Spring 2013 -- DeHon
Intel 65nm SRAM (PSM)
Source:http://www.intel.com/technology/itj/2008/v12i2/5-design/figures/Figure_5_lg.gif
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11Penn ESE535 Spring 2013 -- DeHon
Statistical Dopant
Placement
[Bernstein et al, IBM JRD 2006]
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12Penn ESE535 Spring 2013 -- DeHon
Vth Variability @ 65nm
[Bernstein et al, IBM JRD 2006]
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Gaussian Distribution
Penn ESE535 Spring 2013 -- DeHon 13
From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg
![Page 14: Penn ESE535 Spring 2013 -- DeHon 1 ESE535: Electronic Design Automation Day 24: April 22, 2015 Statistical Static Timing Analysis.](https://reader034.fdocuments.in/reader034/viewer/2022051401/56649f395503460f94c55cdc/html5/thumbnails/14.jpg)
14Penn ESE535 Spring 2013 -- DeHon
ITRS 2011 Variation (3s)
Table DESN10 Design for Manufacturability Technology Requirements
Year of Production 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026Normalized mask cost from public and IDM data
1.0 1.3 1.7 2.2 2.8 3.7 4.9 6.4 8.4 11.0 14.4 18.8 24.6 32.1 ? ?
% Vdd variability: % variability seen in on-chip circuits
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
% Vth variability: doping variability impact on Vth, (minimum size devices, memory)
40% 40% 40% 45% 45% 50% 50% 55% 55% 60% 60% 65% 65% 70% 70% 75%
% Vth variability: includes all sources 42% 42% 42% 47% 47% 53% 53% 58% 58% 63% 63% 68% 68% 74% 74% 79%% Vth variability: typical size logic devices, all sources
20% 20% 20% 23% 23% 25% 25% 28% 28% 30% 30% 33% 33% 35% 35% 38%
% CD variability 12% 12% 12% 12% 12% 12% 12% 12% 12% 12% 12% 12% 12% 12% 12% 12%
% circuit performance variability circuit comprising gates and wires
42% 42% 42% 45% 45% 47% 47% 50% 50% 52% 52% 55% 55% 57% 57% 60%
% circuit total power variability circuit comprising gates and wires
51% 51% 51% 55% 55% 59% 59% 63% 63% 68% 68% 72% 72% 77% 77% 81%
% circuit leakage power variability circuit comprising gates and wires
126% 126% 126% 129% 129% 132% 132% 135% 135% 138% 138% 141% 141% 145% 145% 148%
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Example: Vth
• Many physical effects impact Vth
– Doping, dimensions, roughness
• Behavior highly dependent on Vth
Penn ESE535 Spring 2013 -- DeHon 15
€
IDS =μnCOX
2
W
L
⎛
⎝ ⎜
⎞
⎠ ⎟ VGS −Vth( )
2
[ ]
€
IDS = IS
W
L
⎛
⎝ ⎜
⎞
⎠ ⎟e
VGS −Vth
nkT / q
⎛
⎝ ⎜
⎞
⎠ ⎟1 − e−
VDS
kT / q
⎛
⎝ ⎜
⎞
⎠ ⎟
⎛
⎝ ⎜
⎞
⎠ ⎟1+ λVDS( )
![Page 16: Penn ESE535 Spring 2013 -- DeHon 1 ESE535: Electronic Design Automation Day 24: April 22, 2015 Statistical Static Timing Analysis.](https://reader034.fdocuments.in/reader034/viewer/2022051401/56649f395503460f94c55cdc/html5/thumbnails/16.jpg)
Impact Performance
• Vth Ids Delay (Cload/Ids)
Penn ESE535 Spring 2013 -- DeHon 16
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Impact of Vth Variation
Penn ESE535 Spring 2013 -- DeHon 17
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18
Variation in Current FPGAs
Penn ESE535 Spring 2013 -- DeHon
[Gojman et al., FPGA2013]
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Reduce Vdd (Cyclone IV 60nm LP)
Penn ESE535 Spring 2013 -- DeHon 19
[Gojman et al., FPGA2013]
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20Penn ESE535 Spring 2013 -- DeHon
Source: Noel Menezes, Intel ISPD2007
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21Penn ESE535 Spring 2013 -- DeHon
Source: Noel Menezes, Intel ISPD2007
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22Penn ESE535 Spring 2013 -- DeHon
Old Way
• Characterize gates by corner cases– Fast, nominal, slow
• Add up corners to estimate range
• Preclass:– Slow corner: 1.1– Nominal: 1.0– Fast corner: 0.9
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23Penn ESE535 Spring 2013 -- DeHon
Corners Misleading
[Orshansky+Keutzer DAC 2002]
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24Penn ESE535 Spring 2013 -- DeHon
Parameteric YieldP
roba
bilit
y D
istr
ibut
ion
Delay
DiscardSellPremium
Sellnominal
Sellcheap
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25Penn ESE535 Spring 2013 -- DeHon
Phenomena 1: Path Averaging
• Tpath = t0+t1+t2+t3+…t(d-1)
• Ti – iid random variables – Mean t– Variance s
• Tpath – Mean d×t– Variance = d × s
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26Penn ESE535 Spring 2013 -- DeHon
Sequential Paths
• Tpath = t0+t1+t2+t3+…t(d-1)
• Tpath – Mean d×t– Variance = d × s
• 3 sigma delay on path: d× + 3t d × s– Worst case per component would be:
d×( +3 )t s– Overestimate d vs. d
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27Penn ESE535 Spring 2013 -- DeHon
SSTA vs. Corner Models
• STA with corners predicts 225ps
• SSTA predicts 162ps at 3
• SSTA reduces pessimism by 28%
Source: IBM, TRCAD 2006
[Slide composed by Nikil Mehta]
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28Penn ESE535 Spring 2013 -- DeHon
Phenomena 2: Parallel Paths
• Cycle time limited by slowest path• Tcycle = max(Tp0,Tp1,Tp2,…Tp(n-1))
• P(Tcycle<T0) = P(Tp0<T0)×P(Tp1<T0)…
• = [P(Tp<T0)]n
• 0.5 = [P(Tp<T50)]n
• P(Tp<T50) = (0.5)(1/n)
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29Penn ESE535 Spring 2013 -- DeHon
System Delay
• P(Tp<T50) = (0.5)(1/n)
– N=108 0.999999993• 1-7×10-9
– N=1010 0.99999999993• 1-7×10-11
Pro
babi
lity
Dis
trib
utio
n
Delay
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Gaussian Distribution
Penn ESE535 Spring 2013 -- DeHon 30
From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg
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31Penn ESE535 Spring 2013 -- DeHon
System Delay
• P(Tp<T50) = (0.5)(1/n)
– N=108 0.999999993• 1-7×10-9
– N=1010 0.99999999993• 1-7×10-11
• For 50% yield want– 6 to 7 s– T50=Tmean+7spath
Pro
babi
lity
Dis
trib
utio
n
Delay
![Page 32: Penn ESE535 Spring 2013 -- DeHon 1 ESE535: Electronic Design Automation Day 24: April 22, 2015 Statistical Static Timing Analysis.](https://reader034.fdocuments.in/reader034/viewer/2022051401/56649f395503460f94c55cdc/html5/thumbnails/32.jpg)
32Penn ESE535 Spring 2013 -- DeHon
System Delay
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33Penn ESE535 Spring 2013 -- DeHon
System Delay
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34Penn ESE535 Spring 2013 -- DeHon
Corners Misleading
[Orshansky+Keutzer DAC 2002]
Phenomena 2
Phenomena 1
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35Penn ESE535 Spring 2013 -- DeHon
Source: Noel Menezes, Intel ISPD2007
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36Penn ESE535 Spring 2013 -- DeHon
But does worst-case mislead?
• STA with worst-case says these are equivalent:
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37Penn ESE535 Spring 2013 -- DeHon
But does worst-case mislead?• STA Worst case delay for this?
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38Penn ESE535 Spring 2013 -- DeHon
But does worst-case mislead?• STA Worst case delay for this?
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39
Does Worst-Case Mislead?
• Delay of off-critical path may matter
• Best case delay of critical path?
• Wost-case delay of non-critical path?
Penn ESE535 Spring 2013 -- DeHon
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40Penn ESE535 Spring 2013 -- DeHon
Probability of Path Being Critical
[Source: Intel DAC 2005]
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41Penn ESE535 Spring 2013 -- DeHon
What do we need to do?
• Ideal: – Compute PDF for delay at each gate– Compute delay of a gate as a PDF from:
• PDF of inputs• PDF of gate delay
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42Penn ESE535 Spring 2013 -- DeHon
Delay Calculation
AND rules
Day 23
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43Penn ESE535 Spring 2013 -- DeHon
What do we need to do?
• Ideal: – compute PDF for delay at each gate– Compute delay of a gate as a PDF from:
• PDF of inputs• PDF of gate delay
– Need to compute for distributions• SUM• MAX (maybe MIN)
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44
For Example
• Consider entry:– MAX(u1,u2)+d
Penn ESE535 Spring 2013 -- DeHon
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45
MAX• Compute MAX of two input distributions
– Preclass 2(b)
Penn ESE535 Spring 2013 -- DeHon
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46
SUM
• Add that distribution to gate distribution.
Penn ESE535 Spring 2013 -- DeHon
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47
Continuous
• Can roughly carry through PDF calculations with Guassian distributions rather than discrete PDFs
Penn ESE535 Spring 2013 -- DeHon
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48Penn ESE535 Spring 2013 -- DeHon
Dealing with PDFs
• Simple model assume all PDFs are Gaussian – Model with mean, s– Imperfect
• Not all phenomena are Gaussian• Sum of Gaussians is Gaussian• Max of Gaussians is not a Gaussian
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49Penn ESE535 Spring 2013 -- DeHon
MAX of Two Identical Gaussians
• Max of Gaussians is not a Gaussian
• Can try to approximate as Guassian
• Given two identical Gaussians A and B with and
• Plug into equations• E[MAX(A,B)] = + /()1/2
• VAR[MAX(A,B)] = 2 – /
[Source: Nikil Mehta]
![Page 50: Penn ESE535 Spring 2013 -- DeHon 1 ESE535: Electronic Design Automation Day 24: April 22, 2015 Statistical Static Timing Analysis.](https://reader034.fdocuments.in/reader034/viewer/2022051401/56649f395503460f94c55cdc/html5/thumbnails/50.jpg)
50Penn ESE535 Spring 2013 -- DeHon
More Technicalities
• Correlation– Physical on die– In path (reconvergent fanout)
• Makes result conservative– Gives upper bound– Can compute lower
2
3
1 4
Graphics from: Noel Menezes (top) and Nikil Mehta (bottom)
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51Penn ESE535 Spring 2013 -- DeHon
Max of Gaussians with Correlation
• Max of identical Gaussians
[Blaauw et al. TRCAD v27n4p589]
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52Penn ESE535 Spring 2013 -- DeHon
MAX of Two Identical Gaussians
• Given two identical Gaussians A and B with and
• Plug into equations• E[MAX(A,B)] = + /()1/2
• VAR[MAX(A,B)] = 2 – /
[Source: Nikil Mehta]
Extreme of correlated: is just the input Gaussian
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53Penn ESE535 Spring 2013 -- DeHon
SSTA vs. Monte Carlo Verification Time
Source: IBM, TRCAD 2006
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54Penn ESE535 Spring 2013 -- DeHon
Using SSTA in FPGA CAD
• Kia– FPGA2007– Route with
SSTA
• Le Hei– FPGA2007– SSTA Synthesis,
Place, Route
[Slide composed by Nikil Mehta]
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55Penn ESE535 Spring 2013 -- DeHon
Impact of SSTA in High-Level Synthesis
• Scheduling and provisioning – ALU/MUL s=5% tnominal
[Jung&Kim ICCAD2007]
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56Penn ESE535 Spring 2013 -- DeHon
Summary
• Nanoscale fabrication is a statistical process• Delays are PDFs• Assuming each device is worst-case delay is
too pessimistic– Wrong prediction about timing– Leads optimization in wrong direction
• Reformulate timing analysis as statistical calculation
• Estimate the PDF of circuit delays• Use this to drive optimizations
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57Penn ESE535 Spring 2013 -- DeHon
Big Ideas:
• Coping with uncertainty• Statistical Reasoning and Calculation
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58Penn ESE535 Spring 2013 -- DeHon
Admin
• Reading for Monday on canvas• Milestone Thursday