Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital...
-
Upload
louisa-flowers -
Category
Documents
-
view
216 -
download
0
Transcript of Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital...
![Page 1: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/1.jpg)
Penn ESE370 Fall2012 -- DeHon1
ESE370:Circuit-Level
Modeling, Design, and Optimization for Digital Systems
Day 36: December 7, 2012
Transmission Line Scenarios
Repeaters in Wiring
![Page 2: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/2.jpg)
Previously
• Transmission line (LC wire) reflection
• Unbuffered RC wire delay scales as L2
– 0.5 Rwire Cwire
– 0.5 L2 Ru Cu
Penn ESE370 Fall2012 -- DeHon2
![Page 3: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/3.jpg)
Today
• Transmission Line Scenarios
• RC (on-chip) Interconnect Buffering
Penn ESE370 Fall2012 -- DeHon3
![Page 4: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/4.jpg)
Transmission Line
• Data travels as waves
• Line has Impedance
• May reflect at end of line
Penn ESE370 Fall2012 -- DeHon4
€
ViR − Z0
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vr
€
Vi2R
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vt
€
w =1
LC=
c0
ε rμ r
€
Z0 =L
C
![Page 5: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/5.jpg)
Impedance Change
• What happens if there is an impedance change in the wire? Z0=75, Z1=50– What reflections and transmission do we get?
Penn ESE370 Fall2012 -- DeHon5
![Page 6: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/6.jpg)
Z0=75, Z1=50
• At junction: – Reflects
• Vr=(50-75)/(50+75)Vi
– Transmits• Vt=(100/(50+75))Vi
Penn ESE370 Fall2012 -- DeHon6
€
ViR − Z0
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vr
€
Vi2R
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vt
![Page 7: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/7.jpg)
Impedance Change Z0=75, Z1=50
Penn ESE370 Fall2012 -- DeHon7
![Page 8: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/8.jpg)
What happens at branch?
Penn ESE370 Fall2012 -- DeHon8
![Page 9: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/9.jpg)
Branch
• Transmission line sees two Z0 in parallel
– Looks like Z0/2
Penn ESE370 Fall2012 -- DeHon9
![Page 10: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/10.jpg)
Z0=50, Z1=25
• At junction: – Reflects
• Vr=(25-50)/(25+50)Vi
– Transmits• Vt=(50/(25+50))Vi
Penn ESE370 Fall2012 -- DeHon10
€
ViR − Z0
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vr
€
Vi2R
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vt
![Page 11: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/11.jpg)
End of Branch
• What happens at end?
• If ends in matched, parallel termination– No further reflections
Penn ESE370 Fall2012 -- DeHon11
![Page 12: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/12.jpg)
Branch Simulation
Penn ESE370 Fall2012 -- DeHon12
![Page 13: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/13.jpg)
Branch with Open Circuit?
• What happens if branch open circuit?
Penn ESE370 Fall2012 -- DeHon13
![Page 14: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/14.jpg)
Branch with Open Circuit
• Reflects at end of open-circuit stub
• Reflection returns to branch– …and encounters branch again– Send transmission pulse to both
• Source and other branch
• Sink sees original pulse as multiple smaller pulses spread out over time
Penn ESE370 Fall2012 -- DeHon14
![Page 15: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/15.jpg)
Open Branch Simulation
Penn ESE370 Fall2012 -- DeHon15
![Page 16: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/16.jpg)
Open Branch Simulation
Penn ESE370 Fall2012 -- DeHon16
![Page 17: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/17.jpg)
Bus
• Common to have many modules on a bus– E.g. PCI slots– DIMM slots for memory
• High speed bus lines are trans. lines
Penn ESE370 Fall2012 -- DeHon17
http://en.wikipedia.org/wiki/File:DIMMs.jpg
![Page 18: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/18.jpg)
Multi-drop Bus
• Ideal– Open circuit, no load
Penn ESE370 Fall2012 -- DeHon18
![Page 19: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/19.jpg)
Multi-Drop Bus
• Impact of capacitive load (stub) at drop?– If tight/regular enough, change Z of line
Penn ESE370 Fall2012 -- DeHon19
€
Z0 =L
C
![Page 20: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/20.jpg)
Multi-Drop Bus
• Long wire stub?– Looks like branch
• may produce reflections
Penn ESE370 Fall2012 -- DeHon20
![Page 21: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/21.jpg)
Transmission Line Noise
• Frequency limits
• Imperfect termination
• Mismatched segments/junctions/vias/connectors
• Loss due to resistance in line– Limits length
Penn ESE370 Fall2012 -- DeHon21
![Page 22: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/22.jpg)
Idea
• Transmission lines – high-speed– high throughput– long-distance signaling
• Termination
• Signal quality
Penn ESE370 Fall2012 -- DeHon22
€
w =1
LC=
c0
ε rμ r
€
Z0 =L
C
€
Vr =ViR − Z0
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟
![Page 23: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/23.jpg)
Back to RC Wire
(on-chip, no L)
Penn ESE370 Fall2012 -- DeHon23
![Page 24: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/24.jpg)
Delay of Wire
• Long Wire: 1mm
• Rwire = 60K for the 1mm)
• Cwire = 0.16 pF for the 1mm)
• Driven by inverter– R0 = 25K
– C0 = 0.01 fF
– Assume velocity saturated, sized Wp=Wn=1
• Loaded by identical inverter
Penn ESE370 Fall2012 -- DeHon24
![Page 25: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/25.jpg)
Formulate Delay
€
Rbuf × Cself +Cwire +Cload( ) + 0.5Rwire ×Cwire + Rwire ×Cload
Penn ESE370 Fall2012 -- DeHon25
Delay of inverter driving wire?
Should be able to do these calculations on final.
![Page 26: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/26.jpg)
Calculate Delay
• Cload = 2 C0
• Rbuf = R0
• Cself = 2 C0 = 2 C0
Penn ESE370 Fall2012 -- DeHon26
€
Rbuf × Cself +Cwire +Cload( ) + 0.5Rwire ×Cwire + Rwire ×Cload
![Page 27: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/27.jpg)
Buffer Middle
• Delay if add buffer to middle of wire?
Penn ESE370 Fall2012 -- DeHon27
Should be able to do these calculations on final.
![Page 28: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/28.jpg)
Formulate and Calculate Delay
Penn ESE370 Fall2012 -- DeHon28
€
2 Rbuf × Cself +Cwire
2+Cload
⎛
⎝ ⎜
⎞
⎠ ⎟+ 0.5
Rwire2
×Cwire
2
⎛
⎝ ⎜
⎞
⎠ ⎟+Rwire
2×Cload
⎛
⎝ ⎜
⎞
⎠ ⎟
![Page 29: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/29.jpg)
N Buffers
• Delay for N buffers?
Penn ESE370 Fall2012 -- DeHon29
€
N Rbuf × Cself +CwireN
+Cload ⎛
⎝ ⎜
⎞
⎠ ⎟+ 0.5
RwireN
×CwireN
⎛
⎝ ⎜
⎞
⎠ ⎟+RwireN
×Cload ⎛
⎝ ⎜
⎞
⎠ ⎟
€
N × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + 0.5Rwire ×Cwire
N
⎛
⎝ ⎜
⎞
⎠ ⎟+ Rwire ×Cload
![Page 30: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/30.jpg)
Minimize Delay
• How minimize delay?
• Differentiate &Solve for N:
Penn ESE370 Fall2012 -- DeHon30
€
N = 0.5Rwire ×Cwire
Rbuf × Cself +Cload( )
⎛
⎝
⎜ ⎜
⎞
⎠
⎟ ⎟
€
2 0.5Rwire ×Cwire × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + Rwire ×Cload
€
N × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + 0.5Rwire ×Cwire
N
⎛
⎝ ⎜
⎞
⎠ ⎟+ Rwire ×Cload
Equalizes delay in buffer and wire
![Page 31: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/31.jpg)
Calculate: Delay at Optimum Stages for Example
• Rwire = 60K for the 1mm)
• Cwire = 0.16 pF for the 1mm)
• Rbuf=R0 = 25K
• Cself=Cload=2(C0 = 0.01 fF)=0.02fF
Penn ESE370 Fall2012 -- DeHon31
€
2 0.5Rwire ×Cwire × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + Rwire ×Cload
![Page 32: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/32.jpg)
Segment Length
• Rwire = L×Runit
• Cwire = L×Cunit
Penn ESE370 Fall2012 -- DeHon32
€
N = 0.5Rwire ×Cwire
Rbuf × Cself +Cload( )
⎛
⎝
⎜ ⎜
⎞
⎠
⎟ ⎟
€
N = L 0.5Ru ×Cu
Rbuf × Cself +Cload( )
⎛
⎝
⎜ ⎜
⎞
⎠
⎟ ⎟
![Page 33: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/33.jpg)
Optimal Segment Length
• Delay scales linearly with distance once optimally buffered
Penn ESE370 Fall2012 -- DeHon33
€
N = L 0.5Ru ×Cu
Rbuf × Cself +Cload( )
⎛
⎝
⎜ ⎜
⎞
⎠
⎟ ⎟
€
Lseg* =
L
N= 2
Rbuf × Cself +Cload( )
Ru ×Cu
⎛
⎝
⎜ ⎜
⎞
⎠
⎟ ⎟
![Page 34: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/34.jpg)
Buffer Size?
• How big should buffer be?– Rbuf = R0/W
– Cload = 2 W C0 (assuming velocity saturation)
– Cself = 2 W C0
Penn ESE370 Fall2012 -- DeHon34
€
2 0.5Rwire ×Cwire × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + Rwire ×Cload
€
2 0.5Rwire ×Cwire ×R0
W× 1+γ( )2WC0 +
R0
W×Cwire + Rwire × 2WC0
![Page 35: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/35.jpg)
Implication W
• Rwire = L×Runit
• Cwire = L×Cunit
W independent of Length– Depends on technology
Penn ESE370 Fall2012 -- DeHon35
€
W =R0 ×CwireRwire × 2C0
![Page 36: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/36.jpg)
Delay at Optimum W
• With =1, 1+=2
• Same size as first term
Penn ESE370 Fall2012 -- DeHon36
€
2 0.5Rwire ×Cwire × R0 × 1+γ( )2C0 + 2 R0 ×Cwire × Rwire × 2C0
€
4 R0 ×Cwire × Rwire × 2C0
![Page 37: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/37.jpg)
Ideas
• Wire delay linear once buffered
• Optimal buffering matches– Buffer delay– Delay on wire between buffers
Penn ESE370 Fall2012 -- DeHon37
![Page 38: Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.](https://reader035.fdocuments.in/reader035/viewer/2022062407/56649e245503460f94b1302c/html5/thumbnails/38.jpg)
Admin
• Final – Friday 12/14, noon, Moore 212
• Review – Wednesday, 12/12– Evening – time announced on piazza
• Andre out of town until Friday
Penn ESE370 Fall2012 -- DeHon38