Pei-Ci Wu Martin D. F. Wong On Timing Closure: Buffer Insertion for Hold-Violation Removal DAC’14.
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Transcript of Pei-Ci Wu Martin D. F. Wong On Timing Closure: Buffer Insertion for Hold-Violation Removal DAC’14.
![Page 1: Pei-Ci Wu Martin D. F. Wong On Timing Closure: Buffer Insertion for Hold-Violation Removal DAC’14.](https://reader035.fdocuments.in/reader035/viewer/2022070323/56649d825503460f94a677a8/html5/thumbnails/1.jpg)
Pei-Ci Wu
Martin D. F. Wong
On Timing Closure: Buffer Insertion for Hold-ViolationRemoval
DAC’14
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Outline
Introduction Preliminaries Linear Programming Based
Optimization Bottom-up Buffer Insertion Experimental Results Concluding Remarks
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Introduction
Timing closure, which is to satisfy the timing constraints, is a key problem in the physical design
Setup (long-path) constraints ensure that the signal transitions do not arrive
too late hold-time (short-path) constraints
ensure that the signal transitions do not arrive too early
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Typically, hold violations are addressed after setup optimization has been performed.
Discrete cell sizes (i.e. discrete buffer sizes for hold optimization) in modern industrial designs
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Cell libraries specified for the setup constraints and the hold-time constraints are usually different in modern industrial designs
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Preliminaries
Negative setup slacks and negative hold slacks indicate setup violations and hold violations
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TNS the absolute value of the total negative setup
slacks of all the pins in PO THS
the absolute value of the total negative hold slacks of all the pins in PO
TNS must not be worsen during hold-violation removal
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Given: a design and a buffer library,
find a buffering solution such that: THS and the cost of buffering (i.e. area and
power consumption) are both minimized while TNS is not worsen.
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Linear Programming Based Optimization
Inserting delay into wires to remove hold violations A linear programming formulation Extend such formulation for the complex timing
constraints Graph-reduction approach
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Input Combinational circuit C* s.t. for any pin p of C*,
hold_slackp < 0 and setup_slackp > 0 C* can then be represented as a directed
acyclic graph G(V,E) V is the pins of C* (i, j) ∈ E represents an edge
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I : the zero in-degree pins O : the zero out-degree pins for each pin i in V
three real-value variables, xi(delays inserted at pin i for hold-time constraints), hai, and sai
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Hold-time constraints
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For buffer library characterization is necessary in order to get an empirical ratio such that
we assume that the buffer only affects the driver cell and the sink cells of the buffer
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Delays introduced by inserting the buffer is
(a) (b)
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Setup constraints
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Objective :
The setup constraints limit the delays that can be inserted
ri is only necessary when there is no feasible solution
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Some pins with positive setup slacks and positive hold slacks that are not included
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Graph Reduction
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Bottom-up Buffer Insertion
Given: a pin i, hold delay DH and setup delay DS
Find a buffering solution at pin i from a buffer library B: hold delays introduced by the chosen buffers are
as close to DH
setup delays introduced by the chosen buffers are not larger than DS
Minimize the area of the chosen buffers
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DP based algorithm A set of buffering candidates C(L, dh, ds, A)
is kept during the process For each buffer in B, we insert it to any of
the existing candidates
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New buffering candidates (1) if d′s > DS, C′ is removed immediately (2) if d′h <= dh, C′ is removed as well
d′h > DH + margin where margin is a parameter, then C′ is removed too
(3) C′ is dominated by any existing candidate C*(I*, d*h, d*s, A*) if d′h < d*h and A′ > A*
Chose the candidate that has the largest ratio of dh/A as the buffering solution
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Bottom-up Methodology process the pins by the bottom-up topological
ordering (i.e. from PO to PI) DP algorithm cannot realize the exact
amount of hold delays/setup delays by inserting buffers(extra delays)
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Suppose now we are processing pin p, collected extra delays cur_setup_reqp = setup_reqp − ds_delay extra delays = cur_setup_reqp – sap
Ds = xp + cur_setup_reqp − sap
Similarly to get Dh
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Optimization Flow
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Experimental Results
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Concluding Remarks
First propose a linear programming based approach that minimizes the number of inserted delays
A bottom-up buffer insertion and the flow of optimizing are presented