[AKD4145-A]

Evaluation board Rev.3 for AK4145AKD4145-A

GENERAL DESCRIPTION

The AKD4145 is an evaluation board for the AK4145, BTSC Encoder with D/A Converter, which is optimized for Digital AV application. The AKD4145 has the analog/digital audio interface and can achieve the interface with analog/digital audio systems via BNC/OPT-connector.

Ordering guide

AKD4145-A --- Evaluation board for AK4145 (Cable for connecting with printer port of IBM-AT,compatible PC and control software are packed with this. This control software does not support Windows NT.)

FUNCTION

• ADC with analog input • DIR with optical input • 10pin Header for digital audio I/F and serial control I/F

Opt In

Logic1 (3.3V)

AK4145 (Encoder)

COAX

Regulator

Composite Audio

Serial Control

X’tal

T1:5V=>3.3V T2:3.3V=>1.8V T3:12V=>5V

Video / 27M

PORT2

DSP DATA

PORT1

AK4114 (DIR)

AK5357 (ADC)

AINL

AINR

12V 5V

For OP-Amp

Logic2 (3.3V~1.8V)

DGND (0V)

AGND (0V)

AVDD (3.3V)

DVDD (1.8V)

TVDD (3.3V~1.8V)

For 74AVC8T245 74HC14 74LVC07 AK4114

OP-Amp

Figure. 1 AKD4145 Block Diagram

* Circuit diagram and PCB layout are attached at the end of this manual

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Evaluation Board Manual

Operation sequence

1) Set up the power supply lines. (1-1) In case of using the regulator.<Default> Set up the jumper pins.

JP13 JP14 JP15 JP17 JP18 JP22 JP23 JP AVDD-SEL DVDD-SEL TVDD-SEL Logic2-SEL Logic1-SEL 5V-REG 3.3V-REG

State REG(3.3V) REG(1.8V) REG(3.3V) TVDD REG(3.3V) Short REG(3.3V) Set up the power supply lines.

[REG(12V)] (red) = +12V : for regulator and OP-Amp [REG(5V)] (red) = open : “5V” is supplied from Regulator (T3) [AVDD] (orange) = open : “3.3V” is supplied from Regulator (T1) [DVDD] (orange) = open : “1.8V” is supplied from Regulator (T2) [TVDD] (orange) = open : “3.3V” is supplied from Regulator (T1) [Logic1] (orange) = open : “3.3V” is supplied from Regulator (T1) [Logic2] (orange) = open : “3.3V” is supplied from Regulator (T1) [AGND] (black) = 0V : analog ground [DGND] (black) = 0V : digital ground (Note) VA and VD of AK5357 (ADC) is supplied “3.3V” from regulator (T1).

(1-2) In case of using the power supply connectors.

Set up the jumper pins.

JP13 JP14 JP15 JP17 JP18 JP22 JP23 JP AVDD-SEL DVDD-SEL TVDD-SEL Logic2-SEL Logic1-SEL 5V-REG 3.3V-REG

State TM TM TM TM TM Open TM

Set up the power supply lines.

[REG(12V)] (red) = +12V : for OP-Amp [REG(5V)] (red) = +5V : for regulator (T1, T2) [AVDD] (orange) = +2.7~3.6V : for AVDD of AK4145 (typ. 3.3V) [DVDD] (orange) = +1.7~1.9V : for DVDD of AK4145 (typ. 1.8V) [TVDD] (orange) = +1.7~3.6V : for TVDD of AK4145 (typ. 3.3V) [Logic1] (orange) = +2.7~3.6V : for logic (typ. 3.3V) [Logic2] (orange) = +1.7~3.6V : for logic of I/F (typ. 3.3V : the voltage same as TVDD) [AGND] (black) = 0V : analog ground [DGND] (black) = 0V : digital ground (Note) VA and VD of AK5357 (ADC) is supplied “3.3V” from regulator (T1).

2) Set up the jumper pins and switches. (See the followings.) 3) Power on. SW1 (AK4145), SW2 (ADC) and SW3 (DIR) should be reset once bringing toggle SW “L” upon

power-up. Please refer to Talble.1 on page.3 about setting of toggle SW.

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Setting of the toggle SW

No. Name Function

SW1 PDN-AK4145 PDN SW of AK4145 (U2). Keep “H” during normal operation.

SW2 PDN-ADC PDN SW of AK5357 (U1). Keep “H” during normal operation. Keep “L” when AK5357 is not used.

SW3 PDN-DIR PDN SW of AK4114 (U4). Keep “H” during normal operation. Keep “L” when AK4114 is not used.

Table. 1 Setting of the toggle SW

Indication for LED

[LED1] (INT) : Monitor INT0 pin of the DIR (AK4114). LED turns on when PLL of the AK4114 is unlocked.

Setting of jumper pins

No Name Function

1 Serial AK4145 Control Mode Open : Parallel Control. <Default> Short : Serial Control.

2 AMP Output of OP-Amp Open : Out of use. Short : Connected. <Default>

3 CA Output of CA THR : Out of use. AMP : Amplify CA with OP-Amp <Default>

4 I2S Audio I/F of AK5357 (ADC) Open : 24bit MSB justified. Short : 24bit I2S Compatible. <Default>

6 RX RX input of AK4114 (DIR) OPT : Optical (PORT1). <Default> BNC : BNC RX (J6).

7 DIF/SCL Selection of AK4145’s DIF/SCL pin DIF: DIF in parallel mode. <Default> SCL:SCL in serial mode.

8 FS/SDA Selection of AK4145’s FS/SDA pin FS: FS in parallel mode. <Default> SDA : SDA in serial mode.

9 DIR-SDTI Input of AK4145’s SDTI Open : PORT2. SDTI : DIR. <Default>

10 DIR-LRCK Input of AK4145’s LRCK Open : PORT2. Short : DIR. <Default>

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11 DIR-BICK Input of AK4145’s BICK Open : PORT2. Short : DIR. <Default>

12 DIR-MCLK Input of AK4145’s MCLK Open : PORT2. Short : DIR. <Default>

13 AVDD-SEL Power supply of AK4145’s AVDD REG(3.3V) : AVDD is supplied from regulator (T1). <Default> TM : AVDD is supplied from “AVDD” connector.

14 DVDD-SEL Power supply of AK4145’s DVDD REG(1.8V) : DVDD is supplied from regulator (T2). <Default> TM : DVDD is supplied from “DVDD” connector.

15 TVDD-SEL Power supply of AK4145’s TVDD DVDD : TVDD is supplied from DVDD. <Default> REG(3.3V) : TVDD is supplied from regulator (T1). TM : TVDD is supplied from “TVDD” connector.

16 GND Analog GND and Digital GND Open : Separated. Short : Common. <Default>

17 Logic2-SEL Power supply of logic2 TVDD: Logic2 is supplied from TVDD. <Default> TM : Logic2 is supplied from “Logic2” connector.

18 Logic1-SEL Power supply of logic1 REG(3.3V) : Logic1 is supplied from regulator (T1). <Default> TM : Logic1 is supplied from “Logic1” connector.

22 5V-REG Power supply of regulator (T1) Open : It is supplied from “REG-5V” connector. Short : It is supplied from regulator (T3). <Default>

23 3.3V-REG Power supply of regulator (T2) REG(3.3V) : It is supplied from regulator (T3). <Default> TM : It is supplied from “REG-5V” connector.

Table. 2 Setting of jumper pins

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Evaluation mode Control Mode The supporting control mode is as follows. 1. Parallel Mode <Default> 2. Serial Mode 1. Parallel Mode <Default>

(1-1) Set up the jumper pins. JP8

FS/SDA

SDAFS

JP7 SCL/DIF

DIF SCL

JP1 Serial

(1-2) Set up the DIP SW (S3).

S3 DIF ( Audio I/F ) FS ( Sampling Rate )

L 24bit MSB Justified 32kHz

H 16/24bit I2S Compatible <Default> 48kHz <Default>

Table. 3 Setting of AK4145’s Parallel Mode

2. Serial Mode

(2-1) Set up the jumper pins.

JP8FS/SDA

SDAFS

JP7 SCL/DIF

DIF SCL

JP1 Serial

(2-2) Connect of the 10 wire flat cable.

The AK4145 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (CTRL) with PC by 10 wire flat cable packed with the AKD4145.

PORT3

uP I/F 6

5

10

1

NC

CD

TO

CD

TI

CC

L KC

SN

GN

D

GN

D

GN

D

GN

D

GN

D

Red

Figure. 2 Connect of 10 wire flat cable

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Measurement Mode The supporting measurement mode is as follows. 1. Evaluation using DIR of AK4114 <Default> 2. Evaluation using ADC of AK5357 3. All interface signals are fed externally 1. Evaluation using DIR of AK4114 <Default>

Measurement path : Optical connector (PORT1) or BNC (J6) → DIR (AK4114) → AK4145

Please supply biphase signal to Optical connector (PORT1) or BNC connector (J6). DIR generates MCLK, BICK,

LRCK, and SDTI from received data.

(1-1) Set up the jumper pins. JP6 (RX) should be set according to the RX input. Follow is setting example in Optical connector.

JP9 DIR-SDTI

BNCOPT

JP6 RX

JP10DIR-LRCK

JP11DIR-BICK

JP12DIR-MCLK

(1-2) Set up the DIP SW (S2).

In case of the AK4145 evaluation using the AK4114, it is necessary to correspond to the audio interface format for AK4145 (SDTI) and AK4114 (SDTO). About AK4145’s audio interface format, refer to datasheet of AK4145. About AK4114’s audio interface format, refer to Table. 6 on page 8. (Note) AK4145’s default setting of Audio interface format is I2S Compatible in parallel mode.

DIF0L

S2 DIR-Setting

H

DIF1 DIF2 OCKS1 CM0

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2. Evaluation using ADC of AK5357

Measurement path : AINL(J3) / AINR (J2) → ADC (AK5357) → DIR (AK4114) → AK4145

Please supply analog signal to AINL (J3) / AINR (J2). DIR generates MCLK, BICK, LRCK, and SDTI from

received data via AK5357’s ADC. X’tal (12.288MHz) on the board is used as AK4114’s reference clock.

(2-1) Set up the jumper pins.

JP4 is setting of AK5357‘s Audio interface format. In case of the AK5357 evaluation using the AK4114, it is necessary to correspond to the audio interface format for AK5357 (SDTO) and AK4114 (DAUX). About AK5357’s audio interface format, refer to Table. 4 on this page. About AK4114’s audio interface format, refer to Table. 6 on page 8. (Note) AK5357’s default setting of Audio interface format is I2S Compatible.

JP4 I2S

Open 24bit MSB Justified Short I2S Compatible <Default>

Table. 4 ADC Output Audio Interface Format Setting

(2-2) Set up the DIP SW (S2).

In case of the AK4145 evaluation using the AK4114, it is necessary to correspond to the audio interface format for AK4145 (SDTI) and AK4114 (SDTO). About AK4145’s audio interface format, refer to datasheet of AK4145. About AK4114’s audio interface format, refer to Table. 6 on page 8. (Note) AK4145’s default setting of Audio interface format is I2S Compatible in parallel mode.

3. All interface signals are fed externally

Measurement path : PORT2 → AK4145

Please supply MCLK, BICK, LRCK and SDTI to PORT2.

(3-1) Set up the jumper pins.

JP9 DIR-SDTI

BNCOPT

JP6 RX

JP10DIR-LRCK

JP11DIR-BICK

JP12DIR-MCLK

JP4 I2S

DIF0L

S2 DIR-Setting

H

DIF1 DIF2 OCKS1 CM0

JP9 DIR-SDTI

JP10DIR-LRCK

JP11 DIR-BICK

JP12DIR-MCLK

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Setting of DIP SW No. Name ON (“H”) OFF (“L”) Default

1 DIF0 H

Table. 5 AK4114 Mode Setting

DIF2 DIF1 DIF0 DAUX SDTO LRCK BICK

0 0 0 24bit, Left justified 16bit, Right justified H/L 64fs 0 0 1 24bit, Left justified 18bit, Right justified H/L 64fs 0 1 0 24bit, Left justified 20bit, Right justified H/L 64fs 0 1 1 24bit, Left justified 24bit, Right justified H/L 64fs 1 0 0 24bit, Left justified 24bit, Left justified H/L 64fs 1 0 1 24bit, I2S 24bit, I2S L/H 64fs

Table. 6 AK4114 Audio Data Format

OCKS1 MCKO1

L 256fs H 512fs

Table. 7 AK4114 Master Clock Output Frequency

CM0 PLL Clock Souce SDTO

L ON PLL RX H OFF X’tal DAUX

Table. 8 AK4114 Clock Operation Mode

2 DIF1 L 3 DIF2

Output Audio Interface Format : refer to Table. 6 H

4 OCKS1 Master Clock Frequency Setting : refer to Table. 7 L 5 CM0 Clock Mode Setting : refer to Table. 8 L

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Baseband Composite Audio signal output circuit

THR

C570.1u

+C58 22u

+C5610u

VR150k

13

2

AMP

C590.1u

R3747k

12V

+C6010u

R3847k

Baseband Composite AudioC3 22u

JP3 CA R36 10k

U10

NJM4580

AOUT1

+VP8

-AIN2

BOUT7

+AIN3

-VP4

-BIN6

+BIN5

JP2AMP

C4open

R4647k

R2220

J4CA

Figure. 3 Baseband Composite Audio signal output circuit

1. In case of amplification using the OP-Amp. <Default> The stereo separation can be maximized by adjusting the variable resistor (VR1).

The jumper pins should be set as follows.

JP2 AMP

JP3 CA

AMP THR

2. In case of through.

This mode is out of use.

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Control Software Manual

Set-up of evaluation board and control software

1. Set up the AKD4145-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4145-A by 10-line type flat cable (packed with AKD4145-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software

is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.)

3. Insert the CD-ROM labeled “AK4145-A Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd4145.exe” to set up the control program. 5. Then please evaluate according to the follows.

Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. 3. Click “Write default” button

Explanation of each buttons

[Port Reset] : Set up the USB interface board (AKDUSBIF-A) . [Write default] : Initialize the register of AK4145. [All Write] : Write all registers that is currently displayed. [All Read] : Read all registers of the AK4145. [Function1] : Dialog to write data by keyboard operation. [Function2] : Dialog to write data by keyboard operation. [Function3] : The sequence of register setting can be set and executed. [Function4] : The sequence that is created on [Function3] can be assigned to buttons and executed. [Function5]: The register setting that is created by [SAVE] function on main window can be assigned to

buttons and executed. [SAVE] : Save the current register setting. [OPEN] : Write the saved values to all register. [Write] : Dialog to write data by mouse operation. [Read]: Dialog to read data by mouse operation.

Indication of data

Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet.

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Explanation of each dialog 1. [Write Dialog] : Dialog to write data by mouse operation

There are dialogs corresponding to each register.

Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”.

If you want to write the input data to AK4145, click [OK] button. If not, click [Cancel] button.

2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Input registers address in 2 figures of hexadecimal. Data Box: Input registers data in 2 figures of hexadecimal.

If you want to write the input data to AK4145, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate DVOL

Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4145 by this interval. Step Box: Data changes by this step. Mode Select Box:

If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09

Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09

Data flow: 00 01 02 03 04 05 06 07 08 09

If you want to write the input data to AK4145, click [OK] button. If not, click [Cancel] button.

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4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. <Operation flow> (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”. 4-2. [Open] The register setting data saved by [Save] is written to AK4145. The file type is the same as [Save]. <Operation flow> (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button.

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5. [Function3 Dialog] The sequence of register setting can be set and executed.

(1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.

This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is “aks”.

Figure. 4 Window of [F3]

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6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure. 5 opens.

Figure. 5 [F4] window

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6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure. 6

Figure. 6 [F4] window (2)

(2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The sequence file names can assign be saved. The file name is *.ak4. [OPEN] : The sequence file names assign that are saved in *.ak4 are loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.

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7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure. 7 opens.

Figure. 7 [F5] window

7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure. 8 (2) Click [WRITE] button, then the register setting is executed.

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Figure. 8 [F5] windows(2)

7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded. 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change.

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MEASUREMENT RESULTS [Measurement condition]

• Measurement unit : Audio Precision, System Two Cascade BELAR TV DIGITAL SETEREO MONITOR TVM-230 • MCLK : 256fs • BICK : 64fs • fs : 48kHz • Bit : 24bit • Power Supply : AVDD = TVDD = 3.3V, DVDD = 1.8V • Temperature : Room

[Measurement Results]

Parameter Result (Lch / Rch) Unit Mono -79.5 S/(N+D)

(−1dB Input, 1kHz) Stereo -77.9 / -78.5 dB

Mono -80.9 S/N (Input off, A-weighting) Stereo -81.3 / -81.3 dB

Stereo Separation Stereo 49.4 / 48.5 dB (-1dB Input, 1kHz) [Performance Plots]

Stereo :

Figure. 9 : THD+N vs. Input Level (1kHz) Figure. 10 : THD+N vs. Input Frequency (-15dB) Figure. 11 : Linearity (1kHz) Figure. 12 : Frequency Response (-15dB) Figure. 13 : Separation (Left Channel = Off, Right Channel = -15dB) Figure. 14 : FFT Plot (-1dB) Figure. 15 : FFT Plot (No Signal)

Mono :

Figure. 16 : THD+N vs. Input Level (1kHz) Figure. 17 : THD+N vs. Input Frequency (-15dB) Figure. 18 : Linearity (1kHz) Figure. 19 : Frequency Response (-15dB) Figure. 20 : FFT Plot (-1dB) Figure. 21 : FFT Plot (No Signal)

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[Stereo]

THD + N vs Input Level

-100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBr A

-100 +0-90 -80 -70 -60 -50 -40 -30 -20 -10dBr

Figure. 9 Stereo mode THD + N vs. Input Level (fin=1kHz)

THD + N vs Input Frequency

-100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBr A

20 10k50 100 200 500 1k 2k 5kHz

Figure. 10 Stereo mode THD + N vs. Input Frequency (-15dB)

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Linearity

-100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBr A

-100 +0-90 -80 -70 -60 -50 -40 -30 -20 -10dBr

Figure. 11 Stereo mode Linearity (fin=1kHz)

AKM Frequency Response

-20

-10

-19

-18

-17

-16

-15

-14

-13

-12

-11

dBr A

20 10k50 100 200 500 1k 2k 5kHz

Figure. 12 Stereo mode Frequency Response (-15dB)

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AKM Stereo Separation (Lch Off, Rch -15dB)

-100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBr A

20 10k50 100 200 500 1k 2k 5kHz

Figure. 13 Stereo Separation (Lch Off, Rch -15dB)

FFT (-1dB)

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

dBr A

20 20k50 100 200 500 1k 2k 5k 10kHz

Figure. 14 Stereo mode FFT Plot (-1dB)

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FFT (No Signal)

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

dBr A

20 20k50 100 200 500 1k 2k 5k 10kHz

Figure. 15 Stereo mode FFT Plot (No Signal)

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[Mono]

THD + N vs Input Level

-100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBr A

-100 +0-90 -80 -70 -60 -50 -40 -30 -20 -10dBr

Figure. 16 Mono mode THD + N vs. Input Level (fin=1kHz)

THD + N vs Input Frequency

-100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBr A

20 10k50 100 200 500 1k 2k 5kHz

Figure. 17 Mono mode THD + N vs. Input Frequency (-15dB)

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Linearity

-100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBr A

-100 +0-90 -80 -70 -60 -50 -40 -30 -20 -10dBr

Figure. 18 Mono mode Linearity (fin=1kHz)

AKM Frequency Response

-20

-10

-19

-18

-17

-16

-15

-14

-13

-12

-11

dBr A

20 10k50 100 200 500 1k 2k 5kHz

Figure. 19 Mono mode Frequency Response (-15dB)

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FFT (-1dB)

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

dBr A

20 20k50 100 200 500 1k 2k 5k 10kHz

Figure. 20 Mono mode FFT Plot (-1dB)

FFT (No Signal)

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

dBr A

20 20k50 100 200 500 1k 2k 5k 10kHz

Figure. 21 Mono mode FFT Plot (No Signal)

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Revision History

Date Manual Board Reason Page Contents (yy/mm/dd) Revision Revision

07/09/07 KM090000 0 First Edition 08/03/10 KM090001 1 Change Device revision was changed. Rev.A → Rev.B

Change 18-25 Table data and Plot data were changed. 08/06/05 KM090002 2 Change Device revision was changed. Rev.B → Rev.C

Change 18-25 Table data and Plot data were changed.

IMPORTANT NOTICE

These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products.

AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein.

Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials.

AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property.

It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.

Change 3-8 Default setting of Audio I/F was changed. MSB Justified → I2S Compatible

08/08/18 KM090003 3 Change 27 Circuit diagram was changed. R47 was added. (P/S pin Pull up)

Change 18-25 Table data and Plot data were changed.

< KM090003> 2008/08 - 26 -

A

A

B

B

C

C

D

D

E

E

E E

D D

C C

B B

A A

ADC-VA

OCKS1

CM0

Logic1

OCKS1CM0

Logic1 Logic2

4145-LRCK

4145-SDTI

Logic2

Logic1

Logic1

Logic2

Logic1

ADC-VA

Logic2

Logic2

XTI

XTO

Logic1

XTIXTO

4145-BICK

4145-MCLK

Logic1

AVDD

DVDD

TVDD

4145-MCLK

4145-LRCK

4145-BICK

4145-SDTI

Logic1

DIR-AVDD

12V

TVDD

Title

Size Document Number Rev

Date: Sheet of

Main 3

AKD4145-AA2

1 2Monday, August 18, 2008

Title

Size Document Number Rev

Date: Sheet of

Main 3

AKD4145-AA2

1 2Monday, August 18, 2008

Title

Size Document Number Rev

Date: Sheet of

Main 3

AKD4145-AA2

1 2Monday, August 18, 2008

RX

OPT

BNC

DIF0DIF1DIF2OCKS1CM0

LRCK

MCLK

VCCSDTI

BICKGNDGND

SCL

SDA (ACK)SDA

PORTDIR

HL

DIFFS

FS

DIF

L H HL

DIRPORT

PORTDIR

DIRPORT

SDA

SCL

SCL

THR

AMP

PORT1

TORX141

PORT1

TORX141OUT 1

VCC 3

GND 2

U10

NJM4580

U10

NJM4580

AOUT1

-AIN2

+AIN3

-VP4

+VP 8

BOUT 7

-BIN 6

+BIN 5

C170.1uC170.1u

AK5357

U1

AK5357

U1

AINR1

AINL2

CKS13

VCOM4

AGND5

VA6

VD7

DGND8

LRCK 10

MCLK 11

SCLK 12

PDN 13

CKS2 15

DIF 14

CKS0 16

SDTO 9

C360.1uC360.1u

+C58 22u+C58 22u

+C3010u +C3010u

U9

74LVC07

U9

74LVC07

1A12A33A54A95A116A13

Vcc14

GND7

1Y 22Y 43Y 64Y 85Y 106Y 12

C320.1uC320.1u

SW3PDN-DIRSW3PDN-DIR

213

R1910kR1910k

D1HSU119D1HSU119

KA

C160.1uC160.1u

R3847kR3847k

+C8open+C8open

L1 47uL1 47u1 2

R41 51R41 51

C350.1uC350.1u

J6BNC RXJ6BNC RX

C290.1uC290.1u

R510kR510k

R39 47kR39 47k

R22 470R22 470

C100.1uC100.1u

J1CV27MJ1CV27M

+C2610u+C2610u

R10

470

R10

470

+C610u +C610u

C380.1uC380.1u

D3HSU119D3HSU119

KA

R4 51R4 51

C340.1uC340.1u

R17

10k

R17

10k

C94.7nC94.7n

C570.1uC570.1u

R33 51R33 51

U3

74HC14

U3

74HC14

1A11Y22A32Y43A53Y6

Vcc14

GND7

4Y 84A 95Y 105A 116Y 126A 13

R1810kR1810k

C70.1uC70.1u

R11 51R11 51

C250.1uC250.1u

R1218kR1218k

+ C50.47u+ C50.47u

C59 0.1uC59 0.1u

R2947kR2947k

+ C220.47u

+ C220.47u

PORT2

DSP

PORT2

DSP

13579 10

8642

R9 51R9 51

JP8

FS/SDA

JP8

FS/SDA

X112.288MHzX112.288MHz

12

RP2

47k

RP2

47k

54321

+ C322u + C322u

JP10

DIR-LRCK

JP10

DIR-LRCK

C140.1uC140.1u

R1410kR1410k

R1610kR1610k

R21 470R21 470

+

C60 10u

+

C60 10u

U8

74AVC8T245

U8

74AVC8T245

A13

A24

A35

A46

A57

A68

A79

A810

B1 21

B2 20

B3 19

B4 18

B5 17

B6 16

B7 15

B8 14

GND11

GND12 GND 13

VCCA1

DIR2

VCCB 24

VCCB 23

OE 22

VR150kVR150k

13

2

R4747kR4747k

R42 51R42 51

R8 51R8 51

R4647kR4647k

LED1INTLED1INT

KA

C23 5pC23 5p

C24

0.1u

C24

0.1u

CN2

16pin_R

CN2

16pin_R

9

10

11

12

13

14

15

16

JP11

DIR-BICK

JP11

DIR-BICK

JP9

DIR-SDTI

JP9

DIR-SDTI

R35.1R35.1

R151kR151k

C21 5pC21 5p

JP2AMPJP2AMP

C120.1uC120.1u

R7 51R7 51

R43 51R43 51

R3047kR3047k

JP6RXJP6RX

S2

DIR-Setting

S2

DIR-Setting

12345

109876

C310.1uC310.1u

R34 51R34 51

C270.1uC270.1u

R32 51R32 51

AK4145

U2

AK4145

U2

FILT1

P/S2

CV27M3

PDN4

MCLK5

LRCK6

BICK7

SDTI8

DIF/SCL 10

TVDD 11

DVDD 12

VSS 13

AVDD 15

VCOM 14

CA 16

FS/SDA 9

U5

74HC14

U5

74HC14

1A11Y22A32Y43A53Y6

Vcc14

GND7

4Y 84A 95Y 105A 116Y 126A 13

PORT3

CTRL

PORT3

CTRL

1357910

8642

R2220R2220

R44 51R44 51

R40100kR40100k

J2AINRJ2AINR

U7

74AVC8T245

U7

74AVC8T245

A13

A24

A35

A46

A57

A68

A79

A810

B1 21

B2 20

B3 19

B4 18

B5 17

B6 16

B7 15

B8 14

GND11

GND12 GND 13

VCCA1

DIR2

VCCB 24

VCCB 23

OE 22

R3747kR3747k

R175R175

C150.1uC150.1u

J4CAJ4CA

R1375R1375

SW2PDN-ADCSW2PDN-ADC

213

R45 51R45 51

JP4I2SJP4I2S

+

C110u

+

C110u

R201kR201k

+C1310u+C1310u

JP7

DIF/SCL

JP7

DIF/SCL

C11 0.1uC11 0.1u

+ C3310u

+ C3310u

J3AINLJ3AINL

JP1SerialJP1Serial

CN1

16pin_L

CN1

16pin_L

1

2

3

4

5

6

7

8

R3610kR3610k

+C5610u+C5610u

C370.1uC370.1u

+ C2010u+ C2010u

C4openC4open

C190.1uC190.1u

U4

AK4114U4

AK4114

IPS0/RX41AVSS2DIF0/RX53TEST24DIF1/RX65AVSS6DIF2/RX77IPS1/IIC8P/SN9XTL010XTL111VIN12

TVD

D13

DV

SS

14TX

015

TX1

16B

OU

T17

CO

UT

18U

OU

T19

VO

UT

20D

VD

D21

DV

SS

22M

CK

O1

23LR

CK

24

SDTO 25BICK 26MCKO2 27DAUX 28XTO 29XTI 30PDN 31CM0/CDTO 32CM1/CDTI 33OCKS1/CCLK 34OCKS0/CSN 35INT0 36

INT1

37A

VD

D38

R39

VC

OM

40A

VS

S41

RX

042

AV

SS

43R

X1

44TE

ST1

45R

X2

46A

VS

S47

RX

348

R23 51R23 51

SW1PDN-4145SW1PDN-4145

213

C280.1uC280.1u

S3

4145-Pararel

S3

4145-Pararel

12

43

JP12

DIR-MCLK

JP12

DIR-MCLK

+

C210u

+

C210u

C180.1uC180.1u

D2HSU119D2HSU119

KA

JP3 CAJP3 CA

- 27 -

A

A

B

B

C

C

D

D

E

E

E E

D D

C C

B B

A A

Logic1

Logic2

AVDD

DVDD

TVDD

ADC-VA

12V

DIR-AVDD

Title

Size Document Number Rev

Date: Sheet of

Main-Power Supply 3

AKD4145-AA3

2 2Monday, August 18, 2008

Title

Size Document Number Rev

Date: Sheet of

Main-Power Supply 3

AKD4145-AA3

2 2Monday, August 18, 2008

Title

Size Document Number Rev

Date: Sheet of

Main-Power Supply 3

AKD4145-AA3

2 2Monday, August 18, 2008

5V-->3.3V

REG(3.3V)

TM

REG(1.8V)

TM

REG(3.3V)TM

DVDD

TVDD

TM

TM

REG(3.3V)

3.3V-->1.8V

12V-->5V

RE

G(3

.3V

)

TM

JP15

TVDD-SEL

JP15

TVDD-SEL

T2LT1963AEST-1.8

T2LT1963AEST-1.8

IN1

GN

D2

OUT 3

C540.1uC540.1u

JP18

Logic1-SEL

JP18

Logic1-SEL

JP14

DVDD-SEL

JP14

DVDD-SEL

L2(short)

L2(short)

12

T1TA48M033F

T1TA48M033F

IN1 OUT 2

GN

D3

R27

(short)

R27

(short)

T3NJM78M05FA

T3NJM78M05FA

OUT 3

GN

D2

IN1

+ C5147u

+ C5147u

12

AVDD1

T45_OR

AVDD1

T45_OR

1

C410.1uC410.1u

JP17

Logic2-SEL

JP17

Logic2-SEL

TVDD1

T45_OR

TVDD1

T45_OR

1

C550.1uC550.1u

JP225V-REGJP225V-REG

JP16GNDJP16GND

R35

(short)

R35

(short)

C400.1uC400.1u

R28

(short)

R28

(short)

+ C4747u

+ C4747u

12

DGND1

T45_BK

DGND1

T45_BK

1

R25

(short)

R25

(short)

AGND1

T45_BK

AGND1

T45_BK

1

C450.1uC450.1u

JP13

AVDD-SEL

JP13

AVDD-SEL

L3

(short)

L3

(short)

1 2

R31

(short)

R31

(short)

+ C5047u

+ C5047u

12

REG(12V)1

T45_RED

REG(12V)1

T45_RED

1

+ C4247u

+ C4247u

12

REG(5V)1

T45_RED

REG(5V)1

T45_RED

1

C440.1uC440.1u

R26

(short)

R26

(short)

JP233.3V-REGJP233.3V-REG

LOGIC1

T45_OR

LOGIC1

T45_OR

1

+ C3947u

+ C3947u

12

L5

(short)

L5

(short)

1 2

R24

(short)

R24

(short)

+ C4647u

+ C4647u

L4

(short)

L4

(short)

1 2

+C4347u

+C4347u

+C5247u

+C5247u

+ C4847u

+ C4847u

12

DVDD1

T45_OR

DVDD1

T45_OR

1

LOGIC2

T45_OR

LOGIC2

T45_OR

1

L6

(short)

L6

(short)

1 2

+C5347u

+C5347u

+ C4947u

+ C4947u

12

- 28 -

- 29 -

- 30 -

- 31 -

- 32 -