SWITCHES VTT PLANE + POWER C LPCFlash Time Changed: Engineer: Revision: Page: LAYER 3 Batt. COP...

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2 3

semiconductor

TM

Project:

D

4 5 86

Date Changed:Title:

by

B B

Gary Milliorn

Engineer:

Steve Foster

Revision:

Tiffany Tran-Chandler

7700 W. Parmer Ln

Cass Arnett

Austin, Texas 78729freescale

C

Freescale Semiconductor

C

semiconductor

TM

freescale

87654321

1

Gary Milliorn1.03

01HPCN: Argo Navis

Cover StoryThursday, February 1, 2007

2:05:21 pmPage:

7

A

D

Time Changed:

HPCN: High-Performance Computing platform for Networking

A

42PCIExpress Slot #1

QuadPHY Ports34

loved can be lost. All rights reserved. No warranty is made,

04

VCORE Power Supply

383940

DDR2 DIMM #1

25

DDR2 DIMM #2

V1.02 2006Nov07 PCB Tweaks

Contents

35

DDR1 DIMM #122

10SERDES and 1.8V Power

Global Bypass, Mounting, etc.

USB Ports

07

All information is subject to change without notice.

5.

M1573 PCI, RTC, LPC and Misc

Power Entry, Switches

Contents

20

05Placement and PCB Stackup

DDR1 Termination

Debug, LEDs

52

57

06 Hot Power Supplies

LPC Flash54PIXIS System Logic, Part 114

PIXIS System Logic, Part 215

this product.

13

Revision:

CompactFlash Header

44

Flash and PromJet Headers

MC8641D SERDES #1

Ethernet Port Connectors #1/#2

32

41MC8641D SERDES #2

MC8641D LocalBus Interface

The sheet-to-sheet cross reference format is:

27

MC8641D Control Block

37

Components with the label "No_Stuff" are not to be installed bydefault; they are for test or manufacturing purposes only.

C123

DDR1 DIMM #2

DDR2 Termination and Power

50 AC97 Codec

PEX Alternate Slot #1 and MidBus Probe45M1573 ULI PEX Connection46

23

PCI Isolation Buffer16

VCC_3.3

LocalBus DebugPage

4.

3

08

MC8641D Power part 1MC8641D Power part 2

1.2V power

and ground unless explicitly shown otherwise. Global power

C

11System and PHY Clocks

This schematic is provided for reference purposes only.

1

No warranty, expressed or applied, is made as to theaccuracy of the information contained herein. ContactFreescale Sale/FAEs to obtain the latest information on

4 5 6

51

55

17

COP and Debug Interfaces

SIO53 AC97 Audio Connectors

I2CBus Devices

21

MC8641D DDR Interface #2

24

D

12SERDES (REFCLK) and BCLK Clocks

Engineer:semiconductor

MC8641D Quad Ethernet MAC

28

43

30

VCORE

B

7

29

connections are:

DATE

Sheet VertZoneLetter HorizZoneNumber

of IBM. Other trademarks are the respective property of theirrespective copyright holders. Anyone perfect must be lying,

Initial version

Unless otherwise specified:All resistors are SMD0402, in ohms, 0.08W, +/-5%

47

PCI Slots #1 and #2

Part numbers used are for reference only; compatibleparts may be used; refer to the bill of materials.

49 M1573 SATA + IDE48

Page

Schematic Notes1.

2.

7

VCC_5

3.

4

VCC_1.2

anything easy has it’s cost, anyone plain can be lovely, anyone

33pF

09

Integrated circuits have default connections to power

6.

7.

VCC_2.5

Freescale and the Freescale logo are registered

2

TM

1 2 3

02Block Diagram

01

18Configuration Switches

apply (i.e. PCI). Little-endian numbering is noted at thesource component.

19

M1573 USB + APIC

56

MC8641D DDR Interface #1

8

A

B

D

Date Changed:

Time Changed:


Serial Ports 1 and 2

26

36

QuadPHY MAC

GND

VCORE Power Supply, cont’d

null

null1

All buses follow big-endian bit numbering order (bit 0 is

C

freescale

QuadPHY Power31

CHANGES

V1.0 2005Aug03

Title:Project:

Austin, Texas 78729

33

Cover PageBoard impedance is 55 +/- 5 ohms. General Information

All capacitors are SMD0402, in microfarads (uF), +/-20%.

Page:

A

express or implied.

8

Platform Power

65

No

_Stu

ff

7700 W. Parmer Ln

Ethernet Port Connectors #3/#4

V1.0a 2006Feb27 Initial production

Gary Milliorn1.03

02HPCN: Argo Navis

Information, pleaseThursday, February 1, 2007

2:05:47 pm

the most-significant bit), except where industry standards

trademarks of Freescale Semiconductor. PowerPC is a trademark

All ferrites are Z=50 ohms at 100 MHz.All fuses are self-resetting polyswitch (PTC) devices.

REV

03

All inductances are in microhenries (uH).

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Bus

7700 W. Parmer LnAustin, Texas 78729

C

A

US

B

AU

DIO

PromJET

DDR #1

8

7 8

Serial

RJ45MAG

RJ45MAG

RJ45MAG

Engineer:Revision:

6

Local

VCORE

SA

TA

2 31 5 6

PEX Slot

PEX Slot

PC

I 1

PC

I 2

TM

MC8641D

Title:

7

Group

LPC

PEx

PEx

Flash

SIO

PA

TA

C

54321

M1575

CF+

DDR #2

A

B

Date Changed:

Time Changed:

PIXIS

Clock

Page:Project:

D

VSC8244QuadPHY

RJ45MAG

Gary Milliorn 031.03

HPCN: Argo NavisBlock Diagram

Thursday, February 1, 2007

2:05:55 pm

4

B

D

Flash

freescaleFreescale Semiconductor

semiconductor

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Time Changed:Engineer:

Revision:Page:

LAYER 3

Batt.

CO

P

Su

per

IO

LP

CF

lash

AC97

VCORE

VD

D_P

LA

T

MPC9855

CONFIG SWITCHES

0.5oz0.5oz

LAYER 1

SIGNAL: 7

1.0oz

21

8

VT

T P

LA

NE

+ PO

WE

R #2

USB

RS

T

PW

R

FAN

RST

Title:

SIGNAL: 2

PWR

LE

D

LE

D

STATUS LEDS

PLANE: GND 1

SV

C

QPHY

PS/2

29L

V64

1

Note: Not Definitive -- see

PC

IExp

ress 4X

SATA3

SATA4

432

0.5oz0.5oz

SIGNAL

SIGNAL

PLANE

Project:

ON

A12V

AT

X P

OW

ER

APA150

8

A

B

D

Date Changed:

PLANE

LAYER 2

LAYER 4LAYER 5

LE

D

LE

D

LE

D

LE

D

Pro

mJe

t

IDE

SATA1

APA PROG

SIGNAL

1.5oz

A

B

freescale

Design Workbook.

PLANE: VCC_5, VCC_HOT_xxx

PLANE: GND

DD

R #1 D

IMM

#1

DD

R #1 D

IMM

#2

7

RJ45

SIGNAL: 5PLANE: VCC_3.3, VCORE

SIGNAL: 3SIGNAL: 4

PLANE: GND

244mm (9.6")

SIGNAL: 6

244mm (9.6")

D

1

RJ45SER #1

DD

R #2 D

IMM

#2

5 6 7

RJ45

65

SATA2

Mounting holes, positioned per microATX spec.

M1575

LT1331

PC

I 2

DD

R #2 D

IMM

#1

LE

D

LE

D

Mounting holes for socket.

MC8641D

AUDIO

1.0oz

BURIED CAP LAYER OPTION

USB

USBHDR

MIC2077

LE

D

LE

D

SIGNALSIGNALPLANE

LAYER 6LAYER 7

PC

IExp

ress 8X (in

16X slo

t)

PC

I 3

LAYER 8

semiconductor

TM

4

SIGNAL

1.5oz

SIGNAL: 1

1.0ozPLANE

1.0oz

SIGNAL

C

LE

D

LE

D

LE

D

LE

D

INFO LEDS

158.75mm (6.25")

VT

T P

LA

NE

+ PO

WE

R

RJ45

LAYER 9

LAYER 12

3


C

LE

D

LE

D


HPCN: Argo NavisPlacement Guide and PCB Stackup


2:06:05 pm

LAYER 10LAYER 11

.0930.5oz1.0oz


PLANE

AT

X P

OW

ER

CHASSIS POWER LED

ATX CHASSIS POWERVCC and VCC_3.3 on separate power planes.

LOCAL POWER

OPTION22ms R-C delay, or FPGAcontrol (not both).

22ms

CHASSIS RESET SWITCH

FORCE PSU ALWAYS ON

LOCAL RESET SWITCH

(3V)

LOCAL EVENT SWITCH

semiconductor

TM

321

8


65

A

4321

4 5


HPCN: Argo NavisPower Entry, System Reset


2:06:19 pm

6 7 8

B

D

Date Changed:

7

Engineer:

CUBE FANSINK HEADER

Revision:Page:Title:

Project:7700 W. Parmer LnAustin, Texas 78729

C

A

B

D

C

freescale

CHASSIS POWER

PC FANSINK HEADER

Time Changed:

100

header.1x2J5 1

2

0.1uFC39

14E2

U2

74lvc1g125.sc70

VCC_3.3=VCC_HOT_3.3

2

1

4

R45

VCC_HOT_3.3

VCC_12N

C430.1uF

14D2

VCC_5

14C2

VCC_5

54D1

VCC_3.3

R52

10K

J4header.1x2

1

2

VCC_3.3

25V

C38330uF

+

R46

4.7K

VCC_12

330uFC36

25V

+

VCC_3.3

220

R54

10uF

+

VCC_HOT_3.3

4.7K

R53

VCC_3.3=VCC_HOT_3.3

74lvc1g125.sc70

U12

1

4

C41

R57

sw.1spdtSW7

1

2

3

54D1

0.1uF

sw.1spdtSW9

1

2

3

47K

VCC_12_BULK

R58

10

C40

SW10

sw.1spdt1

2

3

VCC_5

R43

4.7K

VCC_12 VCC_HOT_5

48C7

0.1uFC37

R49

3.3K

J2atxpwr_12v_2x2vert

GND11

2GND2 P12V3

3P12V4

4

VCC_3.3

R48

6.8K

R50

100

header.1x31

2

3

14C8

14D2

3.3K

R47

25V

330uFC34+

14B2

J8

R55

10

14C2

VCC_5

10uFC42

+100

R51

conn.fan.3pos

P2

BK1

RD2

BL3

+

14C8

VCC_HOT_3.3

C32330uF

25V

+

VCC_12

C35330uF

25V

+330uF

C33

25V

17GND_P17

GND_P33

GND_P55

GND_P77

PS_ON14

PWRGOOD8

VCC_P1919

VCC_P2020

VCC_P44

VCC_P66

VSTDBY9

+12V_P1010

+3.3V_P11

+3.3V_P1111

+3.3V_P22

-12V_P1212

-5V_P1818

GND_P1313

GND_P1515

GND_P1616

No_Stuff

header.1x2J7

1

2

atxpwr_2x10vert_nopeg

J6

J3header.1x2

1

2

VCC_HOT_3.3

R1 220

R56

10

R44

220K

FAN_TACH

FAN_PWM

NC

NC

NC

NC

NC

SB_RSMRST

14C8

EVENT*

SHORT_POWERFANPWR

PWRSW*PWRSWS*

PS_ON*

RSMRST*

SB_RSMRST*

PWRGD

Date Changed:

TOP LAYER POUR FOR AGNDSEE LAYOUT RULES FOR VIAS TO GROUND PLANE

ACTEL POWER SEQUENCING

Add 0.5 square inch fill to ground tab.

Add 0.5 square inch fill to ground tab.

43

Revision:Page:Title:7700 W. Parmer Ln

B

D

2

A

Engineer:Project:

RES

1

C

TM

semiconductor

Cass Arnett 061.03

HPCN: Argo NavisHot Power Supplies


2:07:28 pmfreescaleFreescale Semiconductor

C

Austin, Texas 78729

2 43 65 871

5

A

Time Changed:

B

D

6 7 8

SYNC19

17V

BIA

S

VIN114

15VIN2

VIN316

2VSENSE

12PGND2

PGND311

10PH1

PH29

8PH3

PH47

6PH5

POWERPAD21

4PWRGD

20R

T

18SS_ENA

U18tps54310pwp.htssop20

1AGND

BOOT5

COMP3

PGND113

2IN

OUT4

5nRESET_FB

C1461.0uF

750

R68

1%

GND3

GND_TAB6

2IN

OUT4

5nRESET_FB

ddpak5

TPS72525KTT

U7

1ENABLE

GND3

GND_TAB6

1%

1.0uFC147

ddpak5

TPS72518KTT

U8

1ENABLE

1

rc1210

10R4

No_Stuff

VCC_HOT_3.3

R67

3.74K

CR1

MBRS360T3

smc_403

No_Stuff

21

smc_403

MBRS360T3

CR2

No_Stuff

2

R66

18K

1%

71.5K

R65 C1450.1uF

10.0K

R69

1%

100uFC143

VCC_HOT_3.3

C148

0.047uF

C144100uF

R64

10K

No_Stuff

C1381.0uF 1.0uF

C139

3.3UH

L3

1 2

C152470uF

+C140100uF

TP2

100uFC141

C1370.027uF

220K

R63

0.1uFC470

VCC_HOT_2.5

VCC_HOT_3.3

VCC_HOT_1.8

VCC_HOT_3.3 VCC_HOT_5

15B1

47pF

74lvc1g125.sc70

U56

VCC_3.3=VCC_HOT_3.3

2

1

456B1

C151

C1492200pF

C150

HOT_RST*

PS_H33_PG

C142100uF

2200pF

AREA_FILL

NC

NC

SH

OR

T_P

OW

ER

SH

OR

T_P

OW

ER

D

C

semiconductor

TM

5

54 8

2:07:37 pm

7

Place caps close to pins.

All grounds tied together at output caps.

621 3

2 31 7 86

Date Changed:

Time Changed:

A

B

D

Engineer:Revision:

Page:Title:

4

Freescale Semiconductor7700 W. Parmer Ln

Project:freescale

Austin, Texas 78729

C

A

B

VCC_3.3

14B2,56D1

8C8

Cass Arnett 071.03

HPCN: Argo NavisProcessor VDD (Vcore) Supplies


1%

680

R27

MBR0530

CR4

sod_123

cc0805

0.1uF

TP1

sod_123

MBR0530CR5

C18

NPO

cc0805

1uFC21

cc0805 25V

C25

1%

1000pFC27

25V

10nF

cc0805

1000pFC20

6

0

16.2K

R38

20D1

R37

16.2K 1%

C301uF

0.1uF

C24

25V

cc0805

2

VCC_12

8A1

12pFC804

VCC_5

R22

0

rc0603

C23

25V

cc0805

R42

0

rc0603

82.5K

rc0603

0

R41

0.1uF

8B1

30.1K

1%

R26

1%

R30

rc0603

100R36

cc0805

1uF

C17

C311uFcc0805

14C8

8B1

R40

23.7K

1%

No_Stuff

1uF

10nFC28

NPO

25V

cc0805

560pF

R31

10K cc0805

C19

8C8

C261000pF

C22

NPO

25V

cc0805

C2910nF

10K

R28

14C8,17C1

5

4

3

8C1

R34

2.40K

1%

1%

23.7K

R39

No_Stuff

1%

R29

130K

No_Stuff

10

R33

0

130K

R25

1%

0R23 VIN

142 14

VIN

2

43VPN1

VPN213

VREF2

1nPG

12

VCC_5

R32

TG216

37V

5_1

V5_

219

VCCA28

11VID0_LSB

10VID1

9VID2

VID38

7VID4

VID56

5VID6_MSB

36EN

ER

RO

UT

29

22FBn

21FBp

GND45

3HYS

ISH

34

35NC

25S

S

TG140

32CS1n

CS1p33

31CS2n

CS2p30

DA

C26

44DRIFT

39DRN1

DRN217

23DRPn

DRPp24

20DUAL

1

8C8

sc458.mlp44

U38

27A

GN

D

BG138

18BG2

BST141

15BST2

4CLSET

100

R24 0

20D1

BSTRCD1

ER

RO

UT

VREF

VREF

8B8

8D1

8D1

VCC_5

rc0603

R35

VTRC1

DAC

BG1

CFG_VID(6:0)

VPN2

VTRC2

ERC

SC458_AGND

CS1P

CS1N

CS2P

BST1

BSTRCD2

BST2

PG_DEL

PS_VCORE_PG

PS_CORE_EN

BG2

CLSET

CS2N

DRN1

DRN2

DRPNDRPP

HYS

ISH

SS

TG1

TG2

VCCA

VPN1

VCORE_SENSEpVCORE_SENSEn

Engineer:Revision:

Page:Title:Project:

7


C

A

B

D

Distribute caps along plane to processor.

Distribute caps along plane to processor.

DRNx is the "+" end of the inductor.CSxN is the "-" end of the inductor.

Route CS1x, CS2x, DRPx and FBxas differential pairs.

3

C


semiconductor

TM

7651 2 3 4 8

A

B

D

Date Changed:

Time Changed:

4 5 6

0.5..1.5V55A maximum

821

4

1 2 3

081.03

HPCN: Argo NavisProcessor VDD (Vcore) Supply, Part 2


2:07:45 pmCass Arnett

4

1 2 3

so8

Q9

IRF7832

5 6 7 8

C11

2.5V390uF

+

so8

Q6

IRF7832

5 6 7 8

C8070.1uF

VCORE

R18

47K

C4740.1uF 0.1uF

C806

18.2K 1%

C410uF

Q5

so8

5 6 7 8

4

1 2 3

R15

2 3

7B7

7B7

mbrs140lt3.smb403aD1

No_Stuff

2

1

IRF7832

16.2K

so8

IRF7821

Q4

5 6 7 8

4

1

D2mbrs140lt3.smb403a

No_Stuff

2

1

7B7

7B7

R11

1%

6 7 8

4

1 2 3

18.2K

R14

1%

5 6 7 8

4

1 2 3

so8

Q3

IRF7821

5

R21

26.1K

7C7

7C7

7C7

so8

IRF7832

Q1

Q8

so8

5 6 7 8

4

1 2 3

1%

33K

TH2

R16

0

IRF7821

C610uF

390uFC15

2.5V

+C13390uF2.5V

+

C510uF

C4720.1uF 0.1uF

C473

47K

R19

7B7

0.1uFC471

47K

R17

C710uF

7B7

VCORE

C14390uF2.5V

+

2 3

NPO

25V

56nF

C9

cc0805

1%

R12

16.2K

1 2

so8

IRF7832

Q2

5 6 7 8

4

1

IRF7832

5 6 7 8

4

1 2 3

L1

0.50UH

100pFC16

2.5V390uFC12+

so8

Q10

+

VCC_12_BULK

7C7

VCC_12_BULK

TH1

33K

25V

cc0805

L2

0.50UH

1 2

C10390uF2.5V

5 6 7 8

4

1 2 3

NPOC8

56nF

R20

C210uF

so8

Q7

IRF7821

0

R13

C310uF

47K

TG1

BG1

CS1N

DCR_DR1 DRPP

DRPN

DCR_DR2

CS2NTG2

BG2

DRN2

DRN1

Time Changed:

2

1.05 V

Rset = sum of R680 + R156 (switch open)Rset = R680 (switch closed)

56.2K

7700 W. Parmer LnRevision:Austin, Texas 78729

C

1.0-1.2V @ 9A

7654

freescale

1.10 V

VCC_PLAT

B

VCC_PLAT

8


A

B

D

Freescale SemiconductorTM

31

Engineer:

1

4 5 6 7

Date Changed:

32

A

CFG_PLATVDD

0 / OFF1 / ON

Page:semiconductor

Title:Project:

8

5

Cass Arnett 091.03

HPCN: Argo NavisPlatform Power (nominally 1.1V)

Wednesday, February 14, 2007

10:56:47 am

D

C

Rset

VCC_PLAT SETTINGRset

42.2K

VCC_3.3

sop5

74cbtlv1g125dbv.so5

U25

A2

B4

GND3

OE1

VCC

47pF

C800

1%10.0K

R682

2200pF

C799

0.1uFC797

TP170

18K

R679

C791R677

10K

0.047uFC798

1%

14C8

C801

2200pF

1.0uF

1%

42.2K

R680

R678

71.5K

1.0uF

0.033uFC795

1%

R681

750

L13

1UH1 2

C803470uF

4V

+C790

6.3V

100uFC796

1.0uFC792 C793

1.0uF

23VIN4

VIN524

VSENSE2

VCC_PLAT

4V

470uFC802+

13PH8

PH914

29POWERPAD

PWRGD4

RT

28

SS_ENA26

27SYNC

VB

IAS

25

20VIN1

VIN221

22VIN3

PGND217

PGND3

PGND418

19PGND5

6PH1

PH27

8PH3

PH49

PH510

11PH6

PH712

6.3V

14B2,56D1

tps54910pwp.htssop28U50

AGND1

5BOOT

3COMP

PGND115

16

14D8,17C1

1%

R156

14.0K

VCC_3.3

C794100uF

AREA_FILL

PS_PLATFORM_PG

PS_PLATFORM_EN

CFG_PLATVDD

VCC_3.3

7

Austin, Texas 78729

C

A

B

D

semiconductor

TM Page:Title:


8

C


765432

VCC_1.21.2v @ 3.3A

1

1 2 3 4

Cass Arnett 101.03

HPCN: Argo NavisGeneral 1.2V Power

Wednesday, February 14, 2007

5 6 8

Project:

Revision:7700 W. Parmer Ln

A

B

D

Date Changed:


VCC_5

4.7UH

L12

1 2

VCC_1.2

10:47:45 am

R516

18K

R518

750 1%

1.0uFC738

VCC_3.3

C744

47pF

14B2,56D1

+C740100uF

C7371.0uFR514

10K

C746470uF

R517

28.7K

1%

14C8

1%

71.5K

R515

C743

0.047uF

TP151

15VIN2

16VIN3

2VSENSEC739

0.027uF

C7410.1uF

9

8PH3

PH47

PH56

POWERPAD21

4PWRGD

20R

T

18SS_ENA

SYNC19

17V

BIA

S

VIN114


1AGND

BOOT5

COMP3

PGND113

12PGND2

PGND311

10PH1

PH2

2200pF

C745

1%

R519

10.0K

AREA_FILL

PS_1.2V_PG

PS_1.2V_EN

C742

2200pF




C

A

B

D

C

8


semiconductor

TM

4

7

1 52

VCC_SERDESTypically 1.1V @ 3.3A

VCC_1.81.8V @ 3.3A

3

Cass Arnett 111.03

HPCN: Argo NavisSERDES 1.2V and PHY 1.8V Power


2:08:11 pm

1

6

8

A

2 3 4

Engineer:Revision:

Page:

5 6

B

D

Date Changed:

Time Changed:Title:

Project:

7

14C8

1%

71.5K

R505

R504

71.5K

1%

C732

47pF

VCC_SERDES

2200pF

C734

C728

2200pF

1%

14C8

R507

18K

C7220.027uF

18K

R506

R509

9.76K

C730

0.047uF

C7260.1uF

1.0uFC721

4.7UH

L11

1 2

C724100uF

C7181.0uF

VCC_1.8

47pF

C731

VCC_3.3

14C2,56C1

10K

R503

C733

2200pF

2200pF

C727

C736470uF

+

TP150

C7191.0uF

L10

3.3UH1 2

0.047uF

C729

+100uFC723

1.0uFC717

RT

20

SS_ENA18

19SYNC

VB

IAS

17

14VIN1

VIN215

16VIN3

VSENSE2

470uFC735

COMP

13PGND1

PGND212

11PGND3

PH110

9PH2

PH38

7PH4

PH56

21POWERPAD

PWRGD4

SYNC19

17V

BIA

S

VIN114

15VIN2

VIN316

2VSENSE

tps54310pwp.htssop20

U11

AGND1

5BOOT

3

PGND2

PGND311

10PH1

PH29

8PH3

PH47

6PH5

POWERPAD21

4PWRGD

20R

T

18SS_ENA

0.1uFC725


1AGND

BOOT5

COMP3

PGND113

12

1%

0.027uFC720

TP149

42.2K

R508

1%

R513

10.0K

VCC_3.3

14C2,56C1

R502

10K

VCC_5

VCC_5

1%

R511

750

750

R510

1%

10.0K

R512

1%

PS_SERDES_PG

PS_SERDES_EN

PS_ULI_1.8V_PG

PS_ULI_1.8V_EN

5 6 7 8

A


Project:

Very Short

C

A

No special match requirements.

Variable 1-200 MHz reference.SYSCLK Clock

No special match requirements.

Austin, Texas 78729semiconductor

TM

B

D

C

7700 W. Parmer Ln

876

Any Length

Fixed 125.0 MHz reference.


PHY Clocks

3 54

Very ShortVery Short

4


HPCN: Argo NavisSystem Clock Generator


2:08:21 pm

21

1 2 3

B

D

Date Changed:


0

R75

10

R79

6.3V22uFC156

OSCON

+ C157

0.1uF 0.1uF

C158

33

6

19D1

23

7X1_ICLK

X28

R72 0

100

R74

V2

13V3

14V4

15V5

16V6

17V7

18V8

6

VDD1 VDD2

1R5

R62

22REF

3S0

S14

S25 10

V0

11V1

12

21

9

GND1 GND2

20

19PDTS

24R0

R125

26R2

27R3

R428

R81 33

U14ics525_02.ssop28

CLK

No_Stuff

0.1uF

C155

U9

EH2645TS-125.000M

125.000MHz

GND2 1

OE

OUT 34 V3.3V

VCC_3.3

51

R5

1

15B8

15A1

3

15B8

R78 33 1

33R73

2

R70

7

100

R80

0.1uF

0.1uF

C154

5

15B1

R76

100

C159

6

1ICLK

8OE

2Q1

3Q2

4Q3

5Q4

VDD7

0

R71

5

MPC94551EFso8

U10

GND

5

15B1

0R82

VCC_3.3

30D1,32B1

No_Stuff

conn.sma

P7

0.1uF

P1

conn.sma

No_Stuff

4

4

2

VCC_3.3

C153

1

2

1

33R77

SYSCLK_V(7:0)

SRCCLK SYSCLK

SYSCLK_R(4:0)

SYSCLK_S(2:0) 0

0

2

3

NC

NC NC

SYS_REFCLK

POWER_TRACEICSCLKPWR

PHYCLKPWR SHORT_POWER PHYCLK(0:2)PCLK1CM_MAXUTPCLK

SHORT_POWERMBUF1_PWR

UTLSYSCLK2CM_MAX

NC

SYSCLK_EN

1CM_MAXUTPHYCLK0

UTPHYCLK1 1CM_MAX

1CM_MAXUTPHYCLK2

NC

8

1 4

2

63

4

A

B

52 7 8

Time Changed:

D

REFCLK TERMINATIONBoth series and parallel are near the clock source.

TEST: Connect pin 1 to U53 pin 16

Date Changed:

2:08:30 pmTitle:

Project:Engineer:

to disable ULI REFCLK. Required to

Revision:Page:

C

BCLK Clock14.318 MHz reference.No special match requirements.

REFCLK (SerDes) Clock100.0, 125.0 or 156.25 MHz (common)Clocks routed as differential pairs.No special match requirements.

test Serial RapidIO modes.

A

6

7700 W. Parmer Ln

Very Short

Austin, Texas 78729


semiconductor

B

D

73

C

freescale51

TM

46A1

Gary Milliorn1.03

13HPCN: Argo Navis

RefClk (SERDES) and base clock.Thursday, February 1, 2007

R539 33

33R540

5

46A1

R538 33

0.1uF

C781

R534

33R563

R564 33

VCC_3.3

R530

5

1%

475

R532

0.1uF

C783

R536 33

51

R558

19C8,23D1,24D1,27D1,28D1,#6

54A1

C784

0.1uF

1

47C8Q1

3Q2

4Q3

5Q4

VDD7

R552

51

C777MPC94551EFso8

U54

GND

6

1ICLK

8OE

2

R546 33

VCC_3.3

VCC_3.3

50A1

0.1uF

R535

0

42C7

VCC_3.3

17D8

45A1

22uF6.3V

+

44C8

OSCON

C77522uF6.3V

+ C779

0.1uF

OSCON

C782

R557

51

19C8,23D1,24D1,27D1,28D1,#6

14B2,17C8

42C7

VCC_3.3

R556

51

R560

51

R553

51 51

R554

51

R551

33R548

51

R550

R545

43B1

R547 33

C776

OSCON

+

33R544

33

R541

R542 33

6.3V22uF

14.318MHzU52

2GND OE

1

3OUTV3.3V4

VCC_3.3

33

C778

43A1

33R537

33R529

44C8

0.1uF

3 10

VD

D2

14

VD

D3

VD

D4

19 31

VD

D5

VD

D6

36

VD

D7

40

VD

DA

48

X22

1XIN_CLKIN

45A1

34

28OE_3

OE_422

16OE_5

OE_613

7OE_7

5REFOUT

SCLK24

23SDATA

SEL14M_25M27

26SPREAD

VD

D1

FS045

44FS1

FS26

4

GN

D1

GN

D2

15 35

GN

D3

GN

DA

47

46IREF

OE_043

37OE_1

OE_2

29

30DIF3_P

21DIF4_N

DIF4_P20

DIF5_N18

17DIF5_P

12DIF6_N

DIF6_P11

DIF7_N9

8DIF7_P

DIF_STOP25

ICS9FG108BG-LFT

tssop48

U53

41DIF0_N

DIF0_P42

DIF1_N38

39DIF1_P

32DIF2_N

DIF2_P33

DIF3_N

R533

51

45C1

C780

0.1uF

P9conn.sma

19D1

No_Stuff

VCC_3.3

2

51

R555

No_Stuff

0

51

R559

5

R531

C774

R549

51

45C1

R528

50.1uF

33R561

R562 33

1CM_MAX

RCLK1 REFCLK_SD1pDIFF_CLK

RCLK

NC

NC

R543 33

UTREFSD2P 1CM_MAX

UTREFSD2N 1CM_MAX

1CM_MAXUTREFSL1P

1CM_MAXUTREFSL1N

UTREFSL2P 1CM_MAX

UTREFSL2N 1CM_MAX

1CM_MAXUTREFTAPP

1CM_MAXUTREFTAPN

UTREFULIP 1CM_MAX

UTREFULIN

DIFF_CLK REFCLK_SLOT1n

RCLK4DIFF_CLK REFCLK_SLOT2pRCLK4 REFCLK_SLOT2nDIFF_CLK

RCLK5 REFCLK_TAPpDIFF_CLK

RCLK5DIFF_CLK REFCLK_TAPn

RCLK6DIFF_CLK REFCLK_M1575pRCLK6 REFCLK_M1575nDIFF_CLK

POWER_TRACEREFCLKPWR2

POWER_TRACEREFCLKPWR1

RCLK1DIFF_CLK REFCLK_SD1n

RCLK2DIFF_CLK REFCLK_SD2pRCLK2 REFCLK_SD2nDIFF_CLK

RCLK3 REFCLK_SLOT1pDIFF_CLK

RCLK3

1CM_MAX

M1575_BCLK

SIO_BCLK

RTC_CLK

AUD_CLK

POWER_TRACE REFCLKPWR3

REFCLKPWR0

1CM_MAX

UTRCLK

1CM_MAXUTREFSD1N

CFG_REFCLKSEL(2:0)

I2C2_SDAI2C2_SCL

1CM_MAX

1CM_MAX

UTBCLK 1CM_MAX BCLK

1CM_MAX

1CM_MAX

NC

1CM_MAXUTREFSD1P

NC

NC

NC

NC

CFG_REFSPREAD

NC

See MapFile

GND

B

D


C

semiconductor

TM

7

freescale832 6

Stephen Foster1.03

14HPCN: Argo Navis

PIXIS System Controller, Page 1Thursday, February 1, 2007

2:08:40 pm

541

1 2 3 4 5 6 7 8

A

B

D

Date Changed:




C

A

1

5C8

0

5

6

7

0.1uFC759

16V

2

0

0.1uFC757

16V

VDD_5G6

VDD_6G11

VDD_7H6

VDD_8H11

J6VDD_9

R15VPN

VPPP14

0

1

F7

VDD_10K6

K11VDD_11

L7VDD_12

VDD_13L8

VDD_14L9

VDD_15L10

VDD_16J11

VDD_2F8

F9VDD_3

VDD_4F10

VDDP_14M10

VDDP_15M11

VDDP_16

E7VDDP_2

VDDP_3E10

E11VDDP_4

F5VDDP_5

VDDP_6F12

VDDP_7G5

G12VDDP_8

K5VDDP_9

VDD_1

TCKP13

TDIR14

TDOR16

TMST15

P15TRST

VDDP_1E6

VDDP_10K12

L5VDDP_11

VDDP_12L12

M6VDDP_13

M7

E8

E9IO_E9

F1IO_F1

F13IO_F13

IO_F14F14

IO_F15F15

F16IO_F16

IO_F2F2

F3IO_F3

IO_F4F4

N14RCK

D9

E1IO_E1

IO_E12E12

E13IO_E13

IO_E14E14

E15IO_E15

IO_E16E16

E2IO_E2

E3IO_E3

IO_E4E4

E5IO_E5

IO_E8

D14IO_D14

D15IO_D15

IO_D16D16

D2IO_D2

IO_D3D3

D4IO_D4

IO_D5D5

D6IO_D6

IO_D7D7

D8IO_D8

IO_D9

C4

C5IO_C5

IO_C6C6

C7IO_C7

IO_C8C8

C9IO_C9

IO_D1D1

D10IO_D10

IO_D11D11

D12IO_D12

IO_D13D13

B9

C1IO_C1

IO_C10C10

C11IO_C11

IO_C12C12

C13IO_C13

C14IO_C14

C15IO_C15

IO_C16C16

IO_C2C2

C3IO_C3

IO_C4

B14IO_B14

IO_B15B15

B16IO_B16

IO_B2B2

IO_B3B3

B4IO_B4

IO_B5B5

B6IO_B6

IO_B7B7

B8IO_B8

IO_B9

A4

A5IO_A5

A6IO_A6

IO_A7A7

A8IO_A8

IO_A9A9

IO_B1B1

B10IO_B10

IO_B11B11

B12IO_B12

IO_B13B13

AGND_2

J3AVDD_1

J15AVDD_2

A10IO_A10

IO_A11A11

A12IO_A12

IO_A13A13

A14IO_A14

IO_A15A15

IO_A2A2

A3IO_A3

IO_A4

0.1uFC758

apa150.1of2.fbga256

U49

AGND_1H4

H15

16V

C756 0.1uF

10B1

VCC_HOT_2.5

32B1

12

7B1,56D1

4

TP166

11C1

C762

R525

10K

0

1

11A1

3

0.1uF 0.1uFC767

2

48C7

1

13

10K

R5240.1uF

19C1

19C1

19B1

18C1

7B1,17C1

9C1,17C1

C7510.1uF

2

C761

0

1

4

5

3

32B1

0.1uF

19B1,46C8,54B1

1

15C1,16B8

17B8,38B1

43B1,45A1

15C1,16B8

19C1

19C1

C753 C7550.1uF

10A1,56D1

TP164

0.1uFC763

VCC_HOT_3.3

15

11C1,56C1

11A1,56C1

14

18D1

16V

C760 0.1uF

24

25 26

3 4

5 6

7 8

9

14

15 16

17 18

19

2

20

21 22

23

0

11

13C1,17C8

conn.2x13J34

1

10

11 12

13

48D7

5D1

16B8

17B8,18B1

29B8,56C1

5B8

38C1,39C1,41C1

19D8,56B1

23D1,24D1,27D1,28D1

18D1

54B1

C7640.22uF

0.1uF

17B1,18A1

VCC_1.8

10K

R527

0.1uF

3

VCC_HOT_2.5

5D8

C765

48C7

0.1uFC771 C772

6

17A8,18B1

17B8

0.1uFC752

5B1

46C8

9B1,56D1

74lvc1g125.sc70

U512

1

4

0.1uFC769 C770

0.1uF

8

48C7

C7680.1uF

18D1

TP167

0.22uFC766

9B1

46C8

19C1

0.1uFC754

2

VCC_HOT_2.5

0.1uFC773

7B1

PEX_RST*

25B8,56C1

10

5

R526

9

CFG_PLATVDD

GEN_RST*

MEM_RST*

CFG_FLASHBANKCFG_FLASHMAP

CFG_PORTDIVLB_RST*

ASLEEP

PWRSW*PS_ON*

PS_CORE_ENPS_PLATFORM_EN

PS_1.2V_ENPS_SERDES_ENPS_ULI_1.8V_EN

SB_OFFPWR_S4_S5*

CFG_BOOTLOC(0:3)

CFG_VID(6:0)

CFG_BOOTSEQ(0:1)

CFG_REFCLKSEL(2:0)PWRSWX*

COP_HRST*

COP_TRST*HRESET_REQ*

CPU_TRST*CPU_HRST*EVENT*

SRESET_1*SRESET_0*

SPARE01*CFGDRV*

M1_DDR_IOPWRGDM2_DDR_IOPWRGD

SB_CPURST*

SB_INIT*SB_OFFPWR_S3*

SB_PWGRSMRST*

SMI*

PWRGD

10CM_MAX

10CM_MAX

PS_VCORE_PGPS_PLATFORM_PGPS_1.2V_PGPS_SERDES_PGPS_ULI_1.8V_PG

NC

NC

NC

10CM_MAX

COP_SRST*

PME*

PHYRST*

10CM_MAX

10CM_MAX

V3_CBE*(3:0)

V3_PAR

V3_AD(31:0)

APA150_VDDPWR 2CM_MAX

10CM_MAX

10CM_MAX

10CM_MAX

NC

NC

NC

NC

NC

7700 W. Parmer Ln

C

A

B

D

C


semiconductor

TM

1.03

HPCN: Argo NavisPIXIS System Controller, Page 2


2:09:03 pm

876321 54

1 2 3 4 5 6 7

A

B

D

Date Changed:

8


Revision:Austin, Texas 78729Page:Title:

Project:

2

12B1

3

Stephen Foster 15

0

0

14B8,16B8

16B8

6

5

4

19B1,32A1,46C8

51A8

3

1

3

TP155

33R523

1

41C1

2

4

16B8

47A8,51B1,54A1,55B1

17

38B1

26

19

16A8

7

38B1

28

31

1

39B1

VCC_HOT_3.3

J13

1

56A1

56A1

3

16A8

17B1,18A10

1

IO_T3T3

T4IO_T4

T5IO_T5

IO_T6T6

IO_T7T7

T8IO_T8

IO_T9T9

NPECL1H2

NPECL2H14

J2PPECL1

PPECL2

R5

R6IO_R6

R7IO_R7

IO_R8R8

R9IO_R9

T10IO_T10

IO_T11T11

T12IO_T12

IO_T13T13

T14IO_T14

T2IO_T2

P7

P8IO_P8

IO_P9P9

R1IO_R1

IO_R10R10

R11IO_R11

IO_R12R12

R13IO_R13

IO_R2R2

R3IO_R3

IO_R4R4

IO_R5

P1IO_P1

P10IO_P10

IO_P11P11

IO_P12P12

IO_P16P16

IO_P2P2

P3IO_P3

P4IO_P4

IO_P5P5

P6IO_P6

IO_P7

N13

IO_N15N15

N16IO_N16

N2IO_N2

IO_N3N3

N4IO_N4

N5IO_N5

IO_N6N6

IO_N7N7

N8IO_N8

IO_N9N9

IO_M16

M2IO_M2

M3IO_M3

M4IO_M4

M5IO_M5

M8IO_M8

M9IO_M9

IO_N1N1

N10IO_N10

IO_N11N11

N12IO_N12

IO_N13

L15IO_L15

IO_L16L16

L2IO_L2

L3IO_L3

IO_L4L4

M1IO_M1

M12IO_M12

M13IO_M13

M14IO_M14

M15IO_M15

M16

IO_K1

K13IO_K13

IO_K14K14

K15IO_K15

IO_K16K16

IO_K2K2

K3IO_K3

IO_K4K4

IO_L1L1

L13IO_L13

IO_L14L14

IO_G2

IO_G3G3

G4IO_G4

IO_H12H12

H13IO_H13_GLMX2

IO_H3_GLMX1H3

IO_H5H5

J12IO_J12

IO_J14J14

J4IO_J4

IO_J5J5

K1

U49

GL1H1

GL2J1

GL3J16

H16GL4

IO_G1G1

IO_G13G13

IO_G14G14

IO_G15G15

IO_G16G16

G2

1

TP159

0

2

0

apa150.2of2.fbga256

29

25

24

26

1

0

33R522

0

4

17A1

16A8

4

22

4

5

12C1

0

6.3V22uFC749

OSCON

+5R520

TP158

C7500.1uF

018B8,37D8,38B1,41B1

27

8

37D8,38A1,39A1,41A1

0

1

17B8

19

2

30

31

0

27

16A8

16A8

R691 3347A8

22

2

12D1

1

2

23

16A8

U48

2GND OE

1

3OUTV3.3V4

39B1

3

3

33

16

12C1

2

18

33.000MHz

28

29

1

2

1

1

R521

3037D8,38A1,39A1,41B1

0

16B8

17A1,18A1

17A8,18B1

37D8,41A1

6B1

18B8,37D8,38B1,39A1,41C1

7

21

20

14C2,16B8

3

1

SYSCLK_V(7:0)

12C1

6

2

37D8,39A1,41C10

16A8

1CM_MAX

PIXIS_DEBUG(0:1)

LB_A(0:31)

IRQ*(0:11)

FAIL_LED*PASS_LED*

LB_WE*(0:3)

HOT_RST*

PCICLK_SB

SYSCLK_S(2:0)

SYSCLK_R(4:0)

LB_GPL(0:5)

CFG_PIXISOPT(0:1)

CFG_CCBPLL(0:3)

CFG_COREPLL(0:4)

CFG_SYSCLK(0:2)

CFG_HOSTMODE(0:1)

LB_D(0:31)

SYSCLK_EN

LB_CLK(0:1)

V3_AD(31:0)

SYS_REFCLK

HOTCLK

FCS*PJCS*

V3_INT*(0:1)

CF_RDYBSY*CF_CD*

PCI_CLK(0:4)

LB_CS*(0:3)

DATABLIZZARD_INTD*

V3_DEVSEL*

V3_FRAME*

V3_TRDY*V3_IRDY*

V3_STOP*

NC

NC

NC

1CM_MAX

UTHOTCLK

NC

V3_CBE*(3:0)

V3_SERR*V3_PERR*

V3_REQ*V3_GNT*

17

GROUND

8

19

38

49

NC

1

VCC

17

GROUND

8

19

38

49

NC

1

VCC

D

C

8

freescale764


5321


HPCN: Argo NavisPCI 5V-to-3V Level Translators


2:09:15 pmsemiconductor

TM

31 2 4 5 6 7 8

A

B

D

Date Changed:




C

A

B

C748

12

13

20

1

15A1

15A147C1,51B1

0.1uF

47C1,51B1

18

19

22

47D1,51B1

19

18

28

0

14B8,15C1

9

8

0

15B1

14D8

1

2

3

23

15C8

51B1

29

20

21

31

30

4

5

11

10

C747

0.1uF

10

2B634

2B733

2B832

2B9

552OE

1NC

VCC17

27

15A1

15C8

242A8

252A9

412B1

312B10

302B11

292B12

402B2

392B3

372B4

362B5

35

1OE

152A1

262A10

272A11

282A12

162A2

2A318

202A4

212A5

222A6

232A7

1B1043

1B1142

1B12

531B2

521B3

511B4

1B550

481B6

471B7

461B8

451B9

56

141A12

31A2

41A3

51A4

61A5

71A6

91A7

101A8

111A9

541B1

44

7

0

1

tssop56

SN74CBTD16211DGGR

U47

21A1

121A10

131A11

47C1,51B1

14

15

22

23

6

26

2

1

26

27

47C1,51B1

47C1,51B1

47C1,51B1

9

47B1,51C1

47C1,51C1

30

3147A1,51D1 14C2,15C1

25

2

15C8

28

29

2

2

8

15B1

11

4

15A1

3

24

25

14

15

VCC_5

1

5

6

15B1

3

21

7

0

16

17

47C1,51B1

12

13

0

1

17

16

2B436

2B535

2B634

2B733

2B832

2B9

552OE

1NC

17VCC

24

2A522

2A623

2A724

2A825

2A9

412B1

312B10

302B11

292B12

402B2

392B3

37

461B8

451B9

561OE

152A1

262A10

272A11

282A12

162A2

182A3

202A4

21

1A9

541B1

441B10

431B11

421B12

531B2

521B3

511B4

501B5

481B6

471B7

1A1

121A10

131A11

141A12

31A2

41A3

51A4

61A5

71A6

91A7

101A8

11PCI_GNT*(0:2)

47C1,51C1

0

2

3

tssop56

SN74CBTD16211DGGR

U46

2PCI_FRAME*PCI_DEVSEL*PCI_IRDY*PCI_TRDY*PCI_STOP*

V3_FRAME*NC

V3_DEVSEL*V3_IRDY*

V3_TRDY*V3_STOP*V3_PERR*V3_SERR*

V3_INT*(0:1)

V3_REQ*V3_GNT*

PCI_PERR*PCI_SERR*PCI_REQ*(0:2)

PCI_PAR V3_PAR

PCI_CBE*(3:0) V3_CBE*(3:0)

PCI_INT*(0:3)

V3_AD(31:0)PCI_AD(31:0)

NC

semiconductor

TM

8765321 4

2 31 5 6 74 8

B

D


HPCN: Argo NavisGeneral Configuration


2:09:24 pm

Date Changed:

A

Engineer:Revision:

Page:Time Changed:

Title:Project:


C

A

B

D

C


4.7K

R65

4

4.7K

R58

7

7B1,14C8

R59

11K

18C1

R58

84.

7K VCC_HOT_3.3

4.7K

R66

7

R60

51K

4.7K

R65

9

R66

34.

7K

1

1

0

2

1KR

610

14B2,38B1

1KR

613

0

18B1

30A8

1KR

634

1KR

594

4.7K

R58

3

VCC_3.3

0

1

4.7K

R57

7

4.7K

R64

6

R60

11K

R66

94.

7K

4.7K

R67

3

R64

31K

R66

04.

7K

R63

51K 1K

R63

9

0

1

2

R65

84.

7K

38C1,55B1

48D7

4.7K

R56

7

0

R61

91K 1K

R62

3

4.7K

R58

5

2

3

VCC_3.3

1KR

598

R58

24.

7K

1KR

592

R59

51K

2

1

R67

14.

7K

R60

31K

R66

64.

7K

R65

04.

7K

1KR

600

R62

71K 1K

R63

1

R66

4

1KR

644

13

5 12

6 11

7 10

8 9

4.7K

sw.8spst.cts

SW3

1 16

2 15

3 14

4

R62

51K

4.7K

R58

1

47B8

47B8,50B1

47B8

VCC_3.3

1KR

621

7 10

8 9

15C1,18B11

1KR

604

2 15

3 14

4 13

5 12

6 11

6 11

7 10

8 9

SW6

sw.8spst.cts

1 16

1 16

2 15

3 14

4 13

5 12

5 12

6 11

7 10

8 9

sw.8spst.cts

SW5

SW4

sw.8spst.cts

1 16

2 15

3 14

4 13

1KR

590

R57

04.

7K

R64

54.

7K

4.7K

R64

9

R57

44.

7K

2

18B1

4.7K

R65

1

18B1

4.7K

R57

1

1K 1KR

637

4.7K

1KR

608

R63

3

4.7K

R57

3

R67

6R

674

4.7K

R64

74.

7K

R60

71K

4.7K

R66

2

3

R65

34.

7K

4.7K

R65

7

15C1,18A1

R58

91K

18B1

2

1KR

618

3

R66

84.

7K

3

R61

41K

0

4

3

R66

14.

7K

VCC_3.3

1KR

628

15D1

1KR

620

R62

41K

15C1

13C1,14B21

0

R61

61K

5 12

6 11

7 10

8 9

R56

64.

7K

SW2

sw.8spst.cts

1 16

2 15

3 14

4 13

1

4.7K

R67

5

0

0

1

R58

44.

7K

R61

11K

VCC_3.3

14B2

R58

64.

7K

VCC_3.3

1KR

596

R59

31K

40C8

18C1

R63

21K

VCC_3.3

14D8,18A1

4.7K

R56

5 1KR

626

R63

01K

4

6

1

2

R56

84.

7K

R61

71K

1KR

642

R65

54.

7K

4.7K

R56

9

4.7K

R65

6

014C8,18B1

13

5 12

6 11

7 10

8 9

R65

24.

7K

47B8,50B1

sw.8spst.ctsSW8

1 16

2 15

3 14

4

0

1KR

615

1KR

629

48C7,56B1

15C1,18A1

R59

71K

4.7K

R64

8

4.7K

R67

2

1KR

636

R64

01K

14B2,18B1

9C1,14D8

R63

81K

R57

64.

7K

4.7K

R57

9

1

R59

91K 1K

R60

2

1KR

612

13C1

4.7K

R67

0

R60

6

R60

91K

R62

21K

40A1

5

1K

14

4 13

5 12

6 11

7 10

8 9

sw.8spst.cts

SW1

1 16

2 15

3

R64

11K

R58

04.

7K

R57

84.

7K

4.7K

R66

5

CFG_ASMP

R57

24.

7K

4.7K

R57

5

CFG_DDRDEBUG

CFG_HOSTMODE(0:1)

CFG_BOOTSEQ(0:1)

CFG_IOPORTS(0:3)

CFG_REFCLKSEL(2:0)

CFG_FLASHBANKCFG_FLASHMAP

CFG_PIXISOPT(0:1)

CFG_FLASHWP*

CFG_CPUBOOTCFG_BOOTADDR

CFG_SERROM_ADDR

ACZ_SDOUT

ACZ_SYNC

SUSLEDACB_SDOUT

ACB_SYNC

ACPWRCFG_IDWP

CFG_REFSPREAD

CFG_LADOPT(0:1)

CFG_PORTDIV

CFG_COREPLL(0:4)

CFG_CCBPLL(0:3)

CFG_BOOTLOC(0:3)

CFG_SYSCLK(0:2)

CFG_PLATVDD

CFG_VID(6:0)

CFG_MEMDEBUG

4

VCC_3.3

31

42

10

15

21

28

34

39

45

GND

18

7

(MSB)

B2, B5, B8, B11

GROUND

A2, A5, A8, A11, A14

(LSB)

4

VCC_3.3

31

42

10

15

21

28

34

39

45

GND

18

7

semiconductor

TM

43

Route TSECxxx lines through pin 2 of these330-ohm resistors (no stubs in path).

1 2 3 4

21

7 8

A

B

5 6


Revision:Page:

D

Date Changed:Project:7700 W. Parmer LnAustin, Texas 78729

C

Title:

Place near CPU.

D

C



HPCN: Argo NavisConfiguration Buffer; COP and Debug


2:09:33 pm

A

B

87

KEY

CPU JTAG Header

65

0

14C8,17A8

R31

310

.0K

29

1OE1

48OE2

25OE3

OE424

17C8

2

1

2

14C2

14

16

17

30

29

27

26

19

20

22

23

37

8

9

11

12

36

35

33

32

13

47

46

44

43

2

3

5

6

41

40

38

3

1

2

3

tssop48

A4

A3

A2

A1

U2374lvc16244adgg.tssop48

Y1

Y2

Y3

Y4

VCC_3.31K

R32

0

1

2

6

7 8

9

19B8

330R329

11 12

13 14

15 16

2

3 4

5

19C1

0

219C1

J26header_riscwatch

1

10

3

3

17A8

0

1

0

19C1

R330 330

1

TP109

37A8

1

10.0

KR

312

31

3

15C1,17A1

330R331

R326 330

330R692

2

3

27

30B8,31B8

0

330R325

3

17C8

0

0

1

0

1

0

TP111

0

5

3

TP112

1

1

4

TP110

1

10.0

KR

314

37A8,41C1

14C2

30

R332 330

3

15A8,37D8,38B1,41B1

37A8,41B1

R324 330

28

29

0

14C2

2

2

30B1,31B1330R323

1

0

4

19B8

19B8

2

3

10.0

KR

318

14D8,17B1

1

4

R31

710

.0K

R31

910

.0K

30

15A8,37D8,38B1,39A1,41C1

10.0

KR

315

330

2

17C8

17B8

10.0

KR

316

R328

17C8

15C1,17A8

1

R327

OE248

OE325

24OE4

15C1,17B10

3

19B8

19B8

330

17

30

29

27

26

19

20

22

23

OE11

37

8

9

11

12

36

35

33

32

13

14

16

46

44

43

2

3

5

6

41

40

38

D6nA10

D6p

D7nB10

D7pB12

30A1,31A1

Y4

Y3

Y2

Y1

74lvc16244adgg.tssop48U22

A1

A2

A3

A4

tssop48

47

D1nB1

D1pB3

A6D2n

A4D2p

D3nB4

D3pB6

A9D4n

A7D4p

D5nB7

D5pB9

A12

14C2

P8conn.banjo_alt

A15CLK_QUALn

CLK_QUALpA13

A3D0n

A1D0p

0

14B2,17B8

19C1

19B8

0

R157 330

R32

110

.0K

19C1

19C1

NC

D1_MSRCID(4:0)

CFG_MEMDEBUGCFG_DDRDEBUG

CFG_BOOTSEQ(0:1) LB_GPL(0:5)

CFG_IOPORTS(0:3) TSEC4_TXD(3:0)

CFG_CPUBOOT

NC NC

LB_LAD(0:31)

LB_DP(0:3)

LB_WE*(0:3)

CFG_BOOTADDR TSEC1_TXD(3:0)CFG_PORTDIV

10.0

KR

322

NCMDVAL1

D2_MSRCID(4:0)MDVAL2

TRIG_OUTTRIG_IN

CFG_CCBPLL(0:3)

CFG_COREPLL(0:4)

LB_LA(27:31)

CFG_BOOTLOC(0:3) TSEC2_TXD(3:0)

CFG_HOSTMODE(0:1)

NC

NC

NC

NC

NC

CFGDRV*

CFG_LADOPT(0:1)

COP_TRST*

CKSTP_IN*

CKSTP_OUT*

COP_SRST*CPU_TMS

CPU_TDOCPU_TDI

NC

CPU_TCK

COP_HRST*


Revision:Page:

and external clock term.

Project:Freescale Semiconductor

Austin, Texas 78729

C

A

Option: EMI Suppression

TMfreescale

B

D

C

semiconductor

2 87654

5

1 3

2 31 4

Date Changed:

6


HPCN: Argo NavisMC8641D System Interfaces


2:09:43 pm

7 8

A

Title:

CLKOUT: Place outsidethe socket outline on thetop layer.

IRQ[0:7] Pullup/PulldownsMPC8641 V1.0("PD4") - PulldownsMPC8641 V2.0("PD6") - Pullups

B

D

7700 W. Parmer Ln

VCC_3.3

3

4

36B1

11

4.7K

R10

4

4.7K

R86

4.7K

R84

10

6

4.7K

R87

54C1

18C8

14C2,56B1

18C8

TP8

0

0

1

3

4

18D8

14D2,46C8,54B1

2

3

4

15C8,32A1,46C8

R11

54.

7K

No_Stuff

R8

1K

4.7K

R96

R11

34.

7K1KR

111

4.7K

R10

2

R95

4.7K

2

7

TP12

4.7K

R11

6

VCC_3.3

5

1

9

18D1

14C2

18D8

13A8

TP10

R99

4.7K

4.7K

R98

40A8

14C2

4.7K

R10

0

TP14

R10

34.

7K

18D8

R11

44.

7K

TP11

36A1

13C1,23D1,24D1,27D1,28D1,#6

8

14C2

18D8

54C1

18D1

TP13

14C2

0

R699

No_Stuff

R97

4.7K

R118

14C2

VCC_3.3 VCC_3.3

R698

0

R11

21K

0

No_Stuff

100pF

C1

1KR

109

0

R10

14.

7K

R89

4.7K

49.9

R7

36B1

TP15

4.7K

R94

R93

4.7K

No_Stuff

12B8

TP4

TP5

D31

A32UART_SOUT2

J17

18D1

40A8

18C1

R11

01K

TMSF18

TRIG_INJ14

J13TRIG_OUT_READY_QUIESCE

A17TRST

UART_CTS1A31

B31UART_CTS2

UART_RTS1C31

E30UART_RTS2

B32UART_SIN1

C32UART_SIN2

UART_SOUT1C21SRESET_1

G16SYSCLK

TCKH18

TDIJ18

TDOG18

C16TEST_MODE0

TEST_MODE1E17

D18TEST_MODE2

TEST_MODE3D16

AA11

Y11

AD24

LSSD_MODEC18

MCP_0F17

H17MCP_1

J16

D19

RTCK17

SMI_0L15

SMI_1L16

SRESET_0C20

C30

IRQ11_DMA_DDONE3D30

IRQ2H27

IRQ3J23

IRQ4M23

IRQ5J27

IRQ6F28

IRQ7J24

IRQ8_AUX_CLKOUTL23

B30IRQ9_DMA_DREQ3

IRQ_OUTJ26

AG26

DMA_DREQ0E31

DMA_DREQ1E32

HRESETB18

HRESET_REQK18

IIC1_SCLB17

A16IIC1_SDA

IIC2_SCLB21

A21IIC2_SDA

G28IRQ0

IRQ1G29

IRQ10_DMA_DACK3

H15D1_MSRCID3

G15D1_MSRCID4

D2_MSRCID0E16

D2_MSRCID1C17

D2_MSRCID2F16

D2_MSRCID3H16

D2_MSRCID4K16

D32DMA_DACK0

DMA_DACK1F30

DMA_DDONE0F31

DMA_DDONE1F32

18D1

SYSTEM

mc8641d.1of9.system.cbga1023U32

ASLEEPC19

L18CKSTP_IN

CKSTP_OUTL17

CLK_OUTB16

F15D1_MSRCID0

D1_MSRCID1K15

K14D1_MSRCID2

R88

4.7K

36B1

36B1

36A1

R117 0

1

TP9

TP7

TP6

R91

4.7K

4.7K

R90

2

13D1,23D1,24D1,27D1,28D1,#6

TP3

4.7K

R92

R10

84.

7K

14C2

0

R83

4.7K

4.7K

R10

7

No_Stuff

0R6

18D1

R85

4.7K

4.7K

R10

6

TP16

D2_MDVALMDVAL2

TEMP_ANODETEMP_CATHODE

SMI*

RSVD10

ASLEEP

R10

54.

7K

I2C1_SCL

CPU_TDICPU_TDOCPU_TCKCPU_TMSCPU_TRST*

RTC_CLK

HRESET_REQ*

D1_MSRCID(4:0)

UART2_RXD

SRESET_0*SRESET_1*

D2_MSRCID(4:0)

MDVAL1D1_MDVAL

I2C2_SCL

UART2_TXD

I2C2_SDA

UART1_RXDUART1_TXD

UART1_RTS*UART1_CTS*

RSVD9

TRIG_OUTTRIG_IN

CPU_HRST*

I2C1_SDA

SYSCLK

CKSTP_IN*CKSTP_OUT*

TEMP_ANODE

IRQ*(0:11)

SPARE1SPARE01*

TEMP_CATHODE

Engineer:Project:

B

Austin, Texas 78729

B

D

Date Changed:

placement.

TM

8

D

C

Bypass Capacitor PlacementRefer to design workbook for detailed

semiconductor

2

2

7

C


3

FOR MC8641D: V1.0

1

3

654

7

Page:

VCORE_0 and VCORE_1 are connected

1 4 5 6

Revision:7700 W. Parmer Ln

A

internally.

8

Time Changed:Gary Milliorn

1.0320

HPCN: Argo NavisMC8641D Power


2:09:52 pmTitle:

A

C1140.1uF 0.1uF

C120

0.1uFC65

0.1uFC107

C690.1uF

VDD_ENET_IO

C95

C870.1uF

7C1

0.1uFC100

0.1uF

C104

C1150.1uF

0.1uFC83

R62

10

0.1uF

0.1uFC127

0.1uFC123

C990.1uF

0.1uFC54

0.1uFC91

C480.1uF

C840.1uF

0.1uFC44

2A

Z=115ohms

C770.1uF

7C1

0.1uFC112

F2

0.1uFC49 C55

0.1uF

C600.1uF

C450.1uF

VCC_3.3

VCC_PLAT

C460.1uF

C1190.1uF

C662.2uF

0.1uFC63 C71

0.1uFC570.1uF

C1340.1uF

0.1uFC51

0.1uFC58

VCC_SERDES

Z=115ohms

2A

F3

VCC_SERDES

C1082.2uF

C93

0.1uFC136

0.1uFC72

0.1uF

0.1uFC88 C94

0.1uF

C1350.1uF

0.1uFC61

C520.1uF

VCORE

2.2uFC109

0.1uFC47

0.1uFC110

C860.1uF

No_Stuff

R2 0

C80

C1240.1uF

No_Stuff

0R3

R60

10

0.1uF

0.1uF

0.1uFC116

C1280.1uF

C132

0.1uFC117 C121

0.1uF

0.1uFC78

C1110.1uF

0.1uFC890.1uF

C730.1uF

C81C590.1uF

C500.1uF 0.1uF

0.1uFC53

0.1uFC85 C92

0.1uFC70

C1050.1uF

0.1uFC56 C62

0.1uF

0.1uFC101

VCC_PLAT

C98

C1060.1uF

0.1uF

C1030.1uF0.1uF

0.1uFC131

C79

XVDD_4P26

XVDD_5R24

XVDD_6R28

XVDD_7T27

XVDD_8U25

XVDD_9

C900.1uF

XVDD_14AB28

XVDD_15AC26

XVDD_16AD27

XVDD_17AF28

XVDD_18AH27

AK28XVDD_19

L24XVDD_2

XVDD_20AM27

AE25XVDD_21

M27XVDD_3

N25

VDD_CORE1_4T19

VDD_CORE1_5VDD_CORE1_6

T21

VDD_CORE1_7T23

VDD_CORE1_8U16

VDD_CORE1_9U18

K26XVDD_1

V26XVDD_10XVDD_11

W24

XVDD_12Y27

XVDD_13AA25

Y19VDD_CORE1_20

Y21VDD_CORE1_21

Y23VDD_CORE1_22

AA16VDD_CORE1_23

AA18VDD_CORE1_24VDD_CORE1_25

AA20

VDD_CORE1_26AA22

VDD_CORE1_27AB23

VDD_CORE1_28AC24

R20VDD_CORE1_3

T17

VDD_CORE1_10U22

VDD_CORE1_11V17

VDD_CORE1_12V19

VDD_CORE1_13V21

VDD_CORE1_14V23

VDD_CORE1_15W16

W18VDD_CORE1_16

W20VDD_CORE1_17

W22VDD_CORE1_18

Y17VDD_CORE1_19

R18VDD_CORE1_2

VDD_CORE0_26AA14

VDD_CORE0_27AB13

VDD_CORE0_28

VDD_CORE0_3L14

VDD_CORE0_4M13

VDD_CORE0_5M15

N12VDD_CORE0_6

N14VDD_CORE0_7

P11VDD_CORE0_8

P13VDD_CORE0_9

VDD_CORE1_1R16

U12

VDD_CORE0_17U14

VDD_CORE0_18V11

VDD_CORE0_19V13

VDD_CORE0_2L13

VDD_CORE0_20V15

VDD_CORE0_21W12

VDD_CORE0_22W14

VDD_CORE0_23Y12

VDD_CORE0_24Y13

Y15VDD_CORE0_25

AA12

TVDD_1AC17

TVDD_2AG18

TVDD_3AK20

VDD_CORE0_1L12

P15VDD_CORE0_10

R12VDD_CORE0_11

R14VDD_CORE0_12

T11VDD_CORE0_13

T13VDD_CORE0_14

T15VDD_CORE0_15VDD_CORE0_16

SVDD_22AJ29

SVDD_23AK32

AL30SVDD_24

AM31SVDD_25

SVDD_3K28

SVDD_4K32

SVDD_5L30

M28SVDD_6

M31SVDD_7SVDD_8

N29

SVDD_9R30

W30SVDD_13SVDD_14

Y31

AA29SVDD_15SVDD_16

AB32

AC30SVDD_17

AD31SVDD_18

AE29SVDD_19

SVDD_2J29

AG30SVDD_20

AH31SVDD_21

AC20LVDD_1

AD23LVDD_2

AH22LVDD_3

SENSEVDD_CORE0M14

U20SENSEVDD_CORE1

SENSEVSS_CORE0P14

V20SENSEVSS_CORE1

H31SVDD_1

T31SVDD_10

U29SVDD_11SVDD_12

V32

2.2uFC96

cbga_31x31_1mm_skt

U32mc8641d.8of9.power.cbga1023

AVDD_CORE0B20

A19AVDD_CORE1

AVDD_LBIUA20

B19AVDD_PLAT

C76

C1180.1uF

0.1uFC113

0.1uF

0.1uF

C1020.1uF

VCORE

10

R61

C125

0.1uFC68

C972.2uF

2.2uFC74

0.1uFC82

2.2uFC67 C75

2.2uF

0.1uFC122

Z=115ohms

2A

F1

0.1uFC130

0.1uFC126

10

R59

C1290.1uF 0.1uF

C133

VCORE_SENSEp

C640.1uF

SHORT_POWER

VCORE_SENSEn

SHORT_POWER

SHORT_POWER

SHORT_POWER

SHORT_POWER

SHORT_POWER

SHORT_POWER

GND

mapfile.See Spec or

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workbook for details).

c

Engineer:

8

Title:Project:

54

C

A

B

1 2 3 4 5

etc.


7

cc c c

c c

D

c c

21

c

6

TM Page:Revision:

B

CBGA1023 Escape Patternand Capacitor Placement

c

etc.

etc. etc.

C

D

Date Changed:

semiconductor7700 W. Parmer LnAustin, Texas 78729

7 8

A

Time Changed:

cc

cc

c

c

c

Or, use via-in-pad (see Design


HPCN: Argo NavisMC8641D Power, Part 2


2:10:02 pm

6

c c

cc

cc

c

3

0.1uFC548

0.1uFC540

C5450.1uF

C5150.1uF 0.1uF

C519

VCC_DDRB_IO

0.1uFC511

C5570.1uF

C5230.1uF

C5090.1uF

C5360.1uF

0.1uFC505

0.1uFC558

0.1uFC534

0.1uFC529 C533

0.1uF

0.1uFC553

C510

0.1uFC550

C546

0.1uFC544

0.1uF VCC_3.3

C5430.1uF 0.1uF

C5170.1uF

No_Stuff

160

R684

0.1uFC528C512

0.1uF 0.1uFC516

C5270.1uF

0.1uFC560C539

0.1uFC5540.1uF

C5300.1uF

C5070.1uF

C5510.1uF0.1uF

C542

0.1uF

VCC_PLAT

C5060.1uF

C5470.1uF

VCC_DDRA_IO

C537

C5410.1uF

0.1uFC513 C525

0.1uFC538

0.1uFC521

0.1uF

0.1uF

VCC_3.3

0.1uFC532

0.1uFC556 C559

C5140.1uF 0.1uF

C518

0.1uFC508

C5550.1uF

C5490.1uF

C5260.1uF

C5520.1uF

51

R683

C5220.1uF R22

VDD_PLAT_11

VDD_PLAT_2M17

VDD_PLAT_3M18

VDD_PLAT_4N20

N22VDD_PLAT_5

P17VDD_PLAT_6

P19VDD_PLAT_7

P21VDD_PLAT_8VDD_PLAT_9

P23

B28OVDD_3OVDD_4

D17

D24OVDD_5OVDD_6

D27

F19OVDD_7OVDD_8

F22

F26OVDD_9

SENSEVDD_PLATN18

SENSEVSS_PLATP18

VDD_PLAT_1M16

VDD_PLAT_10N16

GVDD2_9

AM30

B22OVDD_1

F29OVDD_10

G17OVDD_11

H21OVDD_12

H24OVDD_13

K19OVDD_14

K23OVDD_15

M21OVDD_16

OVDD_2B25

AJ2GVDD2_27

AK6GVDD2_28

AL4GVDD2_29

GVDD2_3B8

AM2GVDD2_30

GVDD2_4D4

GVDD2_5D7

GVDD2_6E2

F6GVDD2_7

G4GVDD2_8

H2

U2

GVDD2_18W4

GVDD2_19Y2

GVDD2_2B5

AB4GVDD2_20

AC2GVDD2_21

AD6GVDD2_22

AE4GVDD2_23

AF2GVDD2_24

AG6GVDD2_25

AH4GVDD2_26

GVDD1_7H11

GVDD1_8H14

GVDD1_9

GVDD2_1B2

GVDD2_10J6

K4GVDD2_11

L2GVDD2_12

M6GVDD2_13

N4GVDD2_14

P2GVDD2_15

T4GVDD2_16GVDD2_17

AH10GVDD1_26

AJ8GVDD1_27

AJ14GVDD1_28

AK12GVDD1_29

D10GVDD1_3

AL10GVDD1_30GVDD1_31

AL16

GVDD1_4D13

GVDD1_5F9

GVDD1_6F12

H8

GVDD1_16GVDD1_17

W10

GVDD1_18Y8

GVDD1_19AA6

GVDD1_2B14

AB10GVDD1_20

AC8GVDD1_21

AD12GVDD1_22

AE10GVDD1_23

AF8GVDD1_24

AG12GVDD1_25

U32

cbga_31x31_1mm_skt

mc8641d.9of9.power.cbga1023

GVDD1_1B11

GVDD1_10K10

K13GVDD1_11

L8GVDD1_12

P8GVDD1_13

R6GVDD1_14

U8GVDD1_15

V6

C5200.1uF 0.1uF

C524

0.1uFC535

OVDD_17

C5310.1uF

3 4 5 6 7 8

A

B

D

Date Changed:




C

A

B

D

C

freescale8765


HPCN: Argo NavisDDR-2 Interface #1


2:10:11 pm

4321

1


semiconductor

TM

2

23D8,24D8

44

7

8

23B1,24B1,25D10

2

5

24C1

24C1

2

3

4

5

6

7

23C1,24C1,25C1

23C1,24C1,25C1

47

46

23C1,24C1,25C1

4

R392

23C1

23C1

1

2

5

R391 0

0

15

24C1

4

5

23B1,24B1

0

6

34

35

23C1

48

4

5

14

0R390

0

1

58

59

R389 0

61

49

43

42

0

1

2

C5030.1uF

6

L10D1_MECC5

P9D1_MECC6R10

D1_MECC7

D1_MODT0AC9

D1_MODT1AF12

AE11D1_MODT2D1_MODT3

AF10

AB12D1_MRAS_B

D1_MVREFAM18

D1_MWE_BAB11

D1_MDQS6

AJ13D1_MDQS6_B

AK17D1_MDQS7

AM16D1_MDQS7_B

N9D1_MDQS8

P10D1_MDQS8_B

M8D1_MECC0

M7D1_MECC1

R8D1_MECC2

T10D1_MECC3

L11D1_MECC4

C10D1_MDQS1

B10D1_MDQS1_B

H12D1_MDQS2

H13D1_MDQS2_B

J7D1_MDQS3

J8D1_MDQS3_B

AE8D1_MDQS4

AD8D1_MDQS4_B

AM9D1_MDQS5

AL9D1_MDQS5_B

AK13

AL18D1_MDQ59

B13D1_MDQ6

AJ15D1_MDQ60

AL15D1_MDQ61

AL17D1_MDQ62

AM17D1_MDQ63

C13D1_MDQ7

C11D1_MDQ8

D11D1_MDQ9

A13D1_MDQS0

D1_MDQS0_BD14

D1_MDQ49

B15D1_MDQ5

AL14D1_MDQ50

AM14D1_MDQ51

AL11D1_MDQ52

AM11D1_MDQ53

AM13D1_MDQ54

AK14D1_MDQ55

AM15D1_MDQ56

AJ16D1_MDQ57

AK18D1_MDQ58

A15D1_MDQ4

AL8D1_MDQ40

AM8D1_MDQ41

AM10D1_MDQ42

AK11D1_MDQ43

AH8D1_MDQ44

AK8D1_MDQ45

AJ10D1_MDQ46

AK10D1_MDQ47

AL12D1_MDQ48

AJ12

D12D1_MDQ3

K9D1_MDQ30

K8D1_MDQ31

AC6D1_MDQ32

AC7D1_MDQ33

AG8D1_MDQ34

AH9D1_MDQ35

AB6D1_MDQ36

AB8D1_MDQ37

AE9D1_MDQ38

AF9D1_MDQ39

D1_MDQ2

E10D1_MDQ20

E9D1_MDQ21

J11D1_MDQ22

J10D1_MDQ23

G8D1_MDQ24

H10D1_MDQ25

L9D1_MDQ26

L7D1_MDQ27

F10D1_MDQ28

G9D1_MDQ29

D1_MDQ1

D9D1_MDQ10

A8D1_MDQ11

A12D1_MDQ12

A11D1_MDQ13

A9D1_MDQ14

B9D1_MDQ15

F11D1_MDQ16

G12D1_MDQ17

K11D1_MDQ18

K12D1_MDQ19

B12

D1_MDM0 C14

A10D1_MDM1G11D1_MDM2H9D1_MDM3AD7D1_MDM4

D1_MDM5 AJ9

D1_MDM6 AM12

D1_MDM7 AK16

N10D1_MDM8

D15D1_MDQ0

A14

D1_MCK5_B

P7D1_MCKE0M10D1_MCKE1

D1_MCKE2 N8

M11D1_MCKE3

AB9D1_MCS0_BD1_MCS1_B AD10

D1_MCS2_B AC12

D1_MCS3_B AD11

E15D1_MDIC0

G14D1_MDIC1

W6

Y6D1_MCK0_BD1_MCK1

E13

E12D1_MCK1_B

AH11D1_MCK2

AH12D1_MCK2_B

Y7 D1_MCK3AA7

D1_MCK3_BF14

D1_MCK4F13

D1_MCK4_BAG10

D1_MCK5AG11

V8D1_MA4

U6D1_MA5D1_MA6

V10

D1_MA7U9

U7D1_MA8

U10D1_MA9

AA8D1_MBA0AA10D1_MBA1

D1_MBA2 T9

D1_MCAS_BAC10

D1_MCK0

MEMORY #1

mc8641d.2of9.ddr_1.cbga1023

Y10D1_MA0

W8D1_MA1

Y9D1_MA10

T6D1_MA11D1_MA12

T8

D1_MA13AE12

R7D1_MA14D1_MA15

P6

D1_MA2W9

D1_MA3V7

3

18

23C1

23C1

U32

Freescale

2

3

7

8

9

0.01uFC504

0

1

11

0

41

7

7

1

23B1,24B1,25C1

1%18.2R395

24C1

50

51

3

4

5

6

8

R393 0

22

12

13

6

3

23C1,24C1,25C1

1

7

3

12

13

9

10

11

2

3

3

23D1,24D1,25C1

2

0

0R388

21

20

2

14

56

57

R387

36

37

0

0

53

24

60

0R382

54

19

24C1

62

63

0

1

29

16

39

40

0

1

1

6

33

23A1,24A1

23D1,24D1,25D1

VCC_DDRA_IO

23C1

23B8,24B8,25A1

17

2

38

23A1,24A1

23A8,24A8

23

8

24C1

32

30

31

1%R394 18.2

10

0R386

0R384

R385 0

27

R383 0

2

15

45

3

4

25

26

M1_DIFFSERIES M1_MCK5n

28

52

55

1

8

M1_MCK3pM1_MCK3 M1_DIFFSERIES

M1_MCK3nM1_MCK3 M1_DIFFSERIES

M1_MCK4 M1_DIFFSERIES M1_MCK4p

M1_MCK4 M1_DIFFSERIES M1_MCK4n


M1_MCK5

M1_DIFFSERIESM1_MCK0 M1_MCK0p

M1_MCK0nM1_DIFFSERIESM1_MCK0

M1_MCK1pM1_DIFFSERIESM1_MCK1




DIFF_CLKM1_MCLK5pM1_MCK5T DIFF_CLKM1_MCLK5n

2CM_MAX

2CM_MAX

POWER_TRACE M1_MVREF

M1_TSERIES

M1_MCLK3p M1_MCK3T DIFF_CLK

M1_MCLK3n DIFF_CLKM1_MCK3T

M1_MCK4T DIFF_CLKM1_MCLK4pM1_MCK4T DIFF_CLKM1_MCLK4nM1_MCK5T

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_MODT(3:0)

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_MDQS_B(8:0)M1_TDL0

M1_TDL1

M1_TDL2

M1_TDL3

M1_TDL4

M1_TDL5

M1_TDL6

M1_TDL7

M1_TDL8

M1_TDL7

M1_TDL7

M1_TDL7

M1_TDL7

M1_TDL7

M1_TDL7

M1_TDL8

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TDL5

M1_TDL5

M1_TDL5

M1_TDL5

M1_TDL5

M1_TDL5

M1_TDL6

M1_TDL6

M1_TDL6

M1_TDL6

M1_TDL6

M1_TDL6

M1_TDL6

M1_TDL6

M1_TDL7

M1_TDL7

M1_TDL3

M1_TDL3

M1_TDL3

M1_TDL3

M1_TDL3

M1_TDL3

M1_TDL4

M1_TDL4

M1_TDL4

M1_TDL4

M1_TDL4

M1_TDL4

M1_TDL4

M1_TDL4

M1_TDL5

M1_TDL5

M1_TDL1

M1_TDL1

M1_TDL1

M1_TDL1

M1_TDL1

M1_TDL1

M1_TDL2

M1_TDL2

M1_TDL2

M1_TDL2

M1_TDL2

M1_TDL2

M1_TDL2

M1_TDL2

M1_TDL3

M1_TDL3

M1_TDL1

M1_TDL2

M1_TDL3

M1_TDL4

M1_TDL5

M1_TDL6

M1_TDL7

M1_TDL8

M1_TDL0

M1_TDL0

M1_TDL0

M1_TDL0

M1_TDL0

M1_TDL0

M1_TDL0

M1_TDL0

M1_TDL1

M1_TDL1

M1_TDL1

M1_TDL2

M1_TDL3

M1_TDL4

M1_TDL5

M1_TDL6

M1_TDL7

M1_TDL0

M1_TDL8

M1_TDL8

M1_TDL8

M1_TDL8

M1_TDL8

M1_TDL8

M1_MDQS(8:0)

M1_MDQ(63:0)

M1_TDL0

DIFF_CLKM1_MCK1T

M1_MCLK2p DIFF_CLKM1_MCK2T

M1_MCLK2n DIFF_CLKM1_MCK2T

M1_MDM(8:0)

M1_MECC(7:0)M1_TDL8

M1_TDL8

M1_MCKE(3:0)M1_TSERIES

DIFF_CLKM1_MCK0TM1_MCLK0pM1_MCK0T DIFF_CLKM1_MCLK0n

M1_MCLK1p DIFF_CLKM1_MCK1T

M1_MCLK1n

M1_TSERIES M1_MWE*M1_TSERIES M1_MRAS*M1_TSERIES M1_MCAS*

M1_TSERIES

M1_TSERIES

M1_MCS*(3:0)

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TSERIES M1_MBA(2:0)M1_TSERIES

M1_MA(15:0)

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TSERIES

M1_TSERIES

(ECC3)

(AP)

(ECC4)(ECC5)

165, 203, 212, 224

233

102

(ECC6)(ECC7)

NC

Not Supported

126, 135, 147, 156

(DQS9)(DQS10)(DQS11)(DQS12)(DQS13)(DQS14)(DQS15)(DQS16)(DQS17)

(ECC0)(ECC1)(ECC2)

169, 198, 201, 204, 207,

210, 213, 216, 219, 222,

225, 228, 231, 234, 237

GROUND2, 5, 8, 11, 14, 17, 20,

23, 26, 29, 32, 35, 38,

41, 44, 47, 65,

79, 82, 85, 88, 91,

94, 97, 100, 103, 106,

109, 112, 115, 118, 121,

124, 127, 130, 133, 136,

139, 142, 145, 148, 151,

154, 157, 160, 163, 166,

8751

1 2 3 4 5 6 7 8

A

B

D

Date Changed:




C

A

B

D

C


semiconductor

TM

DIMM #1 SPD

PLACE CAPS BY

Gary Milliorn1.03

23HPCN: Argo Navis

DDR-II Interface #1DIMM Socket #1Thursday, February 1, 2007

2:10:20 pm

DIMM PINS

6

ADDR=0x51

432

C715

0.1uF

24

25

26

0.1uF

C700

C714

0.1uF

7

14B8,24D1,27D1,28D1

8

22A1,24A8

5pF

C699

C706

0.1uF

3

22C8,24C1,25C1

4

0

1

50

51

0.1uF

C705

0.1uF

20

4

2

3

SA0240

SA1SA2

101

120SCL

119SDA

WE73

4

VCC_3.3

C716

114

DQS7n113

DQS846

45DQS8n

195ODT0

77ODT1

RAS192

55RC

18RESET

S0193

S176

239

DQS228

DQS2n27

DQS337

DQS3n36

DQS484

83DQS4n

93DQS5

92DQS5n

105DQS6

104DQS6nDQS7

DQ60229

DQ61230

DQ62235

DQ63236

129DQ7DQ8

12

DQ913

7DQS0

6DQS0n

16DQS1

15DQS1n

107

DQ51108

DQ52217

DQ53218

226DQ54DQ55

227

DQ56110

DQ57111

DQ58116

DQ59117

128DQ6

DQ4190

DQ4295

DQ4396

DQ44208

DQ45209

DQ46214

DQ47215

DQ4898

DQ4999

123DQ5

DQ50

159

DQ3280

DQ3381

DQ3486

DQ3587

DQ36199

DQ37200

205DQ38DQ39

206

DQ4122

DQ4089

144

DQ22149

DQ23150

DQ2433

34DQ25DQ26

39

DQ2740

DQ28152

153DQ29

DQ310

158DQ30DQ31

DQ12131

DQ13132

DQ14140

DQ15141

DQ1624

DQ1725

DQ1830

DQ1931

DQ29

143DQ20DQ21

DM2146

DM3155

DM4202

DM5211

DM6223

DM7232

DM8164

3DQ0DQ1

4

DQ1021

DQ1122

168

CKE052

CKE1171

CK_H0185

137CK_H1

CK_H2220

CK_L0186

CK_L1138

221CK_L2

DM0125

DM1134

BA1190

BA254

CAS74

CB042

CB143

CB248

CB349

CB4161

CB5162

167CB6CB7

A14173

A15

A263

A3182

A461

A560

A6180

58A7A8

179

A9177

BA071

55

AT24013-D3-4FFOXCONN

P6

DDR2 DIMM

conn_240_ddr2_vert_1of2

A0188

A1183

A1070

A1157

A12176

A13196

174

0

9

10

7

5

13D1,19C8,24D1,27D1,28D1,#6

2

41

42

1

C711

0.1uF

48

49

15

4

22A8,24A1

22A8,24A1

15

0

22D8,24D1,25D1

22D8,24D1,25C1

22B8,24B1

8

13C1,19C8,24D1,27D1,28D1,#6

3

2

C707

0.1uF

22D8,24C1,25C1

22D8,24C1,25C1

57

58

33

1

12

13

4

5

0.1uF

C713

22D8,24C1,25C11

19

22A1

C698

5pF

0.1uF

C712

2

2

5

6

18

0.1uF

C703

0.1uF

0.1uF

C704

1

0.1uF

C701

VTT_A

C702

56

22A8,24B8,25A1

34

35

21

22

3

38

39

11

12

52

22B8,24D8

17

14

62

22A1

5

6 37

47

10

11

6

7

16

63

122C8,24B1,25D1

0

1

2

6

30

6

7

5

6

59

29

0

1

44

14

43

C710

0.1uF

22A1

0

28

VCC_3.3

0

1

22A1

22A1

C697

5pF

27

0

8

8

7

3

VCC_DDRA_IO

0.1uF

C709

36

22A1

23

13

22C8,24B1,25C1

53

54

0.1uF

C708

1

2

3

9

40

7

VDDQ9181

238VDDSPD

1VREF

60

61

0

0

187

51VDDQ1

VDDQ10191

VDDQ11194

56VDDQ2

62VDDQ3VDDQ4

72

75VDDQ5

78VDDQ6VDDQ7

170

VDDQ8175

66

VDD153

VDD10189

VDD11197

VDD259

VDD364

67VDD4VDD5

69

VDD6172

VDD7178

VDD8184

VDD9

31

32

8

P6

conn_240_ddr2_vert_2of2FOXCONN AT24013-D3-4F

PWR1_SEL_OPT168

PWR1_SEL_OPT250

PWR2_SEL_OPT119

PWR2_SEL_OPT2

MEM_RST*

M1_MCLK2n

M1_MCLK1n

M1_MCLK0pM1_MCLK0n

45

46

4

5

M1_MA(15:0)

M1_MCS*(3:0)

M1_MBA(2:0)

M1_MECC(7:0)

M1_MDM(8:0)

M1_MDQS(8:0) M1_MDQ(63:0)

M1_MCKE(3:0)

M1_MVREF

M1_MDQS_B(8:0)

M1_MODT(3:0)

NC

NC

NC

M1_MWE*

I2C2_SDAI2C2_SCL

M1_MRAS*

M1_MCLK2p

M1_MCLK1p

M1_MCAS*

NC

(ECC3)

(AP)

(ECC4)(ECC5)

165, 203, 212, 224

233

102

(ECC6)(ECC7)

NC

Not Supported

126, 135, 147, 156


(ECC0)(ECC1)(ECC2)

169, 198, 201, 204, 207,

210, 213, 216, 219, 222,

225, 228, 231, 234, 237

GROUND2, 5, 8, 11, 14, 17, 20,

23, 26, 29, 32, 35, 38,

41, 44, 47, 65,

79, 82, 85, 88, 91,

94, 97, 100, 103, 106,

109, 112, 115, 118, 121,

124, 127, 130, 133, 136,

139, 142, 145, 148, 151,

154, 157, 160, 163, 166,

8751

1 2 3 4 5 6 7 8

A

B

D

Date Changed:




C

A

B

D

C


semiconductor

TM

DIMM #2 SPD

PLACE CAPS BY


HPCN: Argo NavisDDR-II Interface #1 DIMM Socket #2


2:10:29 pm

DIMM PINS

6

ADDR=0x52

432

31

32

0

0

5

22A8,23B8,25A1

22A1

22A1

22A1

48

49

15

22D8,23D1,25D1

7

14B8,23D1,27D1,28D1

5pF

13

7

6

5

22D8,23C1,25C1

33

11

5pF

C678 C679

0.1uF

5

4

54

55

4

22A1

VCC_3.3

1

12

13

C688

5pF

C677

VCC_DDRA_IO

2

53

2

3

15

3

0.1uF

C695

0.1uF

C687

0

8

C685

0.1uF

0.1uF

C686

18

0.1uF

C683

C684

0.1uF

2

57

58

16

17

4

9

10

24

322D8,23D1,25C1

13D1,19C8,23D1,27D1,28D1,#6

2

12

C680

0.1uF

C681

0.1uF

RC55

RESET18

193S0

76S1

SA0239

SA1240

101SA2

SCL120

SDA119

73WE

93

92DQS5nDQS6

105

DQS6n104

114DQS7

113DQS7n

46DQS8DQS8n

45

ODT0195

ODT177

192RAS

DQS07

DQS0n6

DQS116

DQS1n15

28DQS2

27DQS2n

37DQS3

36DQS3n

84DQS4DQS4n

83

DQS5

DQ57116

DQ58117

DQ59

DQ6128

229DQ60

230DQ61 235DQ62 236DQ63

DQ7129

12DQ8

13DQ9

DQ4898

99DQ49

DQ5123

107DQ50 108DQ51 217DQ52

218DQ53DQ54

226

227DQ55 110DQ56 111

205DQ38

206DQ39

122DQ4

89DQ40 90DQ41

95DQ42

96DQ43

208DQ44 209DQ45 214DQ46

215DQ47

DQ28DQ29

153

10DQ3

DQ30158

159DQ31

80DQ32 81DQ33 86DQ34 87DQ35

199DQ36

200DQ37

DQ18DQ19

31

9DQ2

DQ20143

144DQ21

149DQ22

150DQ23

33DQ24DQ25

34

39DQ26

40DQ27

152

3DQ0

4DQ1

21DQ10

22DQ11

131DQ12

132DQ13

140DQ14

141DQ15

24DQ16

25DQ17

30

CK_L1

CK_L2221

125DM0

134DM1

146DM2

155DM3

202DM4

211DM5

223DM6

232DM7

164DM8

CB3CB4

161

162CB5CB6

167

168CB7

52CKE0

171CKE1

185CK_H0

CK_H1137

220CK_H2

186CK_L0

138

58A7

179A8

177A9

71BA0

190BA1

54BA2

74CAS

42CB0

43CB1

48CB2

49

A1057

A11176

A12196

A13A14

174

A15173

63A2

182A3

61A4

60A5

180A6

22A1,23A8

8

13C1,19C8,23D1,27D1,28D1,#6

62

AT24013-D3-4Fconn_240_ddr2_vert_1of2

DDR2 DIMM

P3

FOXCONN

188A0

183A1

70

52

47

10

11

5

6

8

22

7

36

1

50

51222D8,23C1,25C1

1

2

3

22B8,23D8

21

37

38

39

14

2

78

170VDDQ7

175VDDQ8

181VDDQ9

VDDSPD238

VREF1

22A1

0.1uF

C682

VDD6178

VDD7184

VDD8187

VDD9

VDDQ151

191VDDQ10

194VDDQ11

VDDQ256

VDDQ362

72VDDQ4VDDQ5

75

VDDQ6

50PWR1_SEL_OPT2

19PWR2_SEL_OPT1

66PWR2_SEL_OPT2

53VDD1

189VDD10

197VDD11

59VDD2

64VDD3VDD4

67

69VDD5

172

0.1uF

0.1uF

C694

AT24013-D3-4FFOXCONNconn_240_ddr2_vert_2of2

P3

68PWR1_SEL_OPT1

2

22D8,23C1,25C1

30

42

14

C693

19

20

8

3

1

4

C696

59

63

0

1

0.1uF

C690

34

0.1uF

25

26

2

6

C689

0.1uF

VTT_A

28

29

0

1

44

6

6

7

43

22B8,23B1

60

61

23

27

22A8,23A1

22A8,23A1

VCC_3.3

35

9

5

3

22A1

3

4

6

56

1

2

3

40

7

4

5

3

41

0

22C8,23B1,25D1

0

8

0.1uF

C691

C692

0.1uF

NC

NC

45

46

22C8,23B1,25C1

22C8,23C1,25C1

7

M1_MRAS*

M1_MA(15:0)

M1_MWE*

M1_MCAS*M1_MCS*(3:0)

M1_MBA(2:0)

M1_MECC(7:0)

M1_MDM(8:0)

I2C2_SDAI2C2_SCL

M1_MDQS(8:0) M1_MDQ(63:0)

M1_MCKE(3:0)

M1_MCLK3nM1_MCLK3p

M1_MCLK4pM1_MCLK4nM1_MCLK5pM1_MCLK5n

M1_MDQS_B(8:0)

M1_MODT(3:0)

NC

MEM_RST*

M1_MVREF

NC

TM

43 8

4 5 6 7

21

D

2 3

Date Changed:


Revision:

8

A

B

Place resistors immediately behind DIMM on a plane


C

Page:

IMAX=20A

Title:Freescale Semiconductor

VTT TERMINATION PLANE

6

One capacitor per four VTT resistors.

VTT SENSE

A

B

D

C

freescale

Place capacitors behind or intermingled with resistors.

75

Place at midpoint of VTT fill plane.

semiconductor

Gary Milliorn1.03

25HPCN: Argo Navis

DDR-II Interface #1 Power and TerminationThursday, February 1, 2007

2:10:39 pm

1

0.1uF

C648

47R

468

C646

0.1uF

2 3

C66822pF

0.1uF

C642

15

C67622pF

1

4 5 6 7

R47

747 47

R48

0

47R

474

7

47R

476

R47

2

R47

347

C655

0.1uF

22pFC672

47

1

0.1uF

C653

C664 C66722pF

22D8,23D1,24D1

C67422pF22pF

R46

547

VTT_A

R46

347 47

R48

9

C665

R46

147 47

R46

2

R48

347

22pF

R48

147 47

R48

2

R47

547

11 12 13

22pFC634

22D8,23D1,24D1

22pF

2 3

0

22pFC641

R46

747

C663

22D8,23C1,24C1

C64322pF

No_Stuff

100K

R478

No_Stuff

R479

100K

C6450.1uF

47R

464

R47

147

100K

R50

0

R46

947 47

R47

0

0

0 1

1

2

0

2

R497

22pFC673

6

22C8,23B1,24B1

8 9

47R

466

7 8

4

1 2 3

4 5

C63910uF

so8

IRF7821PBF

Q13

5 6

2

C651

0.1uF

47R

491

R49

247

C67022pF

R49

047

14

0 1

VCC_3.3

22C8,23B1,24B1

22D8,23C1,24C1

R48

6

R48

847

VTT_A

10

R48

547 47

7 8

4

1 2 3

22pFC649

22pF

so8

IRF7832PBF

Q14

5 6

22pFC666

22A8,23B8,24B8

C637

+

1

4.7K

R50

1

54D8

OSCON

4V

C669

150uF

3

47R

460

3

VCC_5

54D8

0

R487

4.7K

R49

8

2

2 3

VCC_DDRA_IO

R49

447 47

R49

5

14 15

1

47R

493

1 2 3

C658 C65922pF22pF

C65722pF

C636 C640

0.1uF

R49

647

C633

0.1uF 0.1uF

150uF

C671

4V

OSCON

+

0

C66122pF

22C8,23C1,24C1

22D8,23C1,24C1

C64410uF

C66022pF

11S3

S512

14V5IN

VBST20

VDDQSET10

9VDDQSNS

1VLDOIN

2VTT

VTTGND3

VTTREF7

4VTTSNS

U13

tssop20HT

TPS51116PWP

COMP8

15CS

DRVH19

17DRVL

GND5

18LL

MODE6

16PGND

PGOOD13

0

47R

484

+

20A

L9

1UH

1 2

VCC_5

R685

4.7K

22pFC647

OSCON

C6504.7uF10V

12 138 9 10 11

VCC_5

14C2,56C1

10uFC635

4.7K

R49

9

C662

0.1uF

C638

22pFC675

0

22pFC656

0

10uF

22pF 22pFC654

M1_MODT(3:0)

M1_MCKE(3:0)

C652

POWER_TRACE

M1_MCAS*M1_MRAS*

M1_MWE*

M1_MCS*(3:0)

M1_DDR_IOPWRGD

M1_DDR_IOPWR_S3

M1_DDR_IOPWR_S5

M1_MA(15:0)M1_MBA(2:0)

M1_MVREF POWER_TRACE

21


semiconductor

TM

1 2 3 4 5 6 7 8

A

B

D

Date Changed:




C

A

B

D

C

876543


HPCN: Argo NavisDDR-II Interface #2


2:10:48 pm

0

0R452

0R450

R451

R448

R449 0

20

R447 0

0

D2_MECC6M1

D2_MECC7

D2_MODT0AE6

D2_MODT1AG7

AE5D2_MODT2D2_MODT3

AH6

W3D2_MRAS_B

D2_MVREFA8

D2_MWE_BY4

VCC_DDRB_IO

AK2

AL6D2_MDQS7

D2_MDQS7_BAJ6

L6D2_MDQS8

D2_MDQS8_BK5

H6D2_MECC0

J5D2_MECC1

M5D2_MECC2

M4D2_MECC3

G6D2_MECC4

H7D2_MECC5

M2

D2_MDQS1_BA2

F1D2_MDQS2

D2_MDQS2_BF2

K2D2_MDQS3

D2_MDQS3_BK3

AB3D2_MDQS4

D2_MDQS4_BAB2

AF1D2_MDQS5

D2_MDQS5_B AE3

AL1D2_MDQS6

D2_MDQS6_B

D2_MDQ6

AK4D2_MDQ60

AM4D2_MDQ61

AM6D2_MDQ62

AJ7D2_MDQ63

A5D2_MDQ7

C4D2_MDQ8

A3D2_MDQ9

B6D2_MDQS0

D2_MDQS0_BA6

B1D2_MDQS1

D2_MDQ5

AM1D2_MDQ50

AM3D2_MDQ51

AH1D2_MDQ52

AH2D2_MDQ53

AL2D2_MDQ54

AL3D2_MDQ55

AK5D2_MDQ56

AL5D2_MDQ57

AK7D2_MDQ58

AM7D2_MDQ59

D6

AD5D2_MDQ40

AE1D2_MDQ41

AG1D2_MDQ42

AG2D2_MDQ43

AC4D2_MDQ44

AD4D2_MDQ45

AF3D2_MDQ46

AF4D2_MDQ47

AH3D2_MDQ48

AJ1D2_MDQ49

D8

D2_MDQ30L4

D2_MDQ31AA4

D2_MDQ32AA2

D2_MDQ33AD1

D2_MDQ34AD2

D2_MDQ35Y1

D2_MDQ36AA1

D2_MDQ37AC1

D2_MDQ38AC3

D2_MDQ39

C8D2_MDQ4

D2_MDQ20E4

D2_MDQ21G3

D2_MDQ22G2

D2_MDQ23J4

D2_MDQ24J2

D2_MDQ25L1

D2_MDQ26L3

D2_MDQ27H3

D2_MDQ28H1

D2_MDQ29

D5D2_MDQ3

K1

D2D2_MDQ11

A4D2_MDQ12

B4D2_MDQ13

C2D2_MDQ14

C1D2_MDQ15

E3D2_MDQ16

E1D2_MDQ17

H4D2_MDQ18

G1D2_MDQ19

C5D2_MDQ2

D1D2_MDM1

F4D2_MDM2J1D2_MDM3AB1D2_MDM4

D2_MDM5 AE2

D2_MDM6 AK1

D2_MDM7 AM5

K6D2_MDM8

A7D2_MDQ0

B7D2_MDQ1

D3D2_MDQ10

D2_MCKE0N5D2_MCKE1

D2_MCKE2 N2

N3D2_MCKE3

Y3D2_MCS0_BD2_MCS1_B AF6

D2_MCS2_B AA5

D2_MCS3_B AF7

D2_MDIC_0F8

D2_MDIC_1F7

D2_MDM0 C7

B3

F5D2_MCK1

G5D2_MCK1_B

AJ3D2_MCK2

AJ4D2_MCK2_B

V2 D2_MCK3W2

D2_MCK3_BE7

D2_MCK4E6

D2_MCK4_BAG4

D2_MCK5AG5

D2_MCK5_B

N6

D2_MA5D2_MA6

T5

D2_MA7R2

R1D2_MA8

R5D2_MA9

W5D2_MBA0V5D2_MBA1

D2_MBA2 P3

D2_MCAS_BAB5

U1D2_MCK0

V1D2_MCK0_B

U4D2_MA1

V4D2_MA10

R4D2_MA11D2_MA12

P1

D2_MA13AH5

P4D2_MA14D2_MA15

N1

D2_MA2U3

D2_MA3T1

T2D2_MA4

T3

4

51

50

5

10

MEMORY #2

mc8641d.3of9.ddr_2.cbga1023

U32

W1D2_MA0

1

2

3

4

5

3

10

C6320.01uF

54

55

12

4

5

2

3

9

38

39

53

24

25

40

27B1,28B1,29D10

23

8

27A1,28A1

2

2

3

2

28C1

28C1

41

2

3

28C1

28C1

11

17

61

60

28C1

28C1

0R454

44

45

9

5

R453 0

14

21

27D1,28D1,29C1

27C1

6

7

8

7

8

27C1

27C1

27B1,28B1,29C1

4

1

0

R446

27D1,28D1,29D1

6

15

7

8

18

11

12

0

37

49

26

27

6

62

6

1

0

1

27B1,28B1

0

36

59

0

1%R458 18.2

3

27C1,28C1,29C1

1

56

0

1

7

8

3

4

16

27C1

57

58

2

0R456

13

14

3

R455 0

4

5

6

C6310.1uF

1

2

27C1,28C1,29C1

27C1,28C1,29C1

5

6

7

27D8,28D8

34

35

43

22

2

52

47

0

19

13

30

31

27C1

27B8,28B8,29A1

42

28

29

63

0

46

27A1,28A1

27A8,28A8

0

1

2

3

48

R459

15

27C1,28C1,29C1

0

1

27C1

33

R457 0

1%18.2

M2_MCLK5p M2_MCK5T M2_DIFFCLK

M2_MCK5T M2_DIFFCLKM2_MCLK5n

7

1

32

M2_MCK3T M2_DIFFCLKM2_MCLK3pM2_MCLK3n M2_DIFFCLKM2_MCK3T

M2_MCK4T M2_DIFFCLKM2_MCLK4pM2_MCLK4n M2_MCK4T M2_DIFFCLK

M2_MCK3p






M2_MODT(3:0)

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_DIFFSERIESM2_MCK3

M2_TDL5

M2_TDL6

M2_TDL7

M2_TDL8

M2_TSERIES

M2_TSERIES

2CM_MAX

2CM_MAX

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_MDQS_B(8:0)M2_TDL0

M2_TDL1

M2_TDL2

M2_TDL3

M2_TDL4

M2_TDL6

M2_TDL6

M2_TDL6

M2_TDL7

M2_TDL7

M2_TDL7

M2_TDL7

M2_TDL7

M2_TDL7

M2_TDL7

M2_TDL7

M2_TDL8

M2_TDL4

M2_TDL4

M2_TDL4

M2_TDL5

M2_TDL5

M2_TDL5

M2_TDL5

M2_TDL5

M2_TDL5

M2_TDL5

M2_TDL5

M2_TDL6

M2_TDL6

M2_TDL6

M2_TDL6

M2_TDL6

M2_TDL2

M2_TDL2

M2_TDL2

M2_TDL3

M2_TDL3

M2_TDL3

M2_TDL3

M2_TDL3

M2_TDL3

M2_TDL3

M2_TDL3

M2_TDL4

M2_TDL4

M2_TDL4

M2_TDL4

M2_TDL4

M2_TDL0

M2_TDL0

M2_TDL0

M2_TDL1

M2_TDL1

M2_TDL1

M2_TDL1

M2_TDL1

M2_TDL1

M2_TDL1

M2_TDL1

M2_TDL2

M2_TDL2

M2_TDL2

M2_TDL2

M2_TDL2

M2_TDL6

M2_TDL7

M2_TDL0

M2_TDL1

M2_TDL2

M2_TDL3

M2_TDL4

M2_TDL5

M2_TDL6

M2_TDL7

M2_TDL8

M2_TDL0

M2_TDL0

M2_TDL0

M2_TDL0

M2_TDL0

M2_TDL8

M2_MDQS(8:0)

M2_MDQ(63:0)

M2_TDL0

M2_TDL1

M2_TDL2

M2_TDL3

M2_TDL4

M2_TDL5

M2_TDL8

M2_TDL8

M2_TDL8

M2_TDL8

M2_TDL8

M2_TDL8

M2_TDL8

M2_DIFFCLKM2_MCK1TM2_MCLK1nM2_DIFFCLKM2_MCK2TM2_MCLK2p

M2_MCLK2n M2_DIFFCLKM2_MCK2T

POWER_TRACE M2_MVREF

M2_MDM(8:0)

M2_MECC(7:0)

M2_TSERIES

M2_MCS*(3:0)

M2_TSERIES M2_MCKE(3:0)M2_TSERIES

M2_MCLK0p M2_DIFFCLKM2_MCK0T

M2_MCK0T M2_DIFFCLKM2_MCLK0nM2_MCLK1p M2_DIFFCLKM2_MCK1T

M2_TSERIES

M2_TSERIES

M2_MWE*M2_TSERIES

M2_MRAS*M2_TSERIES

M2_MCAS*M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_DIFFSERIESM2_MCK1


M2_TSERIES M2_MBA(2:0)M2_TSERIES

M2_MA(15:0)

M2_TSERIES

M2_TSERIES

M2_TSERIES

M2_MCK0pM2_MCK0 M2_DIFFSERIES




M2_MCK1n

169, 198, 201, 204, 207,

210, 213, 216, 219, 222,

225, 228, 231, 234, 237

GROUND2, 5, 8, 11, 14, 17, 20,

23, 26, 29, 32, 35, 38,

41, 44, 47, 65,

79, 82, 85, 88, 91,

94, 97, 100, 103, 106,

109, 112, 115, 118, 121,

124, 127, 130, 133, 136,

139, 142, 145, 148, 151,

154, 157, 160, 163, 166,

(ECC3)

(AP)

(ECC4)(ECC5)

165, 203, 212, 224

233

102

(ECC6)(ECC7)

NC

Not Supported

126, 135, 147, 156


(ECC0)(ECC1)(ECC2)

D


Engineer:

A

Page:

D

C


C

TM

B

ADDR=0x53

8

PLACE CAPS BYDIMM PINS

semiconductor

5

DIMM #3 SPD

32 7

1

6

3

4

5 6

1

82

B




2:10:56 pm

4

Date Changed:

Time Changed:

7

Revision:

A

Title:Project:

0.1uF

C260

13

7

6

31

32

VCC_DDRB_IO

0.1uF

C259

C253

0.1uF

15

26D8,28D1,29D1

7

14B8,23D1,24D1,28D1

20

8

3

1

0

8

54

55

4

26A1

33

11

19

1

12

13

0

6

13D1,19C8,23D1,24D1,28D1,#6

2

3

8

13C1,19C8,23D1,24D1,28D1,#6

4

18

5

VCC_3.3

126D8,28D1,29C1

48

49

2

53

2

16

17

0

0

26A1

26A1

26A1

12

0

57

58

24

5

26D8,28C1,29C1

C254

0.1uF

5pF

C242

C246

0.1uF

9

10

C258

0.1uF

C245

0.1uF

VDDQ575

VDDQ678

170VDDQ7

175VDDQ8

181VDDQ9

VDDSPD238

VREF1

C257

0.1uF

VDD5172

VDD6178

VDD7184

VDD8187

VDD9

VDDQ151

191VDDQ10

194VDDQ11

VDDQ256

VDDQ362

72VDDQ4

68PWR1_SEL_OPT1

50PWR1_SEL_OPT2

19PWR2_SEL_OPT1

66PWR2_SEL_OPT2

53VDD1

189VDD10

197VDD11

59VDD2

64VDD3VDD4

67

69

11

5

6

8

26A1,28A8

26A8,28B8,29A1


P5

0.1uF

C252

10

C249

0.1uF

C250

0.1uF

0.1uF

C251

22

26A8,28A1

26A8,28A1

0.1uF

C248

5

4

3

4

1

26B8,28D8

21

37

38

39

14

2

239

SA1240

101SA2

SCL120

SDA119

73WE

26A1

0.1uF

C247

DQS7113

DQS7n46

DQS8DQS8n

45

ODT0195

ODT177

192RAS

RC55

RESET18

193S0

76S1

SA0

28DQS2

27DQS2n

37DQS3

36DQS3n

84DQS4DQS4n

83

DQS593

92DQS5nDQS6

105

DQS6n104

114

DQ60230

DQ61 235DQ62 236DQ63

DQ7129

12DQ8

13DQ9

DQS07

DQS0n6

DQS116

DQS1n15

108DQ51 217DQ52

218DQ53DQ54

226

227DQ55 110DQ56 111DQ57

116DQ58

117DQ59

DQ6128

229

90DQ41

95DQ42

96DQ43

208DQ44 209DQ45 214DQ46

215DQ47DQ48

98

99DQ49

DQ5123

107DQ50

DQ3180

DQ32 81DQ33 86DQ34 87DQ35

199DQ36

200DQ37

205DQ38

206DQ39

122DQ4

89DQ40

DQ21149

DQ22150

DQ2333

DQ24DQ25

34

39DQ26

40DQ27

152DQ28DQ29

153

10DQ3

DQ30158

159

131DQ12

132DQ13

140DQ14

141DQ15

24DQ16

25DQ17

30DQ18DQ19

31

9DQ2

DQ20143

144DM2

155DM3

202DM4

211DM5

223DM6

232DM7

164DM8

3DQ0

4DQ1

21DQ10

22DQ11

52CKE0

171CKE1

185CK_H0

CK_H1137

220CK_H2

186CK_L0

138CK_L1

CK_L2221

125DM0

134DM1

146

190BA1

54BA2

74CAS

42CB0

43CB1

48CB2

49CB3CB4

161

162CB5CB6

167

168CB7

A14174

A15173

63A2

182A3

61A4

60A5

180A6

58A7

179A8

177A9

71BA0

62

AT24013-D3-4Fconn_240_ddr2_vert_1of2

DDR2 DIMM

P5

FOXCONN

188A0

183A1

70A10

57A11

176A12

196A13

2

26D8,28C1,29C1

30

43

26B8,28B1

15

3

1

1

50

51

52

47

4

C261

59

63

0

26

026D8,28C1,29C1

7

8

34

0.1uF

28

29

0

1

44

25

0.1uF

C256

VTT_B

5

6

6

73

41

0.1uF

C255

27

VCC_3.3

7

36

35

9

C244

5pF

6

56

23

4

5

1

2

5pF

C243

0

1

2

3

40

7

42

14

60

61

0

26C8,28B1,29D1

NC

NC

45

46

26C8,28B1,29C1

26C8,28C1,29C1

1

26A1

M2_MRAS*

M2_MA(15:0)

M2_MWE*


M2_MBA(2:0)

M2_MECC(7:0)

M2_MDM(8:0)

I2C2_SDAI2C2_SCL

M2_MDQS(8:0) M2_MDQ(63:0)

M2_MCKE(3:0)

M2_MCLK0nM2_MCLK0p


M2_MDQS_B(8:0)

M2_MODT(3:0)

NC

MEM_RST*

M2_MVREF

NC

(ECC3)

(AP)

(ECC4)(ECC5)

165, 203, 212, 224

233

102

(ECC6)(ECC7)

NC

Not Supported

126, 135, 147, 156


(ECC0)(ECC1)(ECC2)

169, 198, 201, 204, 207,

210, 213, 216, 219, 222,

225, 228, 231, 234, 237

GROUND2, 5, 8, 11, 14, 17, 20,

23, 26, 29, 32, 35, 38,

41, 44, 47, 65,

79, 82, 85, 88, 91,

94, 97, 100, 103, 106,

109, 112, 115, 118, 121,

124, 127, 130, 133, 136,

139, 142, 145, 148, 151,

154, 157, 160, 163, 166,

C

freescalesemiconductor

87654321

1 2 3 4 5 6 7 8

A

B

D

Date Changed:




C

A

B

PLACE CAPS BY

3




2:11:04 pm

DIMM PINS


D

TM

DIMM #4 SPDADDR=0x54

0.1uFC330

14

2

6

13C1,19C8,23D1,24D1,27D1,#6

14B8,23D1,24D1,27D1

49

13D1,19C8,23D1,24D1,27D1,#6

20

8

VCC_3.3

15

11

VCC_3.3

26A8,27A1

26A8,27A1

3

2

62

0.1uF

C329

6

7

7

47

6

7

0.1uF

C328

C322

0.1uF

5

63

C327

0.1uF

VTT_B

25

26

26C8,27B1,29C1

5

6

12

26A1

C326

0.1uF

SA1SA2

101

120SCL

119SDA

WE73

27

2

5

DQS846

45DQS8n

195ODT0

77ODT1

RAS192

55RC

18RESET

S0193

S176

239SA0

240

27

DQS337

DQS3n36

DQS484

83DQS4n

93DQS5DQS5n

92

105DQS6

104DQS6nDQS7

114

DQS7n113

230

DQ62235

DQ63236

129DQ7DQ8

12

DQ913

7DQS0

6DQS0n

16DQS1

15DQS1nDQS2

28

DQS2n

DQ52217

DQ53218

226DQ54DQ55

227

DQ56110

DQ57111

DQ58116

DQ59117

128DQ6

DQ60229

DQ61

DQ4295

DQ4396

DQ44208

DQ45209

DQ46214

DQ47215

98DQ48DQ49

99

123DQ5

DQ50107

DQ51108

80

DQ3381

DQ3486

DQ3587

DQ36199

DQ37200

DQ38205

DQ39206

DQ4122

DQ4089

DQ4190

DQ23150

DQ2433

34DQ25DQ26

39

DQ2740

DQ28152

153DQ29

DQ310

158DQ30DQ31

159

DQ32

132

DQ14140

DQ15141

DQ1624

DQ1725

DQ1830

31DQ19

DQ29

143DQ20DQ21

144

DQ22149

155

DM4202

DM5211

DM6223

DM7232

DM8164

DQ03

DQ14

DQ1021

DQ1122

DQ12131

DQ13

CKE1171

CK_H0185

137CK_H1

CK_H2220

CK_L0186

CK_L1138

221CK_L2

DM0125

DM1134

DM2146

DM3

54

CAS74

CB042

CB143

CB248

CB349

161CB4CB5

162

167CB6CB7

168

CKE052

A263

A3182

A461

A560

A6180

A758

A8179

A9177

BA071

BA1190

BA2

FOXCONN

P4

DDR2 DIMM

conn_240_ddr2_vert_1of2

AT24013-D3-4F

A0188

A1183

A1070

A1157

A12176

A13196

174A14

173A15

0.1uF

C320

0.1uF

C321

C318

0.1uF

C319

0.1uF

0

1

26A1

26A1

0.1uF

C317

18

55

54

7

8

14

15

C315

0.1uF

29

1

0

4

19

VCC_DDRB_IO

C314

0.1uF

44

5

26B8,27B1

8

0

1

61

38

9

10

24

6

4

2

26D8,27D1,29D1

21

11

12

37

3

4

5

26C8,27C1,29C1

26D8,27C1,29C1

53

56

2

23

17

0.1uF

C316

1

0.1uF

C324

0.1uF

C325

41

1

2

36

48

0

3

50

3

26A1

28

9

10

5pF

C311

26D8,27D1,29C13

2

8

33

7

8

C323

0.1uF

22

42

226D8,27C1,29C1

3

4

26A1

VDDQ256

VDDQ362

72VDDQ4VDDQ5

75

VDDQ678

170VDDQ7

175VDDQ8

181VDDQ9

VDDSPD238

VREF1

VDD264

VDD3VDD4

67

69VDD5

172VDD6

178VDD7

184VDD8

187VDD9

VDDQ151

191VDDQ10

194VDDQ11


P4

68PWR1_SEL_OPT1

50PWR1_SEL_OPT2

19PWR2_SEL_OPT1

66PWR2_SEL_OPT2

53VDD1

189VDD10

197VDD11

59

45

46

32

3

59

60

26A8,27B8,29A1

13

26D8,27C1,29C1

39

40

7

0

1

31

57

58

51

52

2

16

4

5

0

6

2

30

0

1

26B8,27D8

13

4

3

26C8,27B1,29D1

5pF

C312 C313

5pF

NC

NC

26A1

43

34

35

26A1,27A8

M2_MRAS*

M2_MA(15:0)

M2_MWE*


M2_MBA(2:0)

M2_MECC(7:0)

M2_MDM(8:0)

I2C2_SDAI2C2_SCL

M2_MDQS(8:0) M2_MDQ(63:0)

M2_MCKE(3:0)

M2_MCLK3nM2_MCLK3p


M2_MDQS_B(8:0)

M2_MODT(3:0)

NC

MEM_RST*

M2_MVREF

NC

5432


TM

VTT TERMINATION PLANEPlace resistors immediately behind DIMM on a planePlace capacitors behind or intermingled with resistors.

1

1 2 3 4

DDR-II Interface #2 Power and TerminationThursday, February 1, 2007

2:11:16 pm

8

A

B

5 6 7


Revision:

D

Date Changed:

Austin, Texas 78729Page:Title:

Project:7700 W. Parmer Ln

8

C

A

B

D

IMAX=20A

C

One capacitor per four VTT resistors.

VTT SENSEPlace at midpoint of VTT fill plane.


76


HPCN: Argo Navis

VCC_5

26C8,27C1,28C1

2

VCC_DDRB_IO

1

47R

428

47R

401

VCC_5

4.7K

R686

R39

9

R40

047

C58722pFC588

47

C58622pF 22pF

C589C58522pF

5

0.1uF

C568

2

22pF

VTT_B0.1uF

C561

0 1

0

47R

432

2

47R

397

22pFC591

22pFC595

0

2

10

C576

0.1uF

2

C59222pF

C570

0.1uF 0.1uF

C574C564

0.1uF

R41

247 47

R41

3

22pF

47R

411

3

C59322pF

C594

R42

74747

R40

7

47R

426

1 2 3

10V4.7uFC578

OSCON

+

47R

403

Q11

IRF7821PBF

so8

5 6 7 8

4

R41

847

1

47R

419

R43

147

26D8,27C1,28C1

26C8,27B1,28B1

R42

947 47

R43

0

4

VTT_B

R40

247

3

26A8,27B8,28B8

VCC_5

S311

12S5

V5IN14

20VBST

10VDDQSET

VDDQSNS9

VLDOIN1

VTT2

3VTTGND

7VTTREF

VTTSNS

tssop20HT

U35

8COMP

CS15

19DRVH

DRVL17

5GND

LL18

6MODE

PGND16

13PGOOD

R39

847

10uFC567

TPS51116PWP

R42

247

0

R697

84

26D8,27D1,28D1

47R

424

1

0 1

150uF

C597

4V

OSCON

+

R42

1

3

1

C58422pF

1

47

22pFC580 C582

22pF

11 12 13 1476

C60022pF 22pF

2

0.1uF

C579

1 2 3

R41

647

C603

0.1uF

C590

Q12

IRF7832PBF

so8

5 6 7 8

4

22pFC596

R41

04747

R40

847 47

R40

9

47R

405

R40

6

22pFC604

R40

447

13

C60122pF

157632 12

14C2,56C1

54D8

C56922pF

4 9 10 11

R39

647

R423

0

R414

100K

No_Stuff 2

R42

547

OSCON

4V

C599

150uF+

1UH

L8

20A

1

C56310uF 10uF

C566

R43

64.

7K

26D8,27C1,28C1

10uFC572

0 1

50

26D8,27C1,28C19

C57522pF

15

22pFC598

22pFC571

C581

0.1uF

26C8,27B1,28B1

3

22pFC565

0

26D8,27D1,28D1

22pFC602C562

22pF

3

8

0.1uFC573

R43

44.

7K

R43

510

0K

R43

34.

7K

54D8

R42

04747

R41

7

C583

VCC_3.3

No_Stuff

100K

R415

C57722pF

14

0 2

0.1uF

M2_MCKE(3:0)M2_MWE*M2_MCAS*M2_MRAS*

POWER_TRACE

M2_DDR_IOPWRGD

M2_MODT(3:0)

M2_DDR_IOPWR_S3

M2_DDR_IOPWR_S5

M2_MCS*(3:0)M2_MA(15:0)M2_MBA(2:0)

M2_MVREF POWER_TRACE

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

8

anticipated for ArgoNavis.

Optional: EMI tweaks.

Date Changed:

Time Changed:


C

A

semiconductor

TM

B


5

301.03

HPCN: Argo NavisMC8641 Ethernet Ports


2:11:27 pm

4

D

C

freescale871

4

32

1

6

3 7

A

2 5 6

Page:

NOTE: Series terminations can be omitted

B

D

Engineer:Revision:

Title:

if trace lengths are < 3 inches; this is not

R150

Gary Milliorn

10R168

31B1

31C8

31D8

10

10R165

R170 10

1

10R164

0

2

31A8

1

R163 10 2

31C8

C16710pF

No

_Stu

ff

3

1

31C1

31B1

32A1

No_StuffR172 1K

0

R155

15

No

_Stu

ff

1

31D1

3

31B8

R142 1K

1

18A8,31B1

31C1

31B1

0

No_Stuff 1KR140

1KR9No_Stuff

2

TP19

31C1

AC16ETSEC4_TXD1

AD18ETSEC4_TXD2

AD17ETSEC4_TXD3

AD16ETSEC4_TXD4

AB18ETSEC4_TXD5

ETSEC4_TXD6AB17

AB16ETSEC4_TXD7

AF18ETSEC4_TX_CLK

AF17ETSEC4_TX_EN

AF19ETSEC4_TX_ER

AD13

ETSEC4_RXD2AF13

ETSEC4_RXD3AD14

ETSEC4_RXD4AE14

ETSEC4_RXD5AB15

ETSEC4_RXD6AC14

ETSEC4_RXD7AE17

ETSEC4_RX_CLKAG13

AC15ETSEC4_RX_DV

ETSEC4_RX_ERAF14

AC18ETSEC4_TXD0

AK21ETSEC3_TXD5

AL20ETSEC3_TXD6

ETSEC3_TXD7AL19

AH18ETSEC3_TX_CLK

AH19ETSEC3_TX_EN

AH17ETSEC3_TX_ER

AC13ETSEC4_COL

ETSEC4_CRSAB14

ETSEC4_GTX_CLKAG17

AG14ETSEC4_RXD0

ETSEC4_RXD1

AH15

ETSEC3_RXD6AG16

ETSEC3_RXD7AE19

ETSEC3_RX_CLKAJ18

ETSEC3_RX_DVAG15

AF16ETSEC3_RX_ER

AL21ETSEC3_TXD0

AJ21ETSEC3_TXD1

AM20ETSEC3_TXD2

AJ20ETSEC3_TXD3

AM19ETSEC3_TXD4

AC21

ETSEC2_TX_ENAB21

ETSEC2_TX_ERAB19

AF15ETSEC3_COL

ETSEC3_CRSAE15

ETSEC3_GTX_CLKAG19

ETSEC3_RXD0AJ17

AE16ETSEC3_RXD1

ETSEC3_RXD2AH16

ETSEC3_RXD3AH14

ETSEC3_RXD4AJ19

ETSEC3_RXD5

AC19ETSEC2_RX_DV

ETSEC2_RX_ERAD21

ETSEC2_TXD0AB20

ETSEC2_TXD1AJ23

ETSEC2_TXD2AJ22

ETSEC2_TXD3AD19

ETSEC2_TXD4AH23

ETSEC2_TXD5AH21

ETSEC2_TXD6AG22

AG21ETSEC2_TXD7

ETSEC2_TX_CLK

AE20ETSEC2_CRS

AD20ETSEC2_GTX_CLK

AL22ETSEC2_RXD0

ETSEC2_RXD1AK22

AM21ETSEC2_RXD2

AH20ETSEC2_RXD3

AG20ETSEC2_RXD4

AF20ETSEC2_RXD5

AF23ETSEC2_RXD6

AF22ETSEC2_RXD7

AM22ETSEC2_RX_CLK

ETSEC1_TXD2AG24

ETSEC1_TXD3AG23

ETSEC1_TXD4AE24

ETSEC1_TXD5AE23

AE22ETSEC1_TXD6

ETSEC1_TXD7AD22

ETSEC1_TX_CLKAC22

ETSEC1_TX_ENAB22

ETSEC1_TX_ERAH26

ETSEC2_COLAE21

AK26ETSEC1_RXD2

AK25ETSEC1_RXD3

AM26ETSEC1_RXD4

AF26ETSEC1_RXD5

AH24ETSEC1_RXD6

AG25ETSEC1_RXD7

AK24ETSEC1_RX_CLK

ETSEC1_RX_DVAJ24

AJ25ETSEC1_RX_ER

ETSEC1_TXD0AF25

ETSEC1_TXD1AC23

MC8641D

ETHERNET

mc8641d.4of9.ethernet.cbga1023

AL23EC1_GTX_CLK125

AM23EC2_GTX_CLK125

G31EC_MDC G32

EC_MDIO

ETSEC1_COLAM25

AM24ETSEC1_CRS

AH25ETSEC1_GTX_CLK

ETSEC1_RXD0AL25

AL24ETSEC1_RXD1

No_Stuff R10 1K

1

2

3

4

U32

R169 10

3

1KR159 No_Stuff

10

31B1

0

TP20

10R152

R153

2

No_Stuff1KR176

R174 330

TP21

10R146

31B8

31B8

1KR144

18B8,31B8

31B8R149

2

R151 10

1

31D8

31C8

1KR139

10

1KNo_Stuff

R141 1K

1

3

1KR173

R143

10

31B8

TP22

0

R171 1K

R154

2

3

R167 10

10R166

R161 10

31B1

10R162

R177 1K

10pFC168

No

_Stu

ff

15

R158

17B8

2

3

2

31D1

3

No

_Stu

ff

1KR175

12A8,32B1

R145 10

1

32A1

10R148

1

0

R147 10

18B8,31A1

0

cfg_tsec3_prtcl

cfg_lynx_vdd_sel

3

0

0

cfg_tsec3_reduce

cfg_dram_type1

cfg_dram_type0

NC

NC

TSEC3_RXD(3:0)

TSEC4_TXD(3:0)

NC

cfg_tsec2_prtcl

cfg_tsec2_reduce

cfg_tsec1_reduce

cfg_tsec1_prtcl

NC

cfg_tsec4_reduce

cfg_tsec4_prtcl

TSEC2_TXCTL TSEC2 1CM_MAX

TSEC3_TXCTLTSEC31CM_MAX

TSEC4_TXCTLTSEC41CM_MAX

CFG_ASMP

PHYCLK(0:2)

TSEC1_TXD(3:0)

TSEC2_TXD(3:0)

TSEC2_RXD(3:0)

TSEC3_TXD(3:0)

1CM_MAX

cfg_core2_trans

TSEC3

1CM_MAX

TSEC4

1CM_MAX

TSEC4

TSEC4

1CM_MAX

TSEC4

1CM_MAX

1CM_MAX

TSEC2

1CM_MAX

TSEC2

TSEC31CM_MAX

1CM_MAX TSEC3

TSEC31CM_MAX

TSEC3

NC

TSEC1TSEC1_TXCTL 1CM_MAX

1CM_MAX

1CM_MAX

1CM_MAX

1CM_MAX

TSEC2

TSEC2_RXCLK TSEC2

TSEC2TSEC2_RXCTL

MDC

TSEC3_TXCLKTSEC3

TSEC4 TSEC4_TXCLK

TSEC3

TSEC3

TSEC3

TSEC3

TSEC3_RXCLKTSEC3

TSEC3_RXCTL

TSEC4

TSEC4

TSEC4 TSEC4_RXCTL

TSEC4 TSEC4_RXCLK

MDIO

TSEC2_TXCLK TSEC2

TSEC2

1CM_MAX

TSEC2

1CM_MAX

TSEC2

TSEC2

TSEC2

TSEC1

TSEC1

TSEC1

TSEC1

TSEC1

TSEC1

TSEC1

TSEC1

TSEC1_RXD(3:0)

TSEC1_RXCLK TSEC1

TSEC1TSEC1_RXCTL

TSEC1TSEC1_TXCLK

TSEC4_RXD(3:0)TSEC4

TSEC4

D

C


semiconductor

TM

87

Quad Ethernet Port MACsThursday, February 1, 2007

2:11:35 pm

654321

1 2 3 4 5 6 7 8

A

B

D

A

C

Austin, Texas 78729

Date Changed:




B

TX_CTL_2

TX_CTL_3U5

3


HPCN: Argo Navis

TXD_2_3

TXD_3_0T17

T13TXD_3_1

TXD_3_2V9

V5TXD_3_3

TX_CLK_0V17

U13TX_CLK_1

TX_CLK_2T9

T5TX_CLK_3

U17TX_CTL_0

TX_CTL_1V13

U9

T14TXD_0_1

TXD_0_2V10

V6TXD_0_3

TXD_1_0U18

U14TXD_1_1

TXD_1_2U10

U6TXD_1_3

TXD_2_0V18

V14TXD_2_1

TXD_2_2T10

T6

RXD_3_2

RXD_3_3V3

RX_CLK_0V15

T11RX_CLK_1

RX_CLK_2T7

V2RX_CLK_3

U15RX_CTL_0

RX_CTL_1U11

U7RX_CTL_2

RX_CTL_3U3

TXD_0_0T18

V4

U16RXD_1_0

RXD_1_1U12

U8RXD_1_2

RXD_1_3U4

V16RXD_2_0

RXD_2_1V12

T8RXD_2_2

RXD_2_3T4

T15RXD_3_0

RXD_3_1V11

V7

1

0

18B8,30B8

VSC8244HG

U6

vsc8244.2of3.macs.pbga260

T16RXD_0_0

RXD_0_1T12

V8RXD_0_2

RXD_0_3

0

30A1

3

1

2

0

30C1

2

30C1

0

30B8

30B8

30B1

0

30A830A1

30A8

2

1

0

18A8,30B1

30C1

30C1

30C1

1

2

18B8,30A1

1

30B1

30B1

3

3

2

1

3

30C8

30C8

30C8

30C8

0

0

1

2

30A8

3

2

3

TSEC3

TSEC4_TXCTLTSEC4

TSEC1_RXCLK TSEC1

3

1

30C8

2

30B8

TSEC4

TSEC4

TSEC4

TSEC4

TSEC4_TXCLKTSEC4

TSEC3

TSEC4

TSEC3

TSEC4

TSEC3

TSEC4

TSEC3

TSEC4

TSEC3_TXCTL

TSEC3 TSEC3_RXCLKTSEC3 TSEC3_RXCTL

TSEC4_RXD(3:0)

TSEC4_TXD(3:0)

TSEC4_RXCLKTSEC4

TSEC4_RXCTLTSEC4

TSEC1_TXCLK TSEC1

TSEC3

TSEC3

TSEC3

TSEC3

TSEC2

TSEC2

TSEC2

TSEC2TSEC2_TXCTL

TSEC2

TSEC2

TSEC2

TSEC2

TSEC2TSEC2_RXCLKTSEC2TSEC2_RXCTL

TSEC3 TSEC3_TXCLK

TSEC3_RXD(3:0)

TSEC3_TXD(3:0)

TSEC1_RXD(3:0)

TSEC1_TXD(3:0)

TSEC1

TSEC1

TSEC1

TSEC1

TSEC1_TXCTL TSEC1

TSEC1

TSEC1

TSEC1

TSEC1

TSEC1TSEC1_RXCTL

TSEC2TSEC2_TXCLK

TSEC2_RXD(3:0)

TSEC2_TXD(3:0)

TSEC2

NC

See spec.

Date Changed:

5

1

1 2 3 4 6 7 8

A

B

D


Revision:


Page:Title:

C

A

B

D

C

87654

Gary Milliorn1.03

32HPCN: Argo Navis

Quad Ethernet Port Power and ControlThursday, February 1, 2007

2:11:43 pm

32


semiconductor

TM

14B8

14B8

15C8,19B1,46C8

4.7K

R219TP28

F11

12A8,30D1

VCC_1.2

C18122uF6.3V

+

VCC_1.2

0.1uFC212

TP26

C1880.1uF

OSCON

C1790.1uF0.1uF

C178

0 ohms

R220

0.1uFC183 G4

VSS_8

VSS_9G7

D17XTAL1

XTAL2D18

6.3V22uFC176

OSCON

+

L11

L12VSS_42

VSS_43M4

N4VSS_44

VSS_45N15

P2VSS_46

VSS_47P3

P15VSS_48

VSS_5D7

D8VSS_6

VSS_7F2

K9VSS_32

VSS_33K10

K11VSS_34

VSS_35K12

L3VSS_36

VSS_37L7

L8VSS_38

VSS_39L9

C14VSS_4

L10VSS_40

VSS_41

J8VSS_22

VSS_23J9

J10VSS_24

VSS_25J11

J12VSS_26

VSS_27K2

K3VSS_28

VSS_29K4

VSS_3C13

K7VSS_30

VSS_31K8

G10VSS_12

VSS_13G11

G12VSS_14

VSS_15H7

H8VSS_16

VSS_17H9

H10VSS_18

VSS_19H11

C12VSS_2

H12VSS_20

VSS_21J7

VS

SIO

_1M

7

M8

VS

SIO

_2

VS

SIO

_3M

9

M10

VS

SIO

_4

VS

SIO

_5M

11

M12

VS

SIO

_6

VS

SIO

_7M

15

VSS_1C11

G8VSS_10

VSS_11G9

R4VDDDIG_6

R14VDDDIG_7

R15VDDDIG_8

VDDIO_MAC_1R5

R6VDDIO_MAC_2

VDDIO_MAC_3R7

R9VDDIO_MAC_4

VDDIO_MAC_5R11

R12VDDIO_MAC_6

K15VDD_CTL

VDD_MICROL15

D6

D9VDD33_5

VDD33_6D10

D11VDD33_7

VDD33_8D12

D13VDD33_9

H4VDDDIG_1

H15VDDDIG_2

J4VDDDIG_3

J15VDDDIG_4

P4VDDDIG_5

VDD12_6

VDD12_7M3

N3VDD12_8

VDD12_9R3

C8VDD33_1

VDD33_10F15

G15VDD33_11

VDD33_12L4

R16VDD33_13

VDD33_2D4

D5VDD33_3

VDD33_4

K17TCK

TDIJ16

K16TDO

K18TMS

L16TRST

VDD12_1D14

D15VDD12_2

VDD12_3E4

E5VDD12_4

VDD12_5H3

J3

L18

P16MDC

P18MDINT_0

MDINT_1N16

N17MDINT_2

MDINT_3N18

MDIOP17

REF_FILTC10

REF_REXTC9

RESETM16

M17SOFT_RESET

C2080.1uF

VSC8244HG

U6

vsc8244.3of3.sys_pwr.pbga260

R17CLK125MAC

CLK125MICROM18

L17EECLK

EEDAT

C1980.1uF 0.1uF

C203

C2140.1uF

VCC_3.3

VDD_ENET_IO

C2040.1uF 0.1uF

C209

1%

R218 2.00K

0.1uFC199

C2010.1uF

TP25

2

C1910.1uF0.1uF

C186

F12

0.1uFC185

C1940.1uF

1.0uFC216

0.1uF

0.1uFC213

0.1uFC189

30D8

10

0.1uFC184C180 C211

0.1uF

0.1uFC193

C2070.1uF

0.1uFC196

C1970.1uF 0.1uF

C202C1870.1uF 0.1uF

C192

C2060.1uF

C1900.1uF

TP27

OSCON

C18222uF6.3V

+

0.1uFC205 C210

0.1uF

+

0.1uFC195 C200

0.1uF

VCC_3.3

C215 1.0uF

6.3V22uFC177

OSCON

R217

4.7K

No_Stuff

4.7K

R216

POWER_TRACEPHYPWR_DIG

POWER_TRACE

4.7K

R215

30D8

VCC_3.3

PHYCLK(0:2)

IRQ*(0:11)

PHYRST*

MDIOMDC

NC

NC

NC

NC

GEN_RST*

POWER_TRACE

POWER_TRACEPHYPWR_CORE

2

1 3

0

0

Set

1

3

3

3

0

PHY Address[2]

10

PHY Address[4] 0

LED1[0]

LED2[1]

Value

Advertise Symmetric Pause21

LED3[0]

LED Combine Link/Act

10

00

5

3

10

MAC Interface[1] 1

3Speed/Dup Modes[1]

0

2

3Phy Crossover Mode

0

PHY Address[3]

0

=1

LED0[1]LED0[0]

B

D

=02

Engineer:Revision:

001

6

0

3

bit Definition

0

1

210

MAC Interface[2]

7

3

Advertise Asymmetric Pause2

10

10

111

LED1[1]


LED2[0]

LED3[1]

21

LED PulseStretch/Blink

ActiPHYLink Speed Downshift Ena.

LED4[1]

00

1

1111

0

Resistor

000

4 0000

0000

21

8.25K -> 3.3V

0 -> 3.3V

00

22.6K -> 3.3V

4

CMode

A

1 2 3 5

Date Changed:

Time Changed:

C

A

65

11

3=0

0

RGMII Clock Skew[0] 0101

0 -> GND

0 -> GND

2.26K -> GND

12.1K -> GND

=02

LED4[0]

LED Combine 10/100/1G/ActLED Combine Col/Dup

6

RGMII Clock Skew[1] 1

D

C

1000

1100

1100 8.25K -> 3.3V

2

B

87

Speed/Dup Modes[0]2

NOTE: RGMII-ID mode of VSC8244 usedto implement both TX/RX clock delaysin lieu of routing restrictions.

Austin, Texas 78729

0101

0001

7 8

Gary Milliorn1.03

33HPCN: Argo Navis

Quad Ethernet Port MII InterfacesThursday, February 1, 2007

2:11:52 pmPage:Title:


semiconductor

TM

43

TP38

0

34B1

34B1

34B1

35B1

0R223 1%

TP32

1%

12.1KR227 1%

TP37

TP36

8.25KR221 1%

2.26KR226

R225 0

22.6KR228 1%

0

35D1

0R224

34D1

TP35

TP39

TP29

1%R222 8.25K

TP401

TXVPD_0A15

A11TXVPD_1

A7TXVPD_2

TXVPD_3A3

35B1

35B1

35B1

35B1

35B1

1

A14

TXVPA_2A10

A6TXVPA_3

TXVPB_0A17

A13TXVPB_1

A9TXVPB_2

TXVPB_3A5

A16TXVPC_0

TXVPC_1A12

TXVPC_2A8

A4TXVPC_3

TXVNB_2

TXVNB_3B5

B16TXVNC_0

TXVNC_1B12

TXVNC_2B8

B4TXVNC_3

TXVND_0B15

B11TXVND_1

B7TXVND_2

TXVND_3B3

A18TXVPA_0

TXVPA_1

TXREF_0R13

R10TXREF_1

TXREF_2R8

T3TXREF_3

B18TXVNA_0

TXVNA_1B14

TXVNA_2B10

B6TXVNA_3

TXVNB_0B17

B13TXVNB_1

B9

C3LED2_2

LED2_3E3

LED3_0J17

G17LED3_1

C4LED3_2

LED3_3D3

J18LED4_0

LED4_1G18

LED4_2C5

A1LED4_3

MICRO_REFR18

H16LED0_0

LED0_1F17

LED0_2A2

G3LED0_3

H17LED1_0

LED1_1F18

LED1_2B2

F3LED1_3

LED2_0H18

G16LED2_1

VSC8244HG

U6

vsc8244.1of3.ports.pbga260

F16CMODE0

CMODE1E18

E17CMODE2

CMODE3E16

D16CMODE4

CMODE5C18

C17CMODE6

CMODE7C16

34B1

34B1

035A1

34C1

1

34B1

35B1

35C1

35C1

VCC_3.3

34B1

34B1

0

35B1

1

TP30

34C1

34C1

34C1

34C1

34C1

34C1

34C1

35C1

35C1

35C1

35C1

TP33

35C1

TP31

M3_LEDS(0:1)

2CM_MAX

2CM_MAX

2CM_MAX

2CM_MAX

2CM_MAX

M1_LEDS(0:1)

M2_LEDS(0:1)

2CM_MAX

2CM_MAX

2CM_MAX

CLASS=[ ]MDI1_P0 PHY1_0 DIFF_PHY

35C1

34A1

TP34

CLASS=[ ]MDI0_N1

CLASS=[ ]PHY3_0 DIFF_PHY MDI3_P0

MDI2_P0CLASS=[ ]PHY2_0 DIFF_PHYPHY0_0 DIFF_PHYCLASS=[ ]MDI0_P0

CLASS=[ ]PHY3_0 DIFF_PHY MDI3_N0

MDI2_N0CLASS=[ ]PHY2_0 DIFF_PHY

CLASS=[ ]MDI1_N0 PHY1_0 DIFF_PHY

PHY0_0 DIFF_PHYCLASS=[ ]MDI0_N0

CLASS=[ ]MDI0_N2

MDI3_P1CLASS=[ ]PHY3_1 DIFF_PHY


CLASS=[ ]PHY1_1 DIFF_PHYMDI1_P1





PHY0_1 DIFF_PHY

CLASS=[ ]MDI0_N3








PHY0_2 DIFF_PHY

M0_LEDS(0:1)








PHY0_3 DIFF_PHY

��

��

��

��

��

��

��

��

��

��

��

��

RJ5

RJ7

RJ8

HVCap

G

HVCap

RJ1

RJ8

RJ7

RJ5

RJ4

RJ6

RJ1

RJ2

Y G

Y G

G

RJ3

RJ2

RJ3

RJ6

RJ4

1 2 3 4 6 7 8

A

B

D

Date Changed:



Project:

5

7700 W. Parmer Ln Gary Milliorn 341.03

HPCN: Argo NavisEthernet Ports #1 and #3


2:12:00 pmAustin, Texas 78729

C

A

B

D

C

876

freescale54321


semiconductor

TM

0.1uFC221

C224

33A8

C2230.1uF

33A8

33B8

33A1

33A1

33A8

0.1uF

R230

100

C2220.1uF

100

R231

VCC_3.3

100

R232

10pF

C225

5

11

10

3

2

8

100

R229

19

26

1

S2

7

12

4

9

13

6

14

22

17

25

21

15

16

23

24

18

28

27

30

29

32

31

34

33

20

S1

33A1

33A1

33A1

33A1

33A1

conn.rj45.2x1vert.led.ra

UPPER

LOWER

J38

0845-2R1T-E4

33B10

1

C2180.1uF

0

1

0.1uFC220

33A8

33A1

0.1uFC217

33A8

33A8

33A8

33A8

M0_1GACT*

M2_100ACT*M2_LEDS(0:1) M2_1GACT*

C2190.1uF

M0_100ACT*M0_LEDS(0:1)

MDI0_P3MDI0_N3

MDI0_P2MDI0_N2

MDI0_P1MDI0_N1

MDI0_P0MDI0_N0

MDI2_P3MDI2_N3

MDI2_P2MDI2_N2

MDI2_P1MDI2_N1

MDI2_P0MDI2_N0

��

��

��

��

��

��

��

��

��

��

��

��

RJ5

RJ7

RJ8

HVCap

G

HVCap

RJ1

RJ8

RJ7

RJ5

RJ4

RJ6

RJ1

RJ2

Y G

Y G

G

RJ3

RJ2

RJ3

RJ6

RJ4

Project:

5


C

A

B

D

C

876

freescale5432


HPCN: Argo NavisEthernet Ports #2 and #4


2:12:12 pm

1


semiconductor

TM

1 2 3 4 6 7 8

A

B

D

Date Changed:



C234

33B8

33B8

33B8

0

1

10pF

C2310.1uF 0.1uF

C2330.1uFC22933B8

33B1

33B80

C2270.1uF

100

R234R233

100 100

R236

VCC_3.3

33B1

R235

100

C2320.1uF

33B1

33B1

33B1

33B1

33B8

6

5

11

10

3

2

8

24

18

19

26

1

S2

7

12

4

9

13

33

20

S1

14

22

17

25

21

15

16

23

UPPER

LOWER

J39

0845-2R1T-E4

28

27

30

29

32

31

34

33B1

1

33B1

33B1

33B8

33B8

conn.rj45.2x1vert.led.ra

C2280.1uF0.1uF

C226

MDI1_N1

MDI1_P2

MDI3_P0

MDI3_N1

MDI3_P2

MDI3_N3

M1_LEDS(0:1)

M3_LEDS(0:1)

M1_1GACT*

M3_1GACT*M3_100ACT*

33B8

0.1uFC230

MDI3_N0

MDI3_P1

MDI3_N2

MDI3_P3

MDI1_N0

MDI1_P1

MDI1_N2

MDI1_P3MDI1_N3

M1_100ACT*

MDI1_P0

SYS LINE

C

87654321


semiconductor

TM

7

Serial Port #1

Requires custom cable.

Gary Milliorn1.03

36HPCN: Argo Navis

Serial PortsThursday, February 1, 2007

2:12:20 pm

Serial Port #2

1 2 3 4 5 6 8

A

B

D

Date Changed:




C

A

B

D

19C8

VCC_5

C164

19C8

0.1uFC165

2

3

19C8

C1620.1uF

0.1uF

R5IN12

R5OUT18

V+1

28V-

2VCC

VL14

19C8

No_Stuffheader.1x3J11

17 15

NC

13ON

R1IN6

R1OUT24

8R2IN

22R2OUT

R3IN921

R3OUT10

R4IN20

R4OUT

C1-4

26C2+

27C2-

25D1IN

5D1OUT

23D2IN

7D2OUT

19D3IN D3OUT

11

DRVDIS16

GND

0.1uF

VCC_5 VCC_3.3

lt1331cg.ssop28

U45

C1+3

0.1uFC160

C161

2345

6789

19C8

0.1uFC163

19C8

conn.db9.plug.rtaJ9

1

1CM_MAX

1CM_MAX

1CM_MAX

1CM_MAX

NC

NC

NC

NCNC

UART2_TXD

UART2_RXD

UART1_TXD

UART1_RTS*

UART1_RXD

UART1_CTS*

1CM_MAX

2CM_MAX

NC

NC2CM_MAX

NC

2CM_MAX

2CM_MAX

NC

1CM_MAX

OCT 23 2002

REV 4

see map for

pwr pins

D3 D4

E3 E4

G3 G4

K3 K4

M3 M4

N3 N4

R3 R4

B3 B4

GND

OCT 23 2002

REV 4

see map for

pwr pins

D3 D4

E3 E4

G3 G4

K3 K4

M3 M4

N3 N4

R3 R4

B3 B4

GND

Austin, Texas 78729

Project:

C

A

8

D

C

B

Freescale SemiconductorTitle:freescale Page:

Revision:semiconductor

TM Engineer:

7


HPCN: Argo NavisLocalBus Interface and Demultiplexer


2:12:29 pm

5 62 431

1 2 3 4 5 6 8

A

B

7

Date Changed:

Time Changed:

D

7700 W. Parmer Ln

27R361

F2

H2Y4

K2Y5

Y6M2

Y7P2

T2Y8

No_Stuff

C166

10pF

J3

D1A2

C2D2

D3E2

G2D4

D5J2

L2D6

D7N2

R2D8

B2Y1

Y2D2

Y3

2LET3

2LOET4

J62Q1

2Q2K6

L62Q3

2Q4M6

2Q5N6

P62Q6

2Q7R6

T62Q8

2TOE

R1

T12A8

2B1J5

2B2K5

2B3L5

M52B4

N52B5

2B6P5

R52B7

2B8T5J4

2DIR

1Q5

1Q6F6

G61Q7

1Q8H6

A31TOE

J12A1

2A2K1

L12A3

2A4M1

N12A5

P12A6

2A7

F51B6

1B7G5

H51B81DIR

A4

H31LE

H41LOE

1Q1A6

B61Q2

1Q3C6

D61Q4

E6

C1

D11A4

1A5E1

1A6F1

G11A7

1A8H1

1B1A5

1B2B5

C51B3

1B4D5

1B5E5

4.7K

R13

3

lfbga96_016pad

U42

74ALVCH32973ZKER

1A1A1

B11A2

1A318

19

20

5

6

10

8

9

10

11

7

9

4

14

12

0

15

0

1

1

4

2

5

6

7

15D8,38A1,39A1,41A1

No

_Stu

ff

1

16

28

R122 27

8

4.7K

R12

8

1

2

3

8

19

28

30

28

29

14

15

20

R12

94.

7K

0

R13

04.

7K

R123 27

R124

0

TP17

4.7K

R13

1

R13

64.

7K

27R695

27R694

R693

R120 0

4.7K

VCC_3.3

0R119

27

22

R13

24.

7K

R13

8

14

27

204.7K

R13

5

21

18

20

R13

44.

7K

18

4

12

13

15

12

13

R244

TP18

0

27

R125

27

390R121

4.7K

R16

0

4.7K

R12

6

4.7K

R69

6

11

12

R700

4.7K

5

R12

74.

7K

17

2

10

4

15

0 13

29

31

6

18B8

24

25

14

193

0

15B8,39A1,41C1

30

27

41B1

31

26

25

2

3

16

3

4

LGPL2_LOE_LSDRASK20

LGPL3_LSDCASL21

LGPL4_LGTA_LUPWAIT_LPBSEJ19

LGPL5

M19LSYNC_IN

D20LSYNC_OUT

E21LWE0_LBS0LWE1_LBS1

F21

D22LWE2_LBS2LWE3_LBS3

E20

A23LCS4

LCS5_DMA_DREQ2B23

E23LCS6_DMA_DACK2

F23LCS7_DMA_DDONE2

A24LDP0

E24LDP1

C24LDP2

B24LDP3

F20LGPL0_LSDA10

H20LGPL1_LSDWE

J20

LAD9L22

E19LALE

D21LBCTL

H19LCKE

LCLK0G19

LCLK1L19

LCLK2M20

A22LCS0

C22LCS1

D23LCS2

E22LCS3

LAD27K22

LAD28D25

LAD29

D28LAD3

F25LAD30

H22LAD31

D29LAD4

H25LAD5

B29LAD6

A29LAD7

C28LAD8

LAD17

LAD18E27

G25LAD19

C29LAD2

D26LAD20

E26LAD21

G24LAD22

F27LAD23

A26LAD24

A25LAD25

C25LAD26

H23

LA31G21

A30LAD0

E29LAD1

M22LAD10

A28LAD11

C27LAD12

H26LAD13

G26LAD14

B27LAD15

B26LAD16

A27

K2Y5

Y6M2

Y7P2

T2Y8

U32mc8641d.5of9.localbus.cbga1023

LOCALBUS

J21LA27

K21LA28

G22LA29

F24LA30

C2D2

D3E2

G2D4

D5J2

L2D6

D7N2

R2D8

B2Y1

Y2D2

Y3F2

H2Y4

2LOE

2Q1J6

2Q2K6

L62Q3

2Q4M6

2Q5N6

P62Q6

2Q7R6

T62Q8

2TOEJ3

D1A2

2B1J5

K52B2

2B3L5

M52B4

2B5N5

2B6P5

R52B7

2B8T5J4

2DIR

2LET3

T4

G61Q7

1Q8H6

A31TOE

J12A1

K12A2

L12A3

2A4M1

N12A5

P12A6

2A7R1

T12A8

H51B81DIR

A4

H31LE

1LOEH4

1Q1A6

B61Q2

1Q3C6

D61Q4

E61Q5

1Q6F6

1A5E1

1A6F1

G11A7

1A8H1

1B1A5

1B2B5

C51B3

1B4D5

1B5E5

F51B6

1B7G5

lfbga96_016pad

U40

74ALVCH32973ZKER

1A1A1

B11A2

1A3C1

D11A4

2

41B1

215

15C8,38A1,39A1,41B1

2

4.7K

R13

7

9

27

17

23

24

11

1

5

2

3

1

18A8,41B1

26

8

22

16

21

22

23

28

29

10

0

1

3

9

28

27

26

25

24

0

3123

2

3

21

15A8,18B8,38B1,39A1,41C1

29

29 30

3130

31

16

19

24

25

26

27

0

17

6

7

6

7

3022

13

23

11

15B8,41A1

15A8,18B8,38B1,41B1

3

1

18A8,41C1

4

17

18

7

5

1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

LBUS

LBUS

1CM_MAX

LBUS

LBUS

NC

NC

NC

NC

NC

NC

NC

2CM_MAX

1CM_MAX

LBCTL

LB_CS*(0:7)

LBUSLBUS

LBUSLBUS

LALEX

1CM_MAX

1CM_MAX

LB_LAD(0:31)LB_LAD(0:31)

LBUS

LBUS

LBUS

LBUS

LB_GPL(0:5)

LBUS

LBUS

LBUS

LBUS

LB_CLK(0:1)

1CM_MAX

1CM_MAX

1CM_MAX

1CM_MAX

1CM_MAX

1CM_MAX

LB_A(0:31)2CM_MAX

LB_D(0:31)

LB_LA(27:31)

LBUSLNLBUS

LBUSLNLBUS

LBUSLNLBUS

LBUSLNLBUS

LBUSLNLBUS

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LB_WE*(0:3)

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LB_DP(0:3)

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

LBUS_LATCH

Ax, Bx

Lx

Mx

NC

VCC_3.3

37

GND

27,46

Page:Freescale Semiconductor

semiconductor

TM

Place BGA flash under TSOP flash

8

Alternate flash build option.

654321

1 2

7

4 5

PromJet PinoutNote little-endian conversion

6 7

Header for EmuTec PROMJET attach.Leave 1.5 cm around header clearance.

3

A

B

D

Date Changed:


Austin, Texas 78729 Revision:Gary Milliorn

1.0338

HPCN: Argo NavisLocal Bus - Flash and Flash Emulator

Wednesday, November 8, 2006

10:23:30 am

8

Title:Project:

7700 W. Parmer Ln

C

A

B

D

C

freescale

Vcc

4

9

10

21

0

1

23

12

27

U15

SN74LVC1G86DBVRsot23_5p

1

2

GND

3

5

8

9

11

12

28

23

25

44

45 46

47 48

49

5

50

6

7

35 36

37 38

39

4

40

41 42

43

24

25 26

27 28

29

3

30

31 32

33 34

15 16

17 18

19

2

20

21 22

23

30

14B8,39C1,41C1

J12

header_2x25_05sp

1

10

11 12

13 14

J3

K2GND1

GND2K7J2

OEn

D5RESETn

RY_BYnC4

VCCJ5

H7VIO

C5WEn

D4WPn_ACC

DQ13J6

DQ14H6

J7DQ15

G4DQ2

K4DQ3

K5DQ4

G5DQ5

K6DQ6

DQ7G6

DQ8H3

DQ9

F3A5

E3A6

A7C3

A8D6

C6A9

H2CSn

G3DQ0

K3DQ1

DQ10H4

DQ11J4

DQ12H5

A14F7

A15

A16G7

D3A17

E4A18

F5A19

E2A2

A20F4

A21E5

C2A3

D2A4

26

No_Stuff

S29GL064M90BFIR5U19

bga63

Y

A0G2

F2A1

E6A10

F6A11

D7A12

C7A13

E7

14

15

13

15A8,18B8,37D8,39A1,41C12

27

23

C237

26

VCC_3.3

15A8

0

1

24

15

22

6

5

0.1uF

13

18

3

VCC_3.3

22

15

25

0.1uFC235

12

17

11

10

C2360.1uF

18

2

18

19

11

R237

1K

2

17B8,55B1

11

89

0

14B2,17B8

5

15A8,18B8,37D8,41B1

15

17

19

0.1uFC239

VCC_3.3

15

R238

29

15

14

13

C2380.1uF

16

7

10

28

29

30

26

7

21

VCC_3.3

7

10

13

8

4

VCC_3.3

2

4

38DQ4

40DQ5

42DQ6

44DQ7

30DQ8

32DQ9

28OE

12RESET

47VIO

11WE

14WPCE

29DQ0

31DQ1

34DQ10

36DQ11

39DQ12

41DQ13

43DQ14

DQ1545

33DQ2

35DQ3

A2

A2010

9A21

22A3

21A4

20A5

19A6

18A7

8A8

7A9

ACC13

26

6A10

5A11

4A12

3A13

2A14

1A15

48A16

17A17

16A18

15A19

23

VCC_3.3

9

11

8

am29lv641d.tsop48w

U17

25A0

24A1

12

12

13

0

25

24

9

8

16

24

TP42

29

20

TP41

19

16

10

12

14

13

11

28

VCC_3.3

15A8

20

21

9

14

22

3

5

6

3

20

30

4

5

6

7

14

17

27

CFG_FLASHWP*

LB_A(0:31)

CFG_FLASHBANK

LB_GPL(0:5)

OE*

FOE*

LB_WE*(0:3)

15D8,37D8,39A1,41A1

10

1

15C8,37D8,39A1,41B1

14

A21

A22

A19

A17

A6

A4

A2

VCCSHORT_POWER

NCWR_L*

NCWR_H*

FWE*

FCS*

LB_RST*

A7

A5

A1

A3

A0

D8

D9

D10

D11

D7

D6

D5

D4

A16

A15

A13

A11

A9

D0

D1

D2

D3

D12

D13

D14

D15

A14

A12

A10

A8

A23

A20

A18

LB_D(0:31)

NCNC

GND

NCNC

NCNC

CS*

PJCS*

GND

2CM_MAX

��

��

��

��

��

��

��

��

��

��

LB_D[4]

A06

LB_A[16]

Compact Flash Mapping

Pin2

876

A03

432

LB_A[31]20

8 A1010 A09

6 7 8

3

B

D

Date Changed:

5LB_D[0]

A0516 A0417

22 D0123

A08

44 REG-

Page:

LB_D[3]LB_D[2]LB_D[1]

5

LB_A[22]LB_A[23]

D03

LB_A[25]LB_A[26]LB_A[27]

18 LB_A[29]LB_A[30]

semiconductor

LB_D[7]LB_D[6]LB_D[5]

Project:

LB_A[21]

7700 W. Parmer Ln

11

C

A

B

D044 D05

4

D066 D07

2:12:42 pm

LB_A[24]

A

D

C


12 A0714

Title:

Function Connection

15

Austin, Texas 78729

D02

1

1 2 3

A0219 A01

TM

A0021 D00

5

LB_A[28]


Revision:Gary Milliorn

1.0339

HPCN: Argo NavisCompact Flash Interface


50

6

7

8

9

VCC_3.3

C2400.1uF

41

42

43

44

45

46

47

48

49

530

31

32

33

34

35

36

37

38

39

4

40

21

22

23

24

25

26

27

28

29

3

11

12

13

14

15

16

17

18

19

2

20

6

5

15C8,37D8,38A1,41B1

15D8,37D8,38A1,41A1

conn.cflash.vert.smJ13

1

10

26

27

28

29

30

31

15C8

16

1

2

0

1

25

24

23

22

21

15A8,18B8,37D8,38B1,41C1

1K

R240

15B8,37D8,41C1

15C8

R241

10K

2

14B8,38C1,41C1

7

3

2

4

VCC_3.3

4

R239

1K

CF_RDYBSY*

LB_RST*

CF_CS1*

LB_CS*(0:7)

NC

CF_WE*

NC

LB_GPL(0:5)

CF_WAIT*

NC

LB_D(0:31)LB_A(0:31)

C2410.1uF

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

CF_CE1*

NC

CF_CD*

CF_OE*

8K x 8 serial EEPROM

VCC_3.38

GND4

serial EEprom

256 x 8

serial EEprom

256 x 8

C

A

B

D

C

8765432


Address = 0x50 or 0x51.

Address = 0x57

Address = 0x56

semiconductor

TM

1

1 2 3

REMOTE PROGRAMMINGHEADER

SYSTEM EEPROM / MAC Address

Gary Milliorn1.03

40HPCN: Argo Navis

Miscellaneous I2C Bus DevicesThursday, February 1, 2007

2:12:50 pm

PROCESSOR INIT EEPROM

7 8

Project:

5 64

DINK ENV EEPROM

A

B

D

Date Changed:


Revision:Page:Title:7700 W. Parmer Ln

Austin, Texas 78729

C805

17D8

1A0

A12

3A2

4G

ND

SCL6

SDA5

VC

C8

7WP

0.1uF

A01

2A1

A23

GN

D4

6SCL

5SDA

8V

CCWP

7

U55at24c02.tssop8

1 2A

1

3A

2

6CLK

DATA5

7WC

VCC_3.3

at24c02.tssop8

U26

header.1x4J25

1

2

3

4

17C8

U27at24c64a.s08

A0

C3860.1uF

13C1,19C8,23D1,24D1,27D1,#6

VCC_3.3

13D1,19C8,23D1,24D1,27D1,#6

VCC_3.3

4

GND

5READY

3SCL_I

2SCL_O

SDA_I6

SDA_O7

VCC

8

19C8

19C8

NC

I2C2_SDA

I2C1_SDAI2C1_SCL

CFG_SERROM_ADDR

NC

CFG_IDWP

I2C2_SCL

NC

ltc4300_1.ms8

U21

ENABLE1

25

24

23

22

21

20

CLK_EVENCKQ_0_33

CLK_ODDCKQ_1_236

D10ODDPOD1-230

D7ODD

D6ODD

D5ODD

D4ODD

D3ODD

D2ODD

D1ODD

D0ODD

POD1-7

POD1-6

POD1-5

POD1-4

POD1-3

POD1-1

POD1-0

POD0-7

POD0-6

POD0-5

POD0-4

POD0-3

POD0-2

POD0-1

POD0-0

35

34

33

32

31

29

28

27

26

POD2-5

POD2-4

POD2-3

POD2-2

POD2-1

POD2-0

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

HPTEKPIN

D15ODD

D14ODD

D13ODD

D12ODD

D11ODD

D9ODD

D8ODD

:

19

38

37

:

20

D15EVEN

D14EVEN

D13EVEN

D12EVEN

D11EVEN

D10EVEN

D9EVEN

D8EVEN

D7EVEN

D6EVEN

D5EVEN

D4EVEN

D3EVEN

D2EVEN

D1EVEN

D0EVEN

POD3-7

POD3-6

POD3-5

POD3-4

POD3-3

POD3-2

POD3-1

POD3-0

POD2-7

POD2-6

GROUND

39,40,41,42,43

Note: This connector

is numbered Tek style

1

2

25

24

23

22

21

20

CLK_EVENCKQ_0_33

CLK_ODDCKQ_1_236

D10ODDPOD1-230

D7ODD

D6ODD

D5ODD

D4ODD

D3ODD

D2ODD

D1ODD

D0ODD

POD1-7

POD1-6

POD1-5

POD1-4

POD1-3

POD1-1

POD1-0

POD0-7

POD0-6

POD0-5

POD0-4

POD0-3

POD0-2

POD0-1

POD0-0

35

34

33

32

31

29

28

27

26

POD2-5

POD2-4

POD2-3

POD2-2

POD2-1

POD2-0

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

HPTEKPIN

D15ODD

D14ODD

D13ODD

D12ODD

D11ODD

D9ODD

D8ODD

:

19

38

37

:

20

D15EVEN

D14EVEN

D13EVEN

D12EVEN

D11EVEN

D10EVEN

D9EVEN

D8EVEN

D7EVEN

D6EVEN

D5EVEN

D4EVEN

D3EVEN

D2EVEN

D1EVEN

D0EVEN

POD3-7

POD3-6

POD3-5

POD3-4

POD3-3

POD3-2

POD3-1

POD3-0

POD2-7

POD2-6

GROUND

39,40,41,42,43



1

2

25

24

23

22

21

20

CLK_EVENCKQ_0_33

CLK_ODDCKQ_1_236

D10ODDPOD1-230

D7ODD

D6ODD

D5ODD

D4ODD

D3ODD

D2ODD

D1ODD

D0ODD

POD1-7

POD1-6

POD1-5

POD1-4

POD1-3

POD1-1

POD1-0

POD0-7

POD0-6

POD0-5

POD0-4

POD0-3

POD0-2

POD0-1

POD0-0

35

34

33

32

31

29

28

27

26

POD2-5

POD2-4

POD2-3

POD2-2

POD2-1

POD2-0

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

HPTEKPIN

D15ODD

D14ODD

D13ODD

D12ODD

D11ODD

D9ODD

D8ODD

:

19

38

37

:

20

D15EVEN

D14EVEN

D13EVEN

D12EVEN

D11EVEN

D10EVEN

D9EVEN

D8EVEN

D7EVEN

D6EVEN

D5EVEN

D4EVEN

D3EVEN

D2EVEN

D1EVEN

D0EVEN

POD3-7

POD3-6

POD3-5

POD3-4

POD3-3

POD3-2

POD3-1

POD3-0

POD2-7

POD2-6

GROUND

39,40,41,42,43



1

2

D

Time Changed:Title:

Date Changed:Engineer:

Revision:

Project:Page:7700 W. Parmer Ln

Austin, Texas 78729

C

A

B

D

C

TM

8


semiconductor

765


HPCN: Argo NavisLocal Bus Debug


2:13:00 pm

4321

1 2 3 4 5 6 7 8

A

B

13

14

3

1

2

6

7

8

9

4 11

12

2

TP62

28

24

9

8

7

6

5

4

38SCL

SDA37

17

16

15

14

13

12

11

10

30

31

32

33

34

35

19

18

22

23

24

25

26

27

28

29

conn.mictor.38J23

3

36

GROUND2

1LA5V

20

21

2

1

0

18A8,37A8

14B8,38C1,39C1

2

0

37D8

DATA

10

9

0

15A8,18B8,37D8,38B1,39A1

0

27

21

29

15B8,37D8

1

15A1

12 19

11

4

3

2

1

0

3

21

22

238

7

6

16

17

3

0

TP63

1

0

15A8,18B8,37D8,38B1

15C8,37D8,38A1,39A1

5

27

15

18

17

16

2

37C83

5

4

38SCL

SDA37

20

TP64

12

11

10

9

8

7

6

5

35

19

18

17

16

15

14

13

27

28

29

30

31

32

33

34

2

LA5V1

20

21

22

23

24

25

26

SCL38

37SDA

J21conn.mictor.38

STAT

3

36

GROUND

11

10

9

8

7

6

5

4

19

18

17

16

15

14

13

12

28

29

30

31

32

33

34

35

LA5V

20

21

22

23

24

25

26

27

14

15D8,37D8,38A1,39A1

J22conn.mictor.38

ADDR

3

36

2GROUND

1

1

19

1

0

15B8,37D8,39A1

18A8,37A8

4

26

27

15

29

30

31

23

13 18

5

20

24

25

30

22

28

29

30

31

6

7

10

26

25

28

31

NC

NC

LB_A(0:31)

LB_D(0:31)

LB_CLK(0:1)

LB_RST*

LB_LA(27:31)

PIXIS_DEBUG(0:1)

4

3

5

NC

NC

NC

NC

LBCTL

NC

NC

LB_CS*(0:7)

LB_WE*(0:3)

LB_GPL(0:5)

LB_DP(0:3)

LALEX

NC

NC

NC

TXRX

5 62 84

B

D

Date Changed:

7

A

Engineer:Revision:

Page:Title:Time Changed:


C

A


HPCN: Argo NavisMC8641D PCIExpress/SERDES/Lynx Port 2


2:13:09 pm

B

Project:

C


TM

SerDes TX AC Coupling Caps

D

Must have symmetric placement and near the port pins


7643 81

1

5

3

2

TP

73

100 1%

TP71

TP72

13C8

13C8

TP69

6

4

R303

C348

C347

0.1uF

5

0

4

2

3

43C1

0.1uF

1.0uFC331

0.1uF

C343

3

43C8

0.1uF

C341

R688

2

2

3

R687 330TP70

4

330

R708

No_Stuff

7

5

330

No_Stuff

R709 330

330

330R706

R707

C335

0.1uF

C340

0.1uF

C346

C345

0.1uF

7

0.1uF

C336

VCC_SERDES

0.1uF

5

6

6

7

C344

0.1uF

C342

0.1uF

0.1uF

6

7

4

5

0.1uF

C339

3

C333

SD_2_TX6AJ27

SD_2_TX6_BAJ28

SD_2_TX7AL27

SD_2_TX7_BAL28

AD25

AD26

W26

W27

43C1

2

Y25

SD_2_TX1AA27

SD_2_TX1_BAA28

SD_2_TX2AB25

SD_2_TX2_BAB26

SD_2_TX3AC27

SD_2_TX3_BAC28

SD_2_TX4AE27

SD_2_TX4_BAE28

SD_2_TX5AG27

SD_2_TX5_BAG28

SD_2_RX5

SD_2_RX5_BAJ31

AK30SD_2_RX6

SD_2_RX6_BAK29

AL32SD_2_RX7

SD_2_RX7_BAL31

AG32

AG31

V28

W28

SD_2_TX0Y24

SD_2_TX0_B

Y30SD_2_RX0

SD_2_RX0_BY29

AA32SD_2_RX1

SD_2_RX1_BAA31AB30

SD_2_RX2

SD_2_RX2_BAB29

AC32SD_2_RX3

SD_2_RX3_BAC31

AH30SD_2_RX4

SD_2_RX4_BAH29

AJ32

U32

cbga_31x31_1mm_skt

AF30AGND_SRDS2

AF32AVDD_SRDS2

AD30SD_2_DLL_TPA

SD_2_DLL_TPDAD29

SD_2_IMP_CAL_RXAA26

SD_2_IMP_CAL_TXAM29

SD_2_PLL_TPAAF31

SD_2_PLL_TPDAF29

SD_2_REF_CLKAE32

SD_2_REF_CLK_BAE31

1%200R304

SERDES 2

mc8641d.7of9.serdes_2.cbga1023

TP

74

TP

75

R302

1

1

1

C3320.033uF

TP

76

0.1uF

C337

43C80

0

0

1

C338

0.1uF

SD2_NC1

0.1uF

C334

1

SD2_RSV0_B

SD2_RSV1_B

SD2_NC2

SD2_NC3

SD2_NC0

SD2_RX3

DIFF_SERDESSD2_RX2CLASS=[ ]

DIFF_SERDESCLASS=[ ]SD2_RX1


DIFF_SERDESCLASS=[ ]SD2_RX6 DIFF_SERDES_AC

1CM_MAX

1CM_MAX

SH

OR

T_P

OW

ER

SD2_RSV1

SD2_RSV1





DIFF_SERDESCLASS=[ ]

SD2_RX0







1CM_MAX

SD2_TX4

CLASS=[ ] DIFF_SERDESSD2_TX5

DIFF_SERDESSD2_TX5CLASS=[ ]





SD2_TX_P(7:0)

SD2_TX_N(7:0)

SD2_RX_P(7:0)SD2_RX_N(7:0) DIFF_SERDESCLASS=[ ]

DIFF_SERDES








CLASS=[ ] DIFF_SERDES

CLASS=[ ] REFCLK_SD2nSD2_CLK DIFF_SERIES


DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

SD2_TX0CLASS=[ ]

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

CLASS=[ ] REFCLK_SD2pSD2_CLK DIFF_SERIES

+12V

B8 A9 A10

A49 A51 B52 B53 A54

A55 B56 B57 A58 A59

B60 B61 A62 A63 B64

B65 A66 A67 B68 B69

A70 A71 B72 B73 A74

A75 B76 B77 A78 A79

B80 A82

B1 B2 B3 A2 A3

GND

B4 A4 B7 A12 B13 A15

B16 B18 A18 A20 B21

B22 A23 A24 B25 B26

A27 A28 B29 A31 B32

A34 B35 B36 A37 A38

B39 B40 A41 A42 B43

B44 A45 A46 B47 B49

A50 B82 A19

NC

B3 B12 B30 A32 A33

+3.3V

Engineer: Page:Project:

Austin, Texas 78729

B

D

LANE REVERSAL

C

Both RX and TX are reversed

freescale

to ease the routing for the


MPC8641D in an ATX chassis.

semiconductor

C

TM

87654321

1 2 3 4 5 6 7 8

A

B

D

Date Changed:

Time Changed:

1

Gary Milliorn1.03

43HPCN: Argo Navis

PCIExpress 8X Slot 1Thursday, February 1, 2007

2:13:19 pmRevision:Title:7700 W. Parmer Ln

A

SMDAT TCKA5

TDIA6

A7TDO

TMSA8

TRSTB9B11

WAKE_N

0

1

PETp7

B50PETp8

B54PETp9

PRSNT1A1

PRSNT2_1B17

B31PRSNT2_2

PRSNT2_3B48

PRSNT2_4B81

A14REFCLKN

REFCLKPA13

SMCLKB5

B6

B62PETp11

B66PETp12

B70PETp13

B74PETp14

B78PETp15

B23PETp2

B27PETp3

PETp4B33

B37PETp5

B41PETp6

B45

B24

PETn3B28

PETn4B34

PETn5B38

PETn6B42

PETn7B46

PETn8B51

B55PETn9

B14PETp0

B19PETp1

B58PETp10

PERp7

A52PERp8

A56PERp9

PETn0B15

PETn1B20

PETn10B59

B63PETn11

B67PETn12

B71PETn13

PETn14B75

B79PETn15

PETn2

PERp11A64

PERp12A68

PERp13A72

A76PERp14

A80PERp15

A25PERp2

A29PERp3

A35PERp4

PERp5A39

A43PERp6

A47

PERn2

A30PERn3

A36PERn4

A40PERn5

A44PERn6

PERn7A48

A53PERn8

PERn9A57

A16PERp0

A21PERp1

A60PERp10

B10P3.3V_AUX

A11PERST

A17PERn0

A22PERn1

A61PERn10

PERn11A65

PERn12A69

PERn13A73

A77PERn14

PERn15A81

A26 5

42B1

5

0

42A8

pciexpress_conn_x16

J24

conn_pciexpress16

2

1

1

6

6

042B1

13C8

13C8

5

4

4

3

2

C3520.1uF

VCC_12

3

0.1uFC351

TP77

0

C3500.1uF

7

42A8

13D1,19C8,23D1,24D1,27D1,#6

13C1,19C8,23D1,24D1,27D1,#6

VCC_HOT_3.3

0.1uFC349

7

7

5

6

6

7

4

VCC_3.3

C3530.1uF

54D8

2

2

3

3

14D2,45A1

4

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

SD2_RX_P(7:0)

SD2_RX_N(7:0)

SD2_TX_P(7:0)

SD2_TX_N(7:0)

I2C2_SDAI2C2_SCL

REFCLK_SLOT1pREFCLK_SLOT1n

PEX_RST*S1_PRSNT*

NC

NC

NC

NC

TXRX

Engineer:Revision:

Page:Title:Project:


C

TM

A

B

D

C


semiconductor



HPCN: Argo NavisMC8641D PCIExpress/SERDES/Lynx Port 1


2:13:27 pm


87654321

1 2 3 4 5 6 7 8

A

B

D

Date Changed:

Time Changed:

1

TP

101

R310 100 1%

2

3

1

R689

0.1uF

C399

6

6

7

1.0uFC387

330

1

C3880.033uF

13B8

TP

102

TP

103

R309

VCC_SERDES

13B8

0

2

TP97

45B1,46A1

TP100

C398

0.1uF

0.1uF

C404

4

R690 330

C403

0.1uF

330R704

3

4

R703 330

330R702

No_Stuff

45B8,46A1

TP98

0

1

1

0.1uF

0.1uF

C397

0.1uF

C395

C396

0.1uF

C393

C394

0.1uF

0.1uF

C392

0.1uF

C390

C391

0.1uF

C402

C389

0.1uF

6

6

7

7

2

0.1uF

45B8,46A1

3

3

4

5

5

0

P28

P29

K24

K25

45B1,46A1

2

TP

104

SD_1_TX3P24

SD_1_TX3_BP25

SD_1_TX4R26

SD_1_TX4_BR27

SD_1_TX5T24

SD_1_TX5_BT25

SD_1_TX6U26

SD_1_TX6_BU27

SD_1_TX7V24

SD_1_TX7_BV25

SD_1_RX7_BW31

R32

R31

H30

H29

SD_1_TX0L26

SD_1_TX0_BL27

SD_1_TX1M24

SD_1_TX1_BM25

SD_1_TX2N26

SD_1_TX2_BN27

SD_1_RX2

SD_1_RX2_BL31

M30SD_1_RX3

SD_1_RX3_BM29

T30SD_1_RX4

SD_1_RX4_BT29

U32SD_1_RX5

SD_1_RX5_BU31

V30SD_1_RX6

SD_1_RX6_BV29

W32SD_1_RX7

SD_1_IMP_CAL_RXJ28

SD_1_IMP_CAL_TXY26

SD_1_PLL_TPAT28

SD_1_PLL_TPDU28

SD_1_REF_CLKN32

SD_1_REF_CLK_BN31

J32SD_1_RX0

SD_1_RX0_BJ31

K30SD_1_RX1

SD_1_RX1_BK29L32

4

5

5

SERDES 1

mc8641d.6of9.serdes_1.cbga1023

U32

cbga_31x31_1mm_skt

P30AGND_SRDS1

AVDD_SRDS1P32

P31SD_1_DLL_TPA

SD_1_DLL_TPDN28

TP99

7

1%200R311

C401

0.1uF

0

R705 330

No_Stuff

C400

0.1uF


SD1_TX7 DIFF_SERDESCLASS=[ ]

1CM_MAX

SD1_RSV0_B

SD1_RSV1

SH

OR

T_P

OW

ER

SD1_RSV1

SD1_RSV1_B










SD1_TX6

SD1_NC3

SD1_NC2






SD1_TX5

SD1_RX7



SD1_RX7

1CM_MAX

1CM_MAX

SD1_NC0

REFCLK_SD1pREFCLK_SD1n

DIFF_SERDES

CLASS=[ ] DIFF_SERDESSD1_RX3


SD1_RX4CLASS=[ ] DIFF_SERDES










SD1_RX3CLASS=[ ]

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

SD1_RX_P(7:0) CLASS=[ ] DIFF_SERDESSD1_RX0

SD1_RX_N(7:0)

SD1_TX_P(7:0)

DIFF_SERDES_AC

DIFF_SERDES_AC

SD1_TX_N(7:0)

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

DIFF_SERDES_AC

SD1_NC1

DIFF_SERDES_AC

+12V

B8 A9 A10

A27 A28 B29 A31 B32

NC

B22 A23 A24 B25 B26

B16 B18 A18 A20 B21

B4 A4 B7 A12 B13 A15

B1 B2 A2 A3

GND

B3 B12 B30 A19 A32

+3.3V

4

MidBus Tap is placed in the middle (obviously)

A

B

6

Engineer:7700 W. Parmer Ln

MidPoint Tap Clock

5

Time Changed:

C

A

B

Title:

D

Place near ’midbusprobe’

Austin, Texas 78729semiconductor

TM

This pinout is optimized for uninterruptedrouting. Connections are made with flyingleads, so any (reasonable) pinout may be used.

Date Changed:


D

Project:freescale


76 8

C

5


and all signals flow THROUGH the pads.

1

2 3


HPCN: Argo NavisPEX Alternate Slot + MidBus Probe


2:13:35 pm

1

2

7 84

3

Revision:Page:

C7890.1uF

TP169

5

6

1

7

13D1,19C8,23D1,24D1,27D1,#6

3

54D8

VCC_HOT_3.3

7

7

4

6

7

6

44

GND8 5

GND9 11

5

5

6

6

GND11 23

GND12 29

GND13 35

GND14 41

GND15 47

GND214

20GND3

GND426

32GND5

GND638

GND7

CMn 39

37CMp

CNn42

40CNp

CPn 45

43CPp

CQn48

46CQp

GND02

8 GND1

GND10 17

19

24CHn

CHp22

CIn 27

25CIp

CJn30

28CJp

33CKn

CKp 31

36CLn

CLp34

6

4CBp

9CCn

CCp 7

12CDn

CDp10

CEn 15

13CEp

CFn18

16CFp

21CGn

CGp

TDI

A7TDO

A8TMS

B9TRSTWAKE_N

B11

44A8,46A1

pciexpress_midbusprobe_gen_x16J37

CAn 3

1CAp

CBn

PETp2B23

PETp3B27

A1PRSNT1

B17PRSNT2_1

PRSNT2_2B31

REFCLKNA14

A13REFCLKP

B5SMCLK

SMDATB6 A5

TCK

A6

A30

PERp0A16

PERp1A21

PERp2A25

PERp3A29

B15PETn0

B20PETn1

B24PETn2

B28PETn3

PETp0B14

PETp1B19

7

13C8

No_Stuff

J36

pciexpress_conn_x4

P3.3V_AUXB10

PERSTA11

PERn0A17

PERn1A22

PERn2A26

PERn3

4

13C1,19C8,23D1,24D1,27D1,#6

5

header_1x3_smFTR-103-02-S-S

J35

1

2

3

13C8

0

0

2

2

4

5

7

0.1uFC787

44A8,46A1

1

1

0

2

44B1,46A1

3

3

VCC_12

0.1uFC788

2

0

7

1

C7860.1uF

7

4

5

5

6

5

3

13C8

14D2,43B1

4

4

VCC_3.3

44B1,46A1

4

6

6

4

0.1uFC785

13C8

SD1_TX_N(7:0)

SD1_TX_P(7:0) SD1_RX_P(7:0)

SD1_RX_N(7:0)

REFCLK_TAPn

REFCLK_TAPp

S2_PRSNT*

NC

NC

NC

NC

NC

I2C2_SCL

REFCLK_SLOT2nREFCLK_SLOT2p

PEX_RST*

I2C2_SDA

CPU

PCI-Express

NC


semiconductor

TM

VDD_SBCORE_1.8 = VCC_1.8V

PLACE CAPS CLOSE TO SB

PLACE CAPS CLOSE TO SB VDD18M_CORE PINS

4

PLACE CAPS CLOSE TO SB PCE_VDDA PINS

3

8765

2 5

4321

1 7 8

A

B

6


Project:

D

PLACE CAPS CLOSE TO SB PCE_VDD/VTT PINS

Date Changed:


D


C

A

B

C

freescale Tiffany Tran-Chandler 461.03

HPCN: Argo NavisSouth Bridge PEX Interface


2:13:44 pm

C3640.1uF

VCC_3.3

1.0uFC381

R307

VCC_1.8

C372 0.1uF

3

3

14C2

10V

1000uF

C357+

62

OSCON

+

54B1

0

1

1

2

2

3

2

3

10V4.7uFC361

C374 0.1uF

0

13C8

C379 0.1uF

0.1uFC375

C384

C3690.1uF

C3601.0uF

nHTTSTOPAG30

AH30nIGNNE

nINIT AK27

AG27nSLEEP

nSMIAJ29

nSTPCLKAG26

AG25nTHRM

nVRHIAG24

2.2uF

M19VDD18M_CORE9

VDD33R_IO0F25

F26VDD33R_IO1

VDD_CPUY20

VRMPWGAJ26

AK28nA20M

AJ28nCPUHI

nCPURSTAH26

nDSLEEPAH27

nFERRAH29

AF29nHTTRESET

R12VDD18M_CORE2

VDD18M_CORE20 Y17

Y18VDD18M_CORE21

Y19VDD18M_CORE22

VDD18M_CORE3 T12

VDD18M_CORE4 U12

V12VDD18M_CORE5

M12VDD18M_CORE6

VDD18M_CORE7 M13

VDD18M_CORE8 M18

P12VDD18M_CORE1

M20VDD18M_CORE10

VDD18M_CORE11 W12

VDD18M_CORE12 W13

W14VDD18M_CORE13

W15VDD18M_CORE14

VDD18M_CORE15 W16

VDD18M_CORE16 W17

W18VDD18M_CORE17

W19VDD18M_CORE18

VDD18M_CORE19 W20

R29SB_RDP

AA26SB_TAN

SB_TAPAA25

W26SB_TBN

SB_TBPW25

SB_TCNU26

U25SB_TCP

R26SB_TDN

R25SB_TDP

AH25THRMTRIP

VDD18M_CORE0 N12

PC

E_V

TT

7

REFV29

F29REFCLK_N

REFCLK_PF28

AA28SB_RAN

SB_RAPAA29

W28SB_RBN

W29SB_RBP

U28SB_RCN

SB_RCPU29

R28SB_RDN

PC

E_V

DD

A7

AD

26

PC

E_V

DD

A8

AD

27

AD

28P

CE

_VD

DA

9

AC

25P

CE

_VT

T0

AC

26P

CE

_VT

T1

AC

27P

CE

_VT

T2

AC

28P

CE

_VT

T3

AC

29P

CE

_VT

T4

AC

30P

CE

_VT

T5

T25

PC

E_V

TT

6Y

25

PC

E_V

DD

A12

AE

25

PC

E_V

DD

A13

AE

26

AE

27P

CE

_VD

DA

14

PC

E_V

DD

A15

AE

28

PC

E_V

DD

A16

AE

29

PC

E_V

DD

A17

AE

30

R20

PC

E_V

DD

A2

PC

E_V

DD

A3

T20

PC

E_V

DD

A4

U20

PC

E_V

DD

A5

V20

AD

25P

CE

_VD

DA

6

PC

E_G

ND

9

N19PCE_VDD0

P19PCE_VDD1

PCE_VDD2R19

PCE_VDD3T19

U19PCE_VDD4

V19PCE_VDD5

PC

E_V

DD

A0

N20

P20

PC

E_V

DD

A1

AD

29P

CE

_VD

DA

10

PC

E_V

DD

A11

AE

24

PCE_GND34P18

R18PCE_GND35

T18PCE_GND36

U18PCE_GND37

V18PCE_GND38

AA

27P

CE

_GN

D4

AA

30P

CE

_GN

D5

AB

25P

CE

_GN

D6

AB

26P

CE

_GN

D7

AB

27P

CE

_GN

D8

AB

28

PC

E_G

ND

24U

27P

CE

_GN

D25

U30

PC

E_G

ND

26

PC

E_G

ND

27V

25

V26

PC

E_G

ND

28

V27PCE_GND29

Y29

PC

E_G

ND

3

V28PCE_GND30

W27PCE_GND31

W30PCE_GND32

PCE_GND33N18

R30

PC

E_G

ND

15R

27P

CE

_GN

D16

PC

E_G

ND

17P

29

P28

PC

E_G

ND

18P

27P

CE

_GN

D19

Y28

PC

E_G

ND

2

P26

PC

E_G

ND

20P

25P

CE

_GN

D21

G30

PC

E_G

ND

22F

27P

CE

_GN

D23

G27

NC7H28

H29NC8

NC9J25

AG29NMI

Y26

PC

E_G

ND

0Y

27P

CE

_GN

D1

AB

29P

CE

_GN

D10

T29

PC

E_G

ND

11T

28P

CE

_GN

D12

T27

PC

E_G

ND

13T

26P

CE

_GN

D14

NC3G29

M29NC30

NC31N25

N26NC32

NC33N27

N28NC34

NC35N29

N30NC36

NC4H25

H26NC5

NC6H27

G28

L25NC20

NC21L26

L27NC22

NC23L28

L29NC24

NC25L30

M25NC26

NC27M26

M27NC28

NC29M28

NC10J26

NC11J27

J28NC12

NC13J29

J30NC14

NC15K25

K26NC16

NC17K27

K28NC18

NC19K29

NC2

m1575.1of4.sb.bga628

AJ27CPUPWG

AE23DSPVRHI

GND0AJ30

AK30GND1

GND2AK29

AH28GND3

HTTPWROK AF28

INTRAG28

G25NC0

G26NC1

2

44B1,45B8

1

3

VCC_1.8

VCC_1.8

VCC_1.8

U37

0.1uFC378

14D2,19B1,54B1

1

C358

1

44A8,45B1

0.1uFC3760

3

2

1.0uF

0

10V4.7uFC355

OSCON

+

0.1uFC373

C3831.0uF

R306

10V

C354

1000uF+

C3680.1uF

0

C3561.0uF

VCC_1.8

0.1uFC370

C377 0.1uF

13C8

+

44A8,45B1

VCC_HOT_3.3

9

044B1,45B8

R308

1K

C3801.0uF

OSCON

C3824.7uF10V 1.0uF

C385

2.2K

R305

C3670.1uF

OSCON

C3594.7uF10V

+4.7uF10V

+

1

0.1uFC365

15C8,19B1,32A1

14D2

0.1uFC371

OSCON

C363

EHCI_INT*

AUDIO_INT*IRQ2*

IRQ*(0:11)

IDE_IRQ14

IDE_IRQ15

0.1uFC366

1.0uFC362

NC

NC

NC

NC

SB_CPURST*

IRQ9*

NC

NC

NC

NC

NC

NC

NC

IRQ0* SATA_INT*

OHCI_INT*

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

THERM*

SD1_TX_P(7:0)SD1_TX_N(7:0)

SD1_RX_P(7:0)SD1_RX_N(7:0)

SMI*

SB_INIT*

NC

NC

REFCLK_M1575pREFCLK_M1575n

NC

��

��

��

-+

RTC

PCI

AC97

LPC

MISC

7

C

A

B

D

C


semiconductor

TM

654321

1 2 3

RTC/NVRAM ENABLE1-2: Normal2-3: Reset RTC/NVRAM

4 5


HPCN: Argo NavisM1573_PCI/LPC/RTC/MISC


2:13:52 pm

6 7 8

A

B

D

Date Changed:



Project:freescale 7700 W. Parmer Ln

Austin, Texas 78729

8

TP56

24

13A8

sod_123

MBR0530CR7

2 1

1uFC269+C268

0

54A1

CR6MBR0530

sod_123

2 1

32.768kHz

Y1

sm_xtal_4p

14

53D8

21

0.1uF

0

27

29

22

TP44

19

3

0

1

R247 10K

2

16B1,51C1

16A1,51B1

16B1,51D1

54B1,55B1

2

1

16A1,51B1

16A1,51B1

30

28

VCC_HOT_3.3

VCC_HOT_3.3

conn.batteryJ15

1

C2620.1uF

VCC_1.8

C264

4.7uF

TP58

TP46

31

1M

R257

No_Stuff

16B1,51C1

VCC_3.3

16B1,51B1

17C8,50B1

TP43

0

VCC_HOT_1.8

14

50B1

4

16A1,51B1

VCC_1.8

R254 0

2

4

12

25

3

R243 1K

1

16B1,51B1

54B1,55B1

54B1,55B1

33R249

3

18

2

R245 0

15B11

R246 22

33

16

3

0

R255

0

1

23

CIC21P300NE

F13

R252

16A1,51B1

8

20

16B1,51C1

2

50B1

17D8

17D8

23

12pF

C265

5

15B1,51B1,54A1,55B1

2

C2671.0uF

J14

header.1x3

1

R253

17

TP45

54B1,55B1

TP49

13

26

33

0

R248 33

R256

0

TP57

12pF

C266

R242 1K

17D8,50B1

R259

1K

33

2

1

15

VCC_3.3

16A1,51B1

33R251

R250

nVOLUME_MUTEY5

nVOLUME_UPW4

10

11

54B1

54B1,55B1

0.1uFC263

nPIRQCC1

E3nPIRQD

D2nPIRQE

E2nPIRQF

E5nPIRQG

E6nPIRQH

V2nRTCRST

L3nSERR

K2nSTOP

J5nTRDY

nVOLUME_DOWNW5

nPCIGNT6A3

nPCIREQ0

nPCIREQ1B2

C3nPCIREQ2

C4nPCIREQ3

C6nPCIREQ4

B4nPCIREQ5

B6nPCIREQ6

nPCISTPAC5

D5nPIRQA

D6nPIRQB

K5

AF3nKBCRC

nLDRQ0AD3

AD2nLDRQ1

nLFRAMEAA2

nPCIGNT0A5

nPCIGNT1E1

C2nPCIGNT2

D4nPCIGNT3

C5nPCIGNT4

B3nPCIGNT5

B5

nAGPSTOPAD6

N3nCBE0

L1nCBE1

H5nCBE2

G5nCBE3

nCLKRUND3

AD4nCPUSTP

nDEVESELK3

K4nFRAME

AD5nHTTREQ_nAGPBUSY

nIRDY

VD

D33

M_I

O6

VD

D33

M_I

O7

AA

6

AC

6V

DD

33M

_IO

8

VD

D33

M_I

O9

P11

V6VDD33R_RTC

V3VDDBAT

VDDSWV5

VSSCOREPLL D7

X32KIU1

X32KIIU2

V4X32K_OSC_MODE

F7

VD

D33

M_I

O1

G6

R11

VD

D33

M_I

O10

VD

D33

M_I

O11

T11

VD

D33

M_I

O12

U11

V11

VD

D33

M_I

O13

VD

D33

M_I

O14

W11

J6V

DD

33M

_IO

2

VD

D33

M_I

O3

L6

N6

VD

D33

M_I

O4

VD

D33

M_I

O5

T6

W6

SERIRQAC2

AA5SPKR

VDD18COREPLL C7

VD

D18

R_C

OR

E0

AE

1

VD

D18

R_C

OR

E1

AE

2

AE

3V

DD

18R

_CO

RE

2

VD

D18

R_C

OR

E3

AE

4

VD

D18

R_C

OR

E4

AE

5

VD

D18

R_C

OR

E5

AE

6

VD

D18

R_C

OR

E6

AE

7

VD

D33

M_I

O0

T3PCICLK5

PCICLK6U6

T4PCICLK7

PCICLK8R3

T2PCICLK9

PCICLKFBIE8

PCICLKFBOF8

RUNGPIO0Y4

AF2RUNGPIO1

RUNGPIO2AB5

AB6RUNGPIO3

T5NC37

U3NC38

AF5NC39

PARL2

E7PCICLK

PCICLK0R1

U5PCICLK1

PCICLK2R6

R5PCICLK3

PCICLK4R2

GN

D14

D8

GN

D4

AC

4

GN

D5

AA

4

GN

D6

U4

GN

D7

R4

GN

D8

M4

GN

D9

H4

AA1LAD0

AB3LAD1

AB2LAD2

LAD3AC3

AD7N1

N2AD8

AD9M3

AVDD18COREPLL B7

AVSSCOREPLL A7

AB4CLK14M

CLK48M_24MAC1

GN

D10

B1 A2

GN

D11

GN

D12

A1

GN

D13

E4

F5

G1AD26

AD27F4

AD28G2

AD29G3

AD3P5

F3AD30

F2AD31

AD4N4

AD5P4

N5AD6

H6AD16

AD17J4

J1AD18

AD19J2

P6AD2

AD20H2

AD21J3

H3AD22

AD23G4

F6AD24

AD25W1

ACZ_SDOUTW2

ACZ_SYNCW3

P3AD0

AD1P2

M2AD10

AD11M6

AD12M5

L4AD13

L5AD14

AD15K6

9

U37m1575.2of4.sb.bga628

A20GATEAA3

Y2ACB_BITCLK

Y3ACB_SDOUT

Y6ACB_SYNC

ACZ_BITCLK

6

7

R258

10K

IDE_80PIN

PCI_CLK(0:4)

NC

NC

NC

NC

NC

NC

NC

NC

ACZ_SYNCACZ_SDOUT

ACB_SYNCACB_SDOUT

NC

NC

NC

NC

NC

NC

LPC_LAD2LPC_LAD1LPC_LAD0

M1575_BCLK

SPKR

LPC_SERIRQ

NC

PCICLK_SB

PCI_PAR

NC

NC

NC

LPC_LAD3

LPC_FRAMEJ*

LPC_LDRQ0*

PCI_IRDY*PCI_FRAME*

PCI_DEVSEL*

NC

NC

PCI_AD(31:0)

ACZ_BITCLK

PCI_CBE*(3:0)

PCI_GNT*(0:2)

PCI_REQ*(0:2)

PCI_INT*(0:3)

VBAT

PCI_TRDY*

PCI_STOP*

PCI_SERR*

LAN

USB

RESUME

AC97 Cont.

C


C

A

B

65


TO VDD33RUSB PINS TO VDD33R_IO PINS

8

NOTE: PLACE CAPS CLOSE

32

2 8


7

5 6

4

Tiffany Tran-Chandler 481.03

HPCN: Argo NavisM157X: USB, AC97, Power Management


2:14:00 pmTM

3 4

A

B

D

7

TO VDD18R_CORE PINS

Page:Title:


1

1

semiconductor

Date Changed:


Revision:

D

C4100.1uF

VCC_HOT_1.8

0.1uF

C419

C418

0.1uF

F20

2.2uF

C416

+

TP116

14C8

TP124

51B1,53C1,54B1,55B1

TP123

nUSBOV5C26

D26nUSBOV6

nUSBOV7E25

10K

R351

nPME

nPWRBTNA9

A11nRSMRST

B8nSLPBTN

nSMBALERTD12

C30nSUSPEND

D27nUSBOV0

nUSBOV1E26

B26nUSBOV2

nUSBOV3E27

A27nUSBOV4

M14VDD33R_IO8

VDD33R_IO9M15

F9nACB_RST

F11nACZ_RST

nLOWBATC28

E12nOFFCLKS1

nOFFPWRS3C8

B9nOFFPWRS4_S5

nPCIEX_WAKEUPB11

C10nPCIRST

B10

F20

E21

VD

D33

RU

SB

5

VD

D33

RU

SB

6F

21

E23

VD

D33

RU

SB

7

VD

D33

RU

SB

8M

17

VD

D33

R_I

O2

F14

VD

D33

R_I

O3

F13

F10VDD33R_IO4

VDD33R_IO5F12

L14VDD33R_IO6

VDD33R_IO7L15

C17

VDD18R_CORE10L20

VDD18R_CORE11N11

M11VDD18R_CORE12

VDD18R_CORE7L11

L12VDD18R_CORE8

VDD18R_CORE9L13

L17

VD

D33

RU

SB

0L

18V

DD

33R

US

B1

VD

D33

RU

SB

2L

19

VD

D33

RU

SB

3E

19

VD

D33

RU

SB

4

USB_D3_PA23

D20USB_D4_N

USB_D4_PC20

USB_D5_ND18

C18USB_D5_P

B21USB_D6_N

USB_D6_PA21

USB_D7_NB19

A19USB_D7_P

USB_RX_TXEMB17

USB_TX_CS

E14TXD2

TXD3E13

TXEND14

USBCLKF24

D24USB_D0_N

USB_D0_PC24

USB_D1_ND22

C22USB_D1_P

B25USB_D2_N

USB_D2_PA25

USB_D3_NB23

RXD1

RXD2E15

C15RXD3

F17RXDV

RXERE17

SMBCLKB12

SMBDATAC12

SUSLEDA28

F15TXCLK

C14TXD0

TXD1B14

E29LAN_ENABLE

LIDD28

MDCA15

B15MDIO

D29OHCI_ENABLE

COLA17

PWGC9

RIC11

B16RXCLK

RXD0D16

E16

U15

GN

D59

U16

GN

D60

U17 A29

GN

D64

B30

GN

D65

A30

GN

D66

V17

GN

D67

GN

D69

L16

V16

GN

D70

GND79D15

F16GND80

GN

D47

R15

GN

D48

R16

GN

D49

R17

GN

D51

T13

GN

D52

T14

GN

D53

T15

GN

D54

T16

GN

D55

T17

GN

D56

U13

GN

D57

U14

GN

D58

N14

N15

GN

D37

N16

GN

D38

N17

GN

D39

GN

D40

P13

GN

D41

P14

GN

D42

P15

GN

D43

P16

GN

D44

P17

GN

D45

R13

GN

D46

R14

D21

B20GND26

GND27E20

C19GND28

GND29D19

B18GND30

GND31E18

GND32D17

D11

GN

D33

D9

GN

D34

GN

D35

N13

GN

D36

GND15C27

C25GND16

GND17D25

B24GND18

GND19E24

C23GND20

GND21D23

B22GND22

GND23E22

C21GND24

GND25

F18

AVSSUSBPLLF23

AZLA_ENABLEC29

E30CLK32KO

CRSC16

DFTSEB28

B29DFTTM

A13EECK

EECSD13

EEDIB13

EEDOC13

U37

ULIM1575-GN


E28AC97_ENABLE

ACB_SDATAINE9

ACPWRB27

ACZ_SDATAIN0E11

D10ACZ_SDATAIN1

ACZ_SDATAIN2E10

F22AVDD18RUSBPLL

F19AVDD33RUSBBGR

AVSSUSBBGR

52B1

TP115

TP114

13D1,19C8,23D1,24D1,27D1,#6

VCC_3.3

0.1uF

C414

52A1

52A1

52C1

R344 15K

52C1

0.1uFC405

TP125

R345

10K

R337 15K

15KR338

13C1,19C8,23D1,24D1,27D1,#6

TP128

TP130

0

TP120

14D2

5D8

50B1

4 V3.3V

10K

R353

52C1

R333

1K

R352

14B8

U2448.000MHz

GND2 1

OE

OUT 3

TP122

TP117

C415

0.1uF

VCC_HOT_3.3

C413

0.1uF

C4070.1uF

R348 1K

R339

R350

10K

1%1%

R336

14.3K

VCC_HOT_3.3

15K

R341 15K

TP118

14.3K

R346

15KR342

C4090.1uF

VCC_HOT_3.3

4.7uF

C406

50B1

14D2

C412

2.2uF

+

VCC_HOT_3.3

C417

TP121

TP127

52C1

R349 33

VCC_HOT_3.3

17D8,56B1

0.1uF

1K

R347

TP113

52C1

TP119

52B1

52D1

0

R335

R334

0

+

0.1uFC408

52C1

15KR343

TP126

52D1

150uF

C411

VCC_HOT_1.8

TP129

R340 15K

17D8

PWRSWX*

SUSLED

ACZ_RST*

NC

NC

NC

NC

NC

NC

NC

NC

ACZ_SDIN0

SB_PCIRST*

SB_OFFPWR_S4_S5*SB_OFFPWR_S3*

USB_P3PUSB_P3N

USB_P2PUSB_P2N

USB_P1P

USB_P1N

USB_P0PUSB_P0N

USB_CLK

I2C2_SDAI2C2_SCL

SB_PWG

ACPWR

NC

NC

USBOV3*USBOV2*USBOV1*USBOV0*

SB_RSMRST*

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Primary

IDE

SATA0

IDE

SATA PLL

SATA1

Secondary

freescale432


semiconductor

TM

SATA PORT #0

1

1 2 3 4 6 7

HPCN: Argo NavisM157X: SATA, IDE


2:14:07 pmTitle:

8

A

B

D

Date Changed:


Revision:

A

Page:Project:

5

7

Place close to VDD33M_IO pins.

Place close to SATA_18M pins.

C

B


8

SATA PORT #1

SATA PORT #2

SATA PORT #3

65

D

C

Gary Milliorn1.03

49

0.01uFC431

0

R354

C440 0.01uF

C432 0.01uF

8

F22

C437 0.01uF

0.01uFC435

10

C430

R358

12.1K 1%

R356

1M

VCC_3.3

C429 0.01uF

0.01uF

R357

VCC_3.3

VCC_1.8

VCC_1.8

F21

53D1

11

4.7uF

C443

1%12.1K

nSIDECS3AF18

nSIDEDAKAG15

nSIDEIORAF14

AF13nSIDEIOW

13

R701 1K

No_Stuff

AE

18

AE

20V

DD

33M

_IO

19A

E21

VD

D33

M_I

O20

AJ3X25M1

X25M2AK3

AF23nPIDECS1

AG23nPIDECS3

AG20nPIDEDAK

AE19nPIDEIOR

nPIDEIOWAF19

nSIDECS1AF17

SIDED6AK13

AH13SIDED7

SIDED8AJ13

AH14SIDED9

AE14SIDEDRQ

AF15SIDEIRQ

AG14SIDERDY

VD

D33

M_I

O15

AE

13

AE

15V

DD

33M

_IO

16A

E17

VD

D33

M_I

O17

VD

D33

M_I

O18

AK17SIDED1

SIDED10AH15

AK15SIDED11

SIDED12AJ16

AJ17SIDED13

SIDED14AH18

AH19SIDED15

SIDED2AH17

AH16SIDED3

SIDED4AJ15

AJ14SIDED5

SATA_GPI3AJ12

AG3SATA_GPO0

SATA_GPO1AH3

SATA_GPO2AG2

SATA_GPO3AG1

SATA_LEDAJ2

AF16SIDEA0

SIDEA1AE16

SIDEA2AG17

SIDED0AJ18

SA

TA

_GN

D21

V15

SA

TA

_GN

D3

AJ8

AJ1

0S

AT

A_G

ND

4

SA

TA

_GN

D5

AH

5

AH

7S

AT

A_G

ND

6

SA

TA

_GN

D7

AH

9

AH

11S

AT

A_G

ND

8A

G5

SA

TA

_GN

D9

AH2SATA_GPI0

AH1SATA_GPI1

AH12SATA_GPI2

AG

9

AG

11S

AT

A_G

ND

12

SA

TA

_GN

D13

AG

12

AF

4S

AT

A_G

ND

14

SA

TA

_GN

D15

AF

6

AF

8S

AT

A_G

ND

16

SA

TA

_GN

D17

AF

10

AE

12S

AT

A_G

ND

18

SA

TA

_GN

D19

V13

AJ6

SA

TA

_GN

D2

V14

SA

TA

_GN

D20

SA

TA

_18M

3

SA

TA

_18M

4Y

15

AF

24S

AT

A_1

8M5

SA

TA

_18M

6A

F25

AF

26S

AT

A_1

8M7

SA

TA

_18M

8A

F27

SATA_AVDDPLL0AE8

SATA_AVDDPLL1AE10

SA

TA

_GN

D0

Y16

SA

TA

_GN

D1

AJ4

AG

7S

AT

A_G

ND

10

SA

TA

_GN

D11

SATA2_RX_PAG8

AG10SATA2_TX_N

SATA2_TX_PAH10

SATA3_RX_NAK9

AJ9SATA3_RX_P

SATA3_TX_NAJ11

SATA3_TX_PAK11

SA

TA

_18M

0Y

11

Y12

SA

TA

_18M

1

SA

TA

_18M

2Y

13

Y14

SATA0_REXT

SATA0_RX_NAH4

AG4SATA0_RX_P

SATA0_TX_NAG6

AH6SATA0_TX_P

SATA1_REXTAF11

AK5SATA1_RX_N

SATA1_RX_PAJ5

AJ7SATA1_TX_N

AK7SATA1_TX_P

AH8SATA2_RX_N

PIDED2

PIDED3AJ22

AK21PIDED4

PIDED5AH21

AH20PIDED6

PIDED7AJ19

AK19PIDED8

PIDED9AJ20

AG18PIDEDRQ

PIDEIRQAG21

PIDERDYAF20

AF9

AF21PIDEA1

AE22PIDEA2

AJ25PIDED0

PIDED1AH24

AJ21PIDED10

PIDED11AH22

AH23PIDED12

AK23PIDED13

AJ24PIDED14

PIDED15AK25

AJ23

GN

D73

GN

D74

AG

22

M16

GN

D75

GN

D76

AJ1

AK

1G

ND

77

GN

D78

AK

2

AE9NC37

NC38AF12

AF7NC39

NC40AE11

PIDEA0AF22

12pF

C442

U37


AG

13G

ND

71

GN

D72

AG

16

AG

19

4

GND37

RX_N5

6RX_P

3TX_N

TX_P2

R359 4.7K

4GND2

7GND3

5RX_N

RX_P6

3TX_N

2TX_P

conn.sata.7pin.vertJ30

1GND1

GND2

0.01uFC427


GND11

2

14

C436 0.01uF

C428 0.01uF

C433 0.01uF

0

1

C451

0.1uF

53D10.01uFC434

C420

+

0.1uF

C452

RX_P

3TX_N

TX_P2

12pF

C441

10V

1000uF

C424


GND11

GND24

GND37

RX_N5

6

15

C423

0.1uF

0.1uF

RX_N5

RX_P6

TX_N3

2TX_P

0.01uFC439

56A8

7

53D1

J29conn.sata.7pin.vert

GND11

4GND2

7GND3

C447+

9

C421

0.1uF

C449

0.1uF150uF

Y2

25.0

00M

Hz

0.1uF

C448

4

5

12

6

4.7KR360

C446

0.1uF

53D1

53D1

53D1

3

4.7uF

VCC_3.3

53C1

53D1

53D8

VCC_3.3

C425 0.01uF

53D8

53D1

C444

0.1uF

C445

0.01uFC426

0.01uFC438

R355

0

0.1uF

C422

NC

NC

NC

NC

NC

53D1

0.1uF

C450

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

SATA1_RX_N_B

SATA1_RX_P_B

SATA2_RX_N_B

SATA2_RX_P_B

SATA3_RX_P_B

SATA3_RX_N_B

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

PIDEA2PIDEA1PIDEA0

NC

NC

PIDERDY

PIDEIRQ

PIDEDRQ

PIDEIOW*PIDEIOR*

PIDEDAK*

PIDECS3*PIDECS1*

SATALED

NC

NC

SATA3_TX_N_B

SATA3_TX_P_B

SATA2_TX_N_B

SATA2_TX_P_B

SATA1_TX_N_B

SATA1_TX_P_B

SATA0_RX_P_B

SATA0_TX_N_B

SATA0_TX_P_B

SATA0_RX_N_B

PIDE(15:0)

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CODEC

AUDIO

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C

Time Changed:

C

D

Page:Title:Engineer:Revision:


Project:freescale

1

A

B

TM

87

AVDD_5 should be a copper fillunder the CODEC.

1

semiconductor

3 654

4 5

2

3

A

D

B


HPCN: Argo NavisM1575 AC97 Audio Codec


2:14:16 pm

2


6 7 8

Date Changed:

4.7uFC627 +

F23

TP141

A

10R440

R437

10K

10K

R438

1.0uFC625

TP144

0

A

A

C63022uF

+

0.1uF

53A1

1.0uFC617

R445

TP145

TP147

C606

R442 1K

53B1

VCC_3.3

13B8

47B8

VCC_5

1

2

3

C622

1.0uF

TP143

F24

J32header.1x3

1.0uFC621

C628 1.0uF

header.1x4J33

1

2

3

4

C618 1.0uF

0.1uF

C616

17C8,47B8

TP148

C610 1.0uF

C612

0.1uF

C611 1.0uF

1.0uFC609

TP146

47C8

C629 1.0uF

1.0uFC624

R439 10

C60822pF

+

53B1

53B1

53A1

0.1uF

C605

1.0uFC613

C620 1.0uF

100uFC626

VIDEO_L

VIDEO_R17

31VRAD

VRDA32

VREF27

28VREF_OUT

2XTAL_IN

3XTAL_OUT

XTLSEL46

nRESET11

A

12PC_BEEP

PHONE13

8SDIN

5SDOUT

SPDIFO48

39SURR_OUT_L

41SURR_OUT_R

SYNC10

VDD11

9VDD2

16

GPIO0

LFE_OUT44

LINE_L23

LINE_OUT_L35

LINE_OUT_R36

24LINE_R

MIC121

22MIC2

MONO_OUT37

33NC1

NC240

25

38AVDD2

6BITCLK

19C

D_G

ND

CD_L18

20CD_R

43CENTER_OUT

47EAPD_SPDIFI

FrontMIC34

4G

ND

1

GN

D2

7

45

U44

ALC650.lqfp48

29AFILT1

AFILT230

AG

ND

126 42

AG

ND

2

14AUX_L

AUX_R15

AVDD1

TP142

R441 0C607 .01uF

1.0uFC614

1.0uFC615

R444 1K

C619 1.0uF

C623 100uF+

1KR443

SPKR

NC

NC

NC

ACZ_BITCLK

A

48D1

VCC_3.3

17D8,47B8

48D1

53A1

53B1VREF_FLT

ACZ_RST*

AUD_CLK

ACZ_SYNCACZ_SDOUTACZ_SDIN0

MIC_LMIC_RLINE_LLINE_R

LOUT_LLOUT_R

AVDD_5

-12V A12

A13

B12

B13

A18

GN

D

A24

A30

A35

A37

A42

A48

A56

B3

B15

B17

B22

B28

B34

B38

B46

B57

B1

+5V

A53

B25

B31

B36

B41

B43

B54

NC B10

B14

A2

B6

B61

B62

A5

A8

A61

A62

B5

A9

A11

A21

A27

A33

A39

A45

+3.3

V

+12V

VIO

: 3.

3V o

r 5V

-12V A12

A13

B12

B13

A18

GN

D

A24

A30

A35

A37

A42

A48

A56

B3

B15

B17

B22

B28

B34

B38

B46

B57

B1

+5V

A53

B25

B31

B36

B41

B43

B54

NC B10

B14

A2

B6

B61

B62

A5

A8

A61

A62

B5

A9

A11

A21

A27

A33

A39

A45

+3.3

V

+12V

VIO

: 3.

3V o

r 5V



C

A

B

D

C


semiconductor

TM

87654321

1 2 3 4 5


HPCN: Argo NavisPCI Bus


2:14:24 pm

6 7 8

A

B

D

Date Changed:


16A1,47C1

10K

R26

2

2022

10K

R27

0

10K

R27

3

A16

A59

B19B59

C283

0.1uF

SE

RR

A40

SM

BC

LK

A41

SM

BD

AT

A38

ST

OP

B2

TC

K

A4

TD

I

B4

TD

O

A3

TM

SA

36T

RD

Y

A1

TR

ST

A10

B39

LO

CK

B49

M66

EN

A43

PA

R

B40

PE

RR

A19

PM

E

B9

PR

SN

T1

B11

PR

SN

T2

B18

RE

Q

A60

RE

Q64

A15

RS

T

B42

C_B

E2

B26

C_B

E3

B37

DE

VS

EL

A34

FR

AM

E

A17

GN

T

A26

IDS

EL

A6

INT

A

B7

INT

B

A7

INT

C

B8

INT

D

B35

IRD

Y

AD

31

A55

AD

4

B55

AD

5

A54

AD

6

B53

AD

7

B52

AD

8

A49

AD

9

AU

X_3

VA

14

B16

CL

K

A52

C_B

E0

B44

C_B

E1

B33

A28

AD

22

B27

AD

23

A25

AD

24

B24

AD

25

A23

AD

26

B23

AD

27

A22

AD

28

B21

AD

29

B56

AD

3

A20

AD

30

B20

AD

12

A46

AD

13

B45

AD

14

A44

AD

15

A32

AD

16

B32

AD

17

A31

AD

18

B30

AD

19

A57

AD

2

A29

AD

20

B29

AD

21

16A1

VCC_HOT_3.3

3V:

1451

54-1

5V:

1451

54-1

J16pciconn_with_3.3V_aux_32bit

B60

AC

K64

A58

AD

0

B58

AD

1

B48

AD

10

A47

AD

11

B47

C271

0.1uF

18

27 7

3 00.1uF

C276

25 16

7 6 5 4 3 2

16A1,47C1

3

45

13D1,19C8,23D1,24D1,27D1,#6

13C1,19C8,23D1,24D1,27D1,#6

10K

0

2

16B1,47D1

3

VCC_3.3

R27

110

K

0

R27

4

2

14 9

1

8

2

15B1,47A8,54A1,55B1

0.1uF

C272

3

C281

0.1uF

01

12

18 17

15C8

C270

47uF

+

16A1,47C1

29 23 22 21 20 19

1

23

0

3

2

48C7,53C1,54B1,55B1

31 8

19

2

21

14 13 12

VCC_HOT_3.3

10

0.1uF

C282

10

01

2425

16 15

33

17

26

11

10K

R26

0

VCC_5

16B1,47A1

0

R277

26

C273

0.1uF16B1,47C1

VCC_5

16A1,47C1

0

0.1uF

C27813

33

R278

10K

R26

6

47uF

C277

+

C279

0.1uF

R26

310

K

10K

R26

4

0

0.1uF

C274

1528 131 30 29

1

16B1,47C1

1

27 1617

0

1 3

30 28

R26

510

K

R279

11 9

16B1,47C1

24

10K

10K

R26

9

0

10K

R26

7

R26

8

R27

610

K

R27

210

K

1

R26

110

K

10K

R27

5

B2

TD

IA

4

TD

OB

4

TM

SA

3T

RD

YA

36

TR

ST

A1

A10

A16

A59

B19B59

A19

PM

E

PR

SN

T1

B9

PR

SN

T2

B11

RE

QB

18

RE

Q64

A60

RS

TA

15

SE

RR

B42

A40

SM

BC

LK

A41

SM

BD

AT

ST

OP

A38

TC

K

A17

IDS

EL

A26

INT

AA

6

INT

BB

7

INT

CA

7

INT

DB

8

IRD

YB

35

LO

CK

B39

M66

EN

B49

PA

RA

43

PE

RR

B40

B53

AD

8B

52A

D9

A49

AU

X_3

VA

14

CL

KB

16

C_B

E0

A52

C_B

E1

B44

C_B

E2

B33

C_B

E3

B26

DE

VS

EL

B37

FR

AM

EA

34

GN

T

AD

26A

23A

D27

B23

AD

28A

22A

D29

B21

AD

3B

56

AD

30A

20A

D31

B20

AD

4A

55A

D5

B55

AD

6A

54A

D7

A32

AD

17B

32A

D18

A31

AD

19B

30

AD

2A

57

AD

20A

29A

D21

B29

AD

22A

28A

D23

B27

AD

24A

25A

D25

B24

5V:

1451

54-1

3V:

1451

54-1

AC

K64

B60

AD

0A

58A

D1

B58

AD

10B

48A

D11

A47

AD

12B

47A

D13

A46

AD

14B

45A

D15

A44

AD

16

VCC_3.3

C275

0.1uF

VCC_5

pciconn_with_3.3V_aux_32bitJ17

0.1uF

C280

2 1

16A1,47C1

16B1,47B1

PCI_AD(31:0)

DATABLIZZARD_INTD*

16A1,47C1

018

3 2

PCI_IRDY*PCI_TRDY*PCI_STOP*

PCI_PERR*PCI_SERR*

PCI_CBE*(3:0)

PCI_PAR

PCI_REQ*(0:2)

PCI_INT*(0:3)

NC

I2C2_SDAI2C2_SCL

NC

NC

NC

NC

NC

NC

NC

NC

PCI_GNT*(0:2)

PCI_CLK(0:4) NC

NC NC

NC

NC

NC

NC

NC

PCI_DEVSEL*PCI_FRAME*

NC

SB_PCIRST*

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

765432

with heavy power traces.Place caps near IN_AB and IN_CD


semiconductor

2

TM

3

1

41 5 6 8

B

Date Changed:

7

A

D

Tiffany Tran-Chandler1.03

52HPCN: Argo Navis

USB PortsThursday, February 1, 2007

2:14:34 pmTime Changed:Engineer:



C

A

B

D

C

8

48A1

16V33uFC289+

10pF

C290

15K

R287R285

15K

DLW21SN900SQ2B

L61 2

34

R289

15K

1 2

34

DLW21SN900SQ2B

L51 2

34

9FLGD

4GND1

GND212

13IN_AB

5IN_CD

3OUTA

OUTB14

OUTC6

11OUTD

L4

DLW21SN900SQ2B48A1

VCC_5

mic2077-2bm.so16U16

ENA2

15ENB

7ENC

END10

1FLGA

16FLGB

FLGC8

15K

R286

48B1

48B1

48A1

R282

10K

15K

R288

VCC_3.3

10K

R280 R281

10K

SHIELD

TG4

TN2

3TP

1TV

48B1

48B1

48A1

48A1

48A1

48A1

BOTTOM

TOP

J19

usb_dual_raconn.usb.dual.stacked.ra

8BG

6BN

BP7

BV5

9

DLW21SN900SQ2B

1 2

34

FB

3

FB

1

15K

R284

L7

C287

0.1uF0.1uF

C285

1

10

2

3 4

5 6

7 8

9

C291

10pF

FB

6

J18header.2x5

+ C28833uF16V

+C28433uF16V

+

16V33uFC286

10K

R283

R291

15K

48A1

FB

5

FB

4

USB_P1P USBO1 DIFF_USB

P1P

CLASS=[ ]

CLASS=[ ]USBO0 DIFF_USB

P0P

FB

2

15K

R290

CLASS=[ ]

USBO3 DIFF_USB

P3N

CLASS=[ ]

FU

SB

_PO

WE

R3

FU

SB

_PO

WE

R4

USB2 DIFF_USBCLASS=[ ]USB_P2P USBO2 DIFF_USB

P2P

DIFF_USBCLASS=[ ]

CLASS=[ ]USB3 DIFF_USBCLASS=[ ]USB_P3P DIFF_USB

P3P

USBO3

CLASS=[ ]USB0 DIFF_USBUSB_P0P

CLASS=[ ]USB1 DIFF_USB

USB_P3N USB3 DIFF_USB

CLASS=[ ]USBO0 DIFF_USB P0N

FU

SB

_PO

WE

R2

FU

SB

_PO

WE

R1

USB_POWER1

USB_POWER2

USB_POWER3

USB_POWER4

USBO1 DIFF_USB P1NCLASS=[ ]

USBO2 DIFF_USB P2N

USBOV0*

USBOV1*

USBOV2*

USBOV3*

NC

CLASS=[ ]USB0 DIFF_USBUSB_P0N

CLASS=[ ]USB1 DIFF_USBUSB_P1N

CLASS=[ ]USB_P2N USB2 DIFF_USB

CLASS=[ ]

Line In

Middle

Lime

Line Out

Bottom

Pink

Mic In

Top

Triple Audio Jack

Light Blue

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

shro

ud

ed

A

B

D

C

semiconductor

TM

8


6 7321 54


HPCN: Argo NavisUSB and Audio AC97 Connectors


2:14:41 pm

6 71 2 3 4 5 8

A

B

Place caps close to connector.

D

Date Changed:




C

22K

R296

7

33

34

35

4

5

6789

1

2

21

22

23

24

25

3

31

32

49A8 49A8

49A8

4.7K

R294

U20audiojack.3port

47pF

9

10

11

49A8

49B8

50C1

49A8

49A8

49A8

47pF

C307C306

10K

R298

F15

2

50C1

50C1

56A8

50B8

F19

47C8

14

F16

49B8

3

A

F18

12

8

22K

R297 R299

22K

15

50B8

C3100.047uF

50C1

100K

R301

6

7 8

9

48C7,51B1,54B1,55B1

C305

47pF

F14

33 34

35 36

37 38

39

4

40

5

23 24

25 26

27 28

29

3

30

31 32

13 14

15 16

17 18

19

2

20

21 22

47pF

C308

J20header.vertical.shrouded.2x20

1

10

11 12

5

4

49A8 49A8

1

0

C309

47pF47pF

C304

49A8

50B8

6

F17

A

13

470

A

R295

22K

SB_PCIRST*

PATALED

PIDE(15:0)

PIDEA2PIDECS3*

IDE_80PIN

VREF_FLT

MIC_L

R300

PIDEDRQ

PIDECS1*

PIDEIOR*PIDEIOW*

PIDERDYPIDEDAK*PIDEIRQ

NC

NC

NC

LINE_L

NC

NC

LINE_R

LOUT_L

LOUT_R

NC

MIC_R

NC

NC

PIDEA0PIDEA1

POLYSW

BOTTOM

TOP

POWER/GND

SERIAL

PORT 2

PARALLEL

GAME PORT

KEYBOARD

MOUSE

SERIAL

PORT 1

FLOPPY

DRIVE

POWER/GND

CLOCKS

LPC

PORT

FAN

470ohm to 1K ohm are placed for input safety

3

1 2 3

54

6 7 8

Date Changed:

Time Changed:Revision:

4 5

541.03

HPCN: Argo NavisSIO


2:14:49 pmTitle:


A

B

D

C

Page:

A

B

D

C


semiconductor

TM

???

1 2

680 ohm resistors generate -69deg Celsius

Refer to RG for therm & voltage monitor, VID[3:0]

876

Engineer:

F4ptc_smd100

Tiffany Tran-Chandler

R196 10K

10KR195

VCC_5

VCC_3.3

VCC_3.3

47C8,55B1

R194 10K

VCC_SERDES

VCC_1.8

VCC_DDRA_IOR202 10K

5A8

VCC_3.3

T3 T4

T5 T6

R184 470

J11

B1 B2

B3 B4

B5 B6

CGND1

CGND

T1 T2

C169

22pFC170

conn.din6.dual.stacked.ra

10KR199

5B8

2200pF

R21

14.

7K

45A8

19A8

R198 10K

2A

Z=115ohms

C175

10pF

R186 470

VCC_5

F8

F10

2A

Z=115ohms

470R187

22pFC174

10K

R21

0

VCC_3.3

VCC_PLAT VCC_12_BULK

R204 10K

R191

4.7K

R21

2

25B1

VCC_3.3

10K

R17

8

10K

2A

Z=115ohms

15B1,47A8,51B1,55B1

47C8,55B1

47C8,55B1

47C8,55B1

10K

R20

8

10KR201

F9

J101

2

R20

510

K

4.7K

R21

4

43B8

25B1

10K

R18

0

header.1x2

R190 470

R18

110

K

TP23

22pFC171

14D2,19B1,46C8

47C8

13A8

19A8

56A1

R182 680 R20

910

K

10KR193

TP24

VCC_3.3

3

29B1

29B1

46C8

680R183

470R185

VCC_HOT_3.3

13C1,19C8,23D1,24D1,27D1,#6

10KR192

13D1,19C8,23D1,24D1,27D1,#6

14D2

R197

R20

710

K

47C8,55B1

48C7,51B1,53C1,55B1

10KR203

47C8

10K

10K

R20

6

R17

910

K

Z=115ohms

2A

F7

F6

2A

Z=115ohms

C1720.1uF

10KR200

14nTRK0

nWDATA10

11nWGATE

15nWRTPRT

Z=115ohms

2A

F5

27nLPCPD

3nMTR0

26nPCI_RESET

nRDATA16

90nRI1

nRI2_GP5092

87nRTS1

98nRTS2_GP55

67nSLCTIN

9nSTEP

nSTROBE83

97nDSR2_GP54

89nDTR1

100nDTR2_GP57

81nERROR

12nHDSEL

nINDEX13

66nINIT

17nIO_PME_GP42

50nIO_SMI_GP27

25nLDRQ

nLFRAME24

118

80nACK

82nALF

88nCTS1

99nCTS2_GP56

91nDCD1

94nDCD2_GP51

8nDIR

5nDS0

4nDSKCHG

86nDSR1

106VID0

107VID1

108VID2

109VID3

44VREF

7VSS1

31VSS2

60VSS3

VSS476

18VTR

Vccp_IN

RXD1

95RXD2_IRRX1_GP52

104SCLK

103SDA

30SER_IRQ

77SLCT

85TXD1

96TXD2_IRTX1_GP53

VCC153

65VCC2

93VCC3

MDAT

PCI_CLK29

68PD0

69PD1

70PD2

71PD3

72PD4

73PD5

74PD6

75PD7

78PE

84

39J2Y_GP17

57KCLK

KDAT56

20LAD0

21LAD1

22LAD2

23LAD3

48LED1_GP60

49LED2_GP61

59MCLK

58

HVSS5128

HVSS6

61IRRX2_GP34

62IRTX2_GP35

32J1B1_GP10

33J1B2_GP11

36J1X_GP14

37J1Y_GP15

J2B1_GP1234

35J2B2_GP13

38J2X_GP16

GP37_A20M

2GP41_DRVDEN1

28GP43_DDRC

102HVCC1

111HVCC2

121HVCC3

HVCC4122

101HVSS1

112HVSS2

125HVSS3

126HVSS4

127

54FAN2_GP32

52FAN_TACH1_GP31

51FAN_TACH2_GP30

41GP20_P17

42GP21_P16_nDS1

43GP22_P12_nMTR1

45GP24_SYSOPTIXO

46GP25_MIDIIN

47GP26_MIDIOUT

GP36_nKBDRST63

64

A0_nRESET_nTHERM_XNOROUT

40AVSS

79BUSY

6CLKI32

19CLOCKI

113D0n_XNORIN

D0p114

124D1n

123D1p

DRVDEN0_GP401

55FAN1_GP33

lpc47m192.qfp128

U43

1201.5V_IN

1.8V_IN119

11012V_IN_VID4

1172.5V_IN

1163.3V_IN

1155V_IN

105

C17322pF

R188 470

R21

34.

7K

470R189

PCI_CLK(0:4)

M2_DDR_IOPWR_S5

S1_PRSNT* S1_PRSNT*S2_PRSNT*S2_PRSNT*

FAN_TACHFAN_PWM

NC

2CM

_MA

X

SHORT_POWER

NC

NC

NC

SIO_TP8

SIO_TP14

SIO_TP9

TEMP_ANODE

TEMP_CATHODE

PME*SMI*

LPC_SERIRQ

THERM*

M1_DDR_IOPWR_S3M1_DDR_IOPWR_S5M2_DDR_IOPWR_S3

NC

NC

NC

NC

NC

NC

NC

SIO_BCLK

2CM_MAX

2CM_MAX

2CM_MAX

2CM_MAX

NC

NC

NC

NC

NC

LPC_LDRQ0*LPC_FRAMEJ*

NC

SB_PCIRST*

NC

NC

NC

NC

NC

NC

NCI2C2_SCLI2C2_SDA

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

LPC_LAD0LPC_LAD1LPC_LAD2LPC_LAD3

SIO_LED

NC

NC

NC

3V FLASH

2MB x 8

B

D

8

Time Changed:Title:freescale

Freescale SemiconductorPage:

7


8

Place caps close to SIO.

21303602

C

B

Austin, Texas 78729

C

A

65

D

321 4

2 3

semiconductor

1

Place these caps less than

Replace with socket:

1cm from VDD.

TM

5 6 74

A

1.0355

HPCN: Argo NavisLPC Boot Flash / ULI/AC97 Config


2:14:57 pmTiffany Tran-ChandlerEngineer:

Revision:

Date Changed:

33uFC295+

0.1uFC299 C301

0.1uF

4.7uF

+

10K

R293

47C8,54B1

0.1uFC293

C292

4

47C8,54B1

VCC_3.3

47C8,54B1

R292

10K

nTBL8

7 nWP_AAI

VCC_3.3

VCC_5

15B1,47A8,51B1,54A1

47C8,54B1

47C8,54B1

48C7,51B1,53C1,54B1

17B8,38C1

20NC4

21NC5

NC622

26NC7

NC827

28NC9

25VDD

16VSS

nINIT24

nLFRAME23

nRST2

9

LAD013

LAD114

LAD215

LAD317

LCLK31

1NC1

NC1029

32NC11

18NC2

19NC3

sst49lf016c.plcc32U4

6 GPI0_RYnBY

GPI1_nLD5

GPI24

GPI33

30 GPI4

12ID0

ID111

10ID2

ID3

0.1uFC298

C29433uF

+

0.1uFC300 C302

0.1uF

0.1uFC296

NC

NC

NC

NC

NC

NC

0.1uFC297

0.1uFC303

PCI_CLK(0:4)LPC_FRAMEJ*LPC_LAD0LPC_LAD1LPC_LAD2LPC_LAD3

SB_PCIRST*

CFG_FLASHWP*

NC

NC

NC

NC

NC

C

7654

TM

Chassis disk activity LED connector.

321

1 2 3 4 5 6 7 8

A

B

D

Date Changed:



Project:

C

Austin, Texas 78729

A

B

D

Gary Milliorn1.03

56HPCN: Argo Navis

LEDs, MiscThursday, February 1, 2007

2:15:05 pm7700 W. Parmer LnfreescaleFreescale Semiconductor

semiconductor

8

sod_123

MBR0530CR9

R362

330

1

header.1x2J31 1

2

10A1,14B2

CR8MBR0530

sod_123

1

17D8,48C7

3.3VGreen

D12 1

D16

GreenVSERDES

R370 D11

GreenHOT_1.8V

D8

GreenHOT_5V

1

VCC_HOT_5

6B1

VCC_HOT_1.8

330

Green1.2V

D17 1

330

R367

R380

14C2,29B8

FAIL

D5

Red

1

7B1,14B2

1

11C1,14C2

74lvc1g125.sc70

U282

1

4

330

R363

15B8

M1_VTTGreen

D13

D10 1

U29

74lvc1g125.sc70

2

1

4

330

VCC_HOT_2.5

R378

330

HOT_2.5VGreen

330

R376

330

D15 1

HOT_3.3V

D9

Green

1

R364

1

R374

330

1.8VGreen

4

74lvc1g125.sc70

U302

1

4 D14

GreenM2_VTT

330

R373

U31

74lvc1g125.sc70

2

1

D41

SATAGreen

D20 1

4

330

R365

14C2,25B8

PASSGreen

74lvc1g125.sc70

U342

1

4

VCC_3.3=VCC_HOT_3.3

74lvc1g125.sc70

U52

1

49D1

D21

GreenPATA

1

54A8D3

GreenSIO

1

330

R369

2

1

4

9B1,14B2

D7

GreenSUS

1

VCC_3.3

11A1,14C2

COREGreen

D19 1U41

74lvc1g125.sc70

330

53D1

R372

330

R366

330

No_Stuff

VCC_3.3

15B8

R371

330

R379

4

ASLEEPGreen

D6 1

VCC_3.3

R381

RC73L2Z331JTF

U36

74lvc1g125.sc70

2

1

4

U3

74lvc1g125.sc70

VCC_3.3=VCC_HOT_3.3

2

1

R375

74lvc1g125.sc70

U392

1

4 D18

GreenVPLAT

1

330

R368

14C2,19D8

330

R377

M1_DDR_IOPWRGD

PS_H33_PG330

PS_VCORE_PG

PATALED

SIO_LED

ASLEEP

SUSLED

SATALED

PS_1.2V_PG

PS_PLATFORM_PG

PASS_LED*

PS_SERDES_PG

M2_DDR_IOPWRGD

FAIL_LED*

PS_ULI_1.8V_PG

4 5 62

Revision:Title:

8

B

Date Changed:


INTER POWER PLANE CAPACITANCE

Place ~2cm from each cornerand one in the center.


C

A

B

D

C


semiconductor

TM

GLOBAL BULK CAPACITANCEPlace ~2cm from each cornerand one in the center.

GLOBAL HF CAPACITANCE

8

Place in a grid ~5cm everywhere.

7

CHASSIS MOUNTING HOLES

6

ATX/Micro-ATX Chassis: 7 holes.

5

GROUND TEST POINTS

4

Place in each corner and center


HPCN: Argo NavisGlobal Bypass Capacitors and Mounting


2:15:13 pm

321

1 3

Page:

7

A

D

0.1uF

C478 C480

0.1uF

6.3V

+

6.3V22uFC496

OSCON

+

6.3V22uFC486

OSCON

+

OSCON

C49222uF

0.1uF

C483 C487

0.1uF

MH5MH4MH3 MH7MH6

0.1uF

C502C454

0.1uF

16V33uFC491+C485

33uF16V

+

C455

0.1uF

G5tp.black

0.1uF

C489 C493

0.1uF

0.1uF

C488

VCC_5 VCC_3.3

VCC_3.3

0.1uF

C494C490

0.1uF

0.1uF

C475

0.1uF

C459

C468

0.1uF

0.1uF

C457

C458

0.1uF

tp.blackG2

MH2MH1

+

tp.blackG4G3

tp.black

0.1uF

C497

OSCON

C50022uF6.3V

VCC_5

C501

0.1uF

C467

0.1uF 0.1uF

C469

0.1uF

C465

0.1uF

C456 C463

0.1uF

0.1uF

C484

0.1uF

0.1uF

C479 C481

+C49533uF16V

+

C477

0.1uF0.1uF

C466

16V33uFC499

0.1uF

C462 C464

0.1uF

G1tp.black

0.1uF

C453

0.1uF

C482 C498

0.1uF

VCC_5

0.1uF

C461

C476

0.1uF

C460

0.1uF

VCC_3.3

SWITCHES VTT PLANE + POWER C LPCFlash Time Changed: Engineer: Revision: Page: LAYER 3 Batt. COP...

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Transcript of SWITCHES VTT PLANE + POWER C LPCFlash Time Changed: Engineer: Revision: Page: LAYER 3 Batt. COP...