pdf-2011-GC985201030
-
date post
05-Jan-2016 -
Category
Documents
-
view
23 -
download
3
description
Transcript of pdf-2011-GC985201030
-
Automatic Synthesis Flow of DC to DC
Step-Down Converter Circuits
-
( 1 )
/ ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( )
985201030
:
100 7 9
1. 15 3
http://blog.lib.ncu.edu.tw/plog/
2.
3.
4.
http://blog.lib.ncu.edu.tw/plog/ -
i
Buck Converter
Linear Low Dropout Voltage Regulator, LDO
Control Circuit
HSpice
Tool Command Language,
Tcl Linux
-
ii
Abstract
Recent trend of integrated circuit design requires miniaturization as well as
diversification. As such, the IC contains different kinds of circuits on a whole chip
including power converters. This work proposes an automatic synthesis flow for
DC-DC step-down converters. The converter architectures of a switcher DC-DC
step-down converter buck converter and a linear low dropout voltage regulator
LDO are both supported in the flow with complete control circuits. Moreover, the
area of compensation circuits is minimized.
Users can select topology of converter and input specifications of converters in
the proposed synthesis tool, like input voltage, output voltage, etc. Then the synthesis
tool will automatically generate proper design parameters and corresponding design
netlist. The netlist is then simulated with HSpice to verify the implementation results
with specifications. If the required specifications are not achieved, the tool will adjust
the input parameters and re-run the synthesis procedure actomatically. For buck
converters, the primary concern is the efficiency. For LDO circuits, the primary
concerns are the line regulation and load regulation. This proposed synthesis flow has
been integrated with the tool command languagetcl on Linux platform. As
demonstrated on the circuit examples, all the generated circuits can meet the required
specifications.
-
iii
-
iv
................................ .............................. i
Abstract ................................ ......................... ii
................................ ............................ iii
................................ ............................. iv
................................ .......................... vii
................................ ............................ x
................................ ..................... 1
1- 1 ........................................................................................................ 1
1- 2 .................................................................................... 5
1- 3 ........................................................................................................ 9
1- 4 ...................................................................................................... 11
................................ .................... 12
2- 1 .............................................................................................................. 12
2- 2 ...................................................................... 13
2- 2- 1 .......................................................................................... 15
2- 2- 2 .................................................. 16
2- 3 ...................................................................... 17
2- 3- 1 .......................................................................................... 19
................................ .... 21
3- 1 ...................................................................................................... 21
-
v
3- 2 .............................................................................................. 23
3- 3 .............................................................................................. 26
3- 4 .............................................................................................................. 28
3- 5 .............................................................................................. 33
3- 5- 1 .......................................................................... 34
3- 5- 2 .............................................................. 37
3- 5- 3 .......................................................... 39
3- 6 .......................................................................................... 43
3- 7 ...................................................................................................... 44
................................ .... 55
4- 1 ...................................................................................................... 55
4- 2 ...................................................................................................... 57
4- 3 ...................................................................................................... 58
4- 4 .................................................................................................. 60
4- 5 .................................................................................................. 61
4- 6 ...................................................................................................... 63
4- 7 .......................................................................................... 67
4- 8 ...................................................................................................... 68
................................ .......... 76
5- 1 .............................................................................................................. 76
5- 2 ...................................................................................... 77
5- 3 ...................................................................................... 81
-
vi
................................ .......... 86
6- 1 .............................................................................................................. 86
6- 2 ...................................................................................................... 87
................................ ..................... 88
-
vii
1-1 [1] ........................................................................................... 1
1-2 3D IC[2] .............................................................................. 2
1-3 2008 2012 [3] ..................................................... 3
1-4 ................................................................................ 4
1-5 [5] ........................................................................... 5
1-6 [6] ........................................................................... 6
1-7 [7] ................................................... 8
2-1 .......................................................................... 12
2-2 [6] ......................................................................... 13
2-3 .............................................................................. 13
2-4 .................................................................................. 14
2-5 .................................................................................. 14
2-6 .............................................................................. 15
2-7 ...................................... 17
2-8 .................................. 17
2-9 A NPN B PNP C NMOS D PMOS[16].......................... 18
2-10 ............................................................................ 20
3-1 .......................................................................... 21
3-2 ...................................................... 24
-
viii
3-3 .............................................................. 26
3-4 .................................................. 28
3-5 .......................................................................................................... 31
3-6 ...................................................... 33
3-7 A B ...................................... 34
3-8 .................................................................................. 38
3-9 ...................................................................................... 40
3-10 ................................................................................ 41
3-11 .................................................... 53
3-12 ........................................ 53
4-1 .......................................................................... 55
4-2 ...................................... 57
4-3 ...................................................................... 59
4-4 ...................................................................... 59
4-5 .................................................................. 60
4-6 .................................................................. 62
4-7 AC [28] ................................................. 63
4-8 .......................................... 65
4-9 .......................................... 66
4-10 ................................ 74
4-11 ........................................ 74
5-1 ...................................................................................................... 76
-
ix
5-2 .................................................................. 77
5-3 .......................................................... 78
5-4 .......................................................... 79
5-5 .................................................................. 79
5-6 ...................................................... 80
5-7 .............................................................. 80
5-8 .............................................................. 81
5-9 .............................................................. 82
5-10 ............................................................ 83
5-11 ........................................................ 83
5-12 ................................................................ 84
5-13 ............................................ 84
5-14 ............................................................ 85
-
x
1-1 [6] ........................................................................... 7
1-2 ...................................................................... 10
2-1 .......................................................... 15
2-2 [17] ....................................................................................... 19
3-1 .......................................................................... 22
3-2 .......................................................................... 45
3-3 SMD [25] ....................................... 46
3-4 SMD [25] ....................................... 46
3-5 SMD [26] ........................................................... 47
3-6 ...................................................... 50
3-7 .................................................. 51
3-8 ...................................................... 51
3-9 EA ............................... 51
3-10 ................................ 52
3-11 ........................................................ 52
3-12 ........................................................................ 54
4-1 .......................................................................... 56
4-2 .......................................................................... 69
4-3 .......................................................... 71
-
xi
4-4 .......................... 71
4-5 .......................... 72
4-6 .......................................................... 73
4-7 .................................. 73
4-8 .......................................................................... 75
-
1
1- 1
Integrated Circuit, IC
More than Moore
1-1 [1] / Analog/RF
Passive Power Sensor
Actuators Biochip
1-1 [1]
-
2
System on Chip,
SoC System in Package, SiP System
on Package, SoP Three-dimensional Integrated Circuit, 3D
IC
1-2
[2]
Power Converter
1-2 3D IC[2]
IC
-
3
[4]
1-3 World Semiconductor Trade Statistics,
WSTS [3] 2008 2012
Amplifier & Comparator
Signal Conversion Power Management
Interface Circuit
1-3 2008 2012 [3]
2009
50.9% 2010
-
4
IC DC-DC Converter
Personal Digital Assistants, PDA Digital Still Camera,
DSC Digital Video, DV mp3
1-4
Time to Market
-
5
1- 2
1-5
DC-DC Converter [5] Switching
Linear
Inductor based
Capacitor based
1-5 [5]
-
6
1-6 [6]
Graphite
Coke CMOS 0.35 m 2.8V
CMOS 0.18 m
1.8V
TSMC 0.1 CMOS 1P6M 1.8V/3.3V
1-6 [6]
-
7
Buck Converter
95%
90%
buck converter
Linear Low Dropout Voltage Regulator, LDO
Electro Magnetic
Interference, EMI
1-1 [6]
1-1 [6]
Parameters Linear Inductor based Capacitor based
Efficiency 20-60% 90-95% 75-90%
Ripple Very low Low Moderate
EMI Very low Moderate Low
Size(PCB Real Estate) Compact Largest Medium
Cost and Complexity Lowest Highest Medium
1-7 [7]
2006 2011
-
8
1-7 [7]
Buck converter LDO
buck converter LDO buck converter
LDO buck converter
LDO
buck converter LDO
-
9
1- 3
Operation amplifier, OPA
Knowledge-based
Equation-based Simulation-based [8]
BLADES[9]
[10]
[11]
[12] Buck converter
Control Circuit Convert Circuit
Efficiency [13] buck converter
buck converter PSpice
LDO [14] MATLAB
Geometric Programming, GP LDO
CADENCE SPECTRE
-
10
200pF
200pF
HSpice
C Tool
Command Language, Tcl
buck converter
Equivalent Series Resistance, ESR
LDO Load Regulation
Load Regulation LDO
1-2
1-2
Buck[12] Buck[13] LDO[14]
This work
Buck LDO
Convert circuit
Control circuit
Efficiency --- ---
Load/Line regulation --- --- ---
Automation tool
-
11
1- 4
Buck converter
LDO
buck converter LDO
buck converter
LDO
-
12
2- 1
2-1 V in R1
R2 Vout Vout V in
2-1
LDO 2-2 [6] R1
Pass Element
Feedback
-
13
2-3
2-2
2-3
2-2 [6]
2-3
2- 2
Switcher, S Inductor,
L Capacitor, C 2-4 Standard
Buck Converter V i Vo Io
S1 S2 (Power Metal Oxide Semiconductor Field
Transistor, Power MOSFET) Diode power MOSFET
MOSFET S2
Forward Voltage
PD 2.1 VD
-
14
2-4
2. 1
S2 power MOSFET 2-5
Synchronous Buck Converter
S2 N power
MOSFET S2 2.2
Ron power MOSFET On-resistance
2-5
2. 2
-
15
2-1 Io 600mA
power MOSFET
2-1
Case Io=600mA VD=0.7V Ron=0.05
Diode Power MOSFET
Power Losses mW 420 182
2- 2- 1
Buck Converter 2-6
Convert Circuit Control
Circuit
2-6
-
16
V i Io
V i Vo S1 S2
Feedback Vo Vref
Error Amplifier, EA EA Zi Zo EA Vo
Vref Vcon Pulse Width
Modulator, PWM PWM Comparator Vcon
Triangular Waveform Vtri d S1
S2
S1 S2 S2 S1
Shoot-through current
Nonoverlap Clock
nonoverlap clock buck converter
power MOSFET Driver
2- 2- 2
Continuous Conduction Mode, CCM Discontinuous
Conduction Mode, DCM [15] 2-7
iL(t) Ts iL(0) iL(0)
-
17
2-7
2-8 iL(t) Ts
2-8
buck converter
2- 3
LDO Pass Element
NPN PNP NMOS PMOS 2-9[16]
Bipolar Junction Transistor, BJT MOSFET
-
18
2-9 a NPN b PNP c NMOS d PMOS[16]
BJT MOSFET NPN
Base, B Emitter, E
Ignd
Vdo VBE
2.3 PNP
IB Ignd
Ignd PNP
Vdo VBE(min) 2.4 PNP NPN
2. 3
2. 4
MOSFET MOSFET Gate, G
Ignd NMOS Drain,
D Source, S Vdo NMOS
VGS 2.5 Body effect
-
19
2. 5
PMOS LDO p-channel MOS
Base, B
PMOS NMOS Threshold Voltage
NMOS LDO PMOS
2.6 PMOS VSD 2-2
2. 6
2-2 [17]
BJT MOSFET
NPN PNP NMOS PMOS
V in(min) Vo+Vdo VEB+VCE(min) Vo+Vdo VSG+VDS(sat)
Vdo VBE VEC(min) VGS VSD(sat)
I gnd 0 Io(max)/ 0 0
I o(max) Highest High Low Moderate
2- 3- 1
2-10 Linear Low Dropout Voltage Regulator, LDO
V i Pass Element
Vo
-
20
Sample Resistance Vref
Feedback Error Amplifier, EA
EA Vfb Vref
Gate
2-10
IL
EA MP MP
Co rcsr Co
shoot rcsr
Phase Margin, PM
-
21
3- 1
3-1 Buck Converter
Technology File Specification TSMC 0.1
CMOS 1P6M 1.8V/3.3V Discrete
Component
3-1
-
22
9 3-1 V i
Vo Io IL,rip Vo,rip fs
PM TSMC
Sheet ResistanceRsh
3-1
Item Specification Symbol Unit
1 Input voltage V i V
2 Output voltage Vo V
3 Maximum load current Io mA
4 Current ripple IL,rip mA
5 Voltage ripple Vo,rip mV
6 Switching frequency fs kHz
7 Efficiency %
8 Phase Margin PM deg
9 Resistor layout model --- ---
Steady State Analysis
Efficiency
Small Signal Analysis
C
Spice Netlist HSpice
Tool Command Language,
Tcl
I. Inductor
II. Capacitor III. Power MOS IV.
-
23
Compensation Network V. EA Unity-gain
Frequency
3-2 Current Ripple
3-3 Voltage Ripple
Efficiency 3-4 3-5
3-6 3-7
3- 2
Steady State Analysis Inductor, L
Current Ripple
Duty Cycle, D 3.1 D 1
Vo V i V i D Vo
3. 1
d S1 S2
S1 S2 buck converter
Switching Frequency Ts fs
3.2
3. 2
-
24
3.3 D vL
V i Vo V i Vo
iL 3-2 iL
1-D
Io
3. 3
3-2
-
25
current ripple IL,rip
IL IL,rip 3.4 L
IL,rip IL
current ripple 3.5 Lmin
3. 4
3. 5
Current Rating
Lmin
3.6
IL,rating [18] Io Io
3. 6
Datasheet Lmin IL,rating
DC Resistance,
DCR
-
26
3- 3
Convert Circuit
Capacitor, C Voltage Ripple
Vo
3-3 vo
Vo Io
Q [19] Q Io
3.7
Vo 3.8 C
Vo,rip Voltage Ripple Vo Vo,rip
3-3
-
27
3. 7
3. 8
IL
fs Vo,rip 3.8 Cmin
Equivalent Series Resistance, ESR
Vo [20]
3.8 IL 3.5 resr
Vo 3.9
fs
resr
3.9 resr,max
resr,max
3. 9
Datasheet Cmin resr,max
Cost
resr resr
-
28
3- 4
Buck converter Po
Pi 3.10 Pi Po
Ploss Pi Po Ploss
0 100
3.10
Po Vo Io
3.10 Power loss Ploss
Ploss Power MOSFET
Ploss Conduction Loss
buck converter S1 S2 L
C 3-4 Power MOSFET Drain
Source On-resistance S1 rp S2 rn
L DC Resistance, DCR rdcr C
Equivalent Series Resistance, ESR resr
3-4
-
29
R P 3.11
Irms
3.11
ISrms 3.12
Io IL S1 PS1 S2
PS2 3.13 3.14 rp rn S1 S2
3.12
3.13
3.14
ILrms ISrms 3.15
Io IL ICrms
Io ICrms Io IL
3.16 Io IL 3.5
ILrms ICrms
3.15
3.16
-
30
3.11
rdcr Pind 3.17
Pcap ICrms
resr ILrms ICrms 3.15 3.16 rdcr resr
Pind Pcap
3.17
3.18
3-4 3.19 S1
D 1-D PS1 D S2 1-D
D PS2 1-D
3.19
3.19 Ploss Pind
Pcap D PS1 PS2 3.20
On-resistance [21] 3.13 3.14
3.20
eff Carrier Mobility Cox Gate Oxide
Vth Threshold Voltage
-
31
Technology File VGS Gate, G
Source, S L 0.35
S1 P Wp S2 N
Wn P
N Wp Wn
3.21
buck converter Cg
3.22
Driver 3-5 [23] d Vg N
Inverter A
A 3.23 Cin1
Cin2
3.22
3-5
-
32
3.23
Cg 3.23
Cg Cin1
3.24
N N A 3.24
3.25
N 3.26 Cg
Win1
3.26
Steady State Analysis
Convert Circuit
Control Circuit
Small Signal Analysis
Control Circuit buck
converter
-
33
3- 5
Negative-feedback Control System buck converter
3-6
Transfer Function ~ ac
Compensated Error AmplifierGEA(s)
PWM GP(s) Convert
Circuit GCT(s)
3-6
GOL(s) GCT(s) GP(s)
GEA(s) 3.27
GCT(s) GP(s) GCT(s)GP(s)
GEA(s)
3.27
-
34
3- 5- 1
GCT(s)
State-space Averaging [19]
3-7 V i
Vo RL L rdcr C
resr a S1 S2 L V i
Charge Mode b S1 S2
V i Discharge Mode
a b
3-7 a b
State-variable Vector x
x1 x2
Kirchhoff s Voltage Law, KVL 3-7 a
3.28
3.29
-
35
3.30
State Matrix A1
V i B1
3.30
3-7 b
V i
3.31
A2 B2
3. 32
RL
x Transposed Vector
3.33
-
36
C 3.34 C1 C2
3.34
RL rdcr resr
3.35 A A1 3.36
C C1 B
3.37
3.35
3.36
3.37
Laplace Transformation ac
s-Domain GCT(s)
3.38
-
37
I Unity Matrix V i 3.35 3.37
3.38 GCT(s)
3.39
3.40
V i 0 L C
GCT(s) Quadratic Pole 180 z Simple
Zero C resr
GCT(s)
GP(s)
3.40
3- 5- 2
PWM vcon(t)
vtri(t) d(t) Duty Cycle vcon(t)
Vcon vcon(t)
3-8
-
38
3-8
vtri(t) Switching Frequency s
Sine Wave s
3.41 a
3.41
vcon(t) vtri(t) d(t)
vcon(t) vtri(t) d(t)
3.42
d(t) Fourier Series
3.43
-
39
3.44
GP(s) 3.41
3.44
3.45
3- 5- 3
GCT(s) GP(s) buck converter
buck converter GOL(s) [19]
GOL(s) Crossover Frequencyfco 0dB
Switching Frequency fs [20] fco
10% fs fs fs Harmonics
PWM
Phase Margin, PM buck converter
3.46
-
40
buck converter
Transient Response 45
60
EA
10 fs EA Two-stage
40MHz[24] 4MHz
3-9 EA
MEA PWM MEA
EA
90 GCT(s) LC 180
GP(s) GCT(s)
resr cross
z
3-9
-
41
20dB/decade z
0dB/decade p
EA 20dB/decade EA
boost
3.47
A z p 3-10 R C
R1 R2 C1 C2
90 RC 3.48
3-10
3.48
-
42
RC z p cross
K-factor
3.49
3.50
z cross K-factor p cross K-factor cross
Switching Frequency K-factor
boost
3.51
Phase Margin, PM boost
PWM GP(s) EA
Convert Circuit GCT(s)
PM 180
EA 90 boost
3.52
3.52 3.51 K-factor 3.49 3.50
GEA(s) EA 0dB
-
43
GEA(at cross) GCT(at cross) GP(at cross) 1 3.49
3.50 EA 3.47
3.53
R1 C2
C1 R2
3.54
TSMC 0.18 CMOS R C
3.55
AR AC
RC
3.55
3- 6
HSpice
-
44
d p r
3.56
3- 7
3-2 3-6
I. II. III. IV. V.
3-2
max max
TSMC 0.18 m CMOS
1.5mm 1.5mm 1.2mm 1.2mm
N 10mm 0.35 m P
max
-
45
3-2
Item Specification Constrain
Input voltage V 2.8 1.8~5
Output voltage V 1.2 < Input voltage
Maximum load current mA 300 50~600
Current ripple mA 60 < Output current
Voltage ripple mV 60 < Output voltage
Switching frequency MHz 0.5 0.1~4
Efficiency % 91.55 > 0
Phase Margin deg 45 45~60
Rsh square RW 7.9 1 From PDK
Step I Duty Cycle, D 3.1
0.43 Lmin IL,rating
3.5 3.6
SMD [25] 3-3
3-4
SCD1004
24 24 H
27 0.69A rdcr 0.12
-
46
3-3 SMD [25]
Inductance
Rating Current A Max.
SCD 0501
SCD 0502
SCD 0503
SCD 0504
SCD 0703
SCD 0705
SCD 1004
SCD 1005
4.7 1.80 2.00 2.50 --- --- 3.70 --- 2.60 5.6 1.60 1.80 2.40 --- --- 3.50 --- ---
6.8 1.50 1.70 2.20 --- --- 3.10 --- 4.33 8.2 1.30 1.40 2.00 --- --- 2.70 --- --- 10 1.10 1.20 1.80 1.44 1.44 2.30 2.38 2.60 12 1.05 1.18 1.75 1.40 1.39 2.00 2.13 2.45 15 1.00 1.15 1.70 1.30 1.24 1.80 1.87 2.27 18 0.95 1.10 1.60 1.23 1.12 1.60 1.73 2.15
22 0.90 1.00 1.50 1.11 1.07 1.50 1.60 1.95
27 0.77 0.86 1.40 0.97 0.94 1.30 1.44 1.76
33 0.68 0.76 1.10 0.88 0.85 1.20 1.26 1.50 39 0.67 0.75 1.00 0.80 0.74 1.10 1.20 1.37 47 0.66 0.73 0.90 0.72 0.68 1.10 1.10 1.28 56 0.50 0.55 0.85 0.68 0.64 0.94 1.01 1.17 68 0.47 0.52 0.80 0.61 0.59 0.85 0.91 1.11 82 0.45 0.50 0.65 0.58 0.54 0.78 0.85 1.00
100 0.36 0.40 0.60 0.52 0.51 0.72 0.74 0.97 120 0.32 0.36 0.58 0.48 0.49 0.66 0.69 0.89
3-4 SMD [25]
Inductance
DC Resistance Max.
SCD 0501
SCD 0502
SCD 0503
SCD 0504
SCD 0703
SCD 0705
SCD 1004
SCD 1005
4.7 0.134 0.14 0.07 --- --- 0.04 --- 0.04
5.6 0.170 0.15 0.08 --- --- 0.04 --- --- 6.8 0.187 0.16 0.09 --- --- 0.04 --- 0.037 8.2 0.225 0.17 0.10 --- --- 0.05 --- --- 10 0.255 0.18 0.12 0.10 0.08 0.07 0.05 0.06 12 0.292 0.20 0.13 0.12 0.09 0.08 0.06 0.07 15 0.360 0.22 0.15 0.14 0.10 0.09 0.07 0.08
18 0.430 0.25 0.18 0.15 0.11 0.10 0.08 0.09 22 0.492 0.35 0.22 0.18 0.13 0.11 0.09 0.10
27 0.603 0.45 0.26 0.20 0.15 0.12 0.10 0.11
33 0.796 0.56 0.33 0.23 0.17 0.13 0.12 0.12 39 0.897 0.69 0.42 0.32 0.22 0.16 0.15 0.14 47 1.020 0.72 0.50 0.37 0.25 0.18 0.17 0.17 56 1.164 0.84 0.55 0.42 0.28 0.24 0.20 0.19 68 1.220 0.90 0.65 0.46 0.33 0.28 0.22 0.21
82 1.57 1.20 0.8 0.60 0.41 0.37 0.25 0.28 100 1.80 1.30 0.90 0.70 0.48 0.43 0.34 0.35 120 2.00 1.38 1.00 0.93 0.54 0.47 0.40 0.40
-
47
Step II SMD [26]
buck converter
80mA 35V ESR resr
3.9 1.184
ESR
3-5 SMD [26]
CapacitanceF
Working Voltage Vdc
16V 25V 35V 50V
ESR
mA ESR
mA
ESR
mA ESR
mA
4.7 --- --- --- --- 1.8 80 --- ---
10 --- --- 18 80 0.76 150 0.88 165
22 0.76 150 0.76 150 0.76 150 0.88 165 33 --- --- 0.44 230 0.44 230 0.75 185 47 0.44 230 0.44 230 0.44 230 0.75 185 100 0.44 230 0.34 280 --- --- 0.40 300
150 0.34 280 0.34 450 0.17 450 0.22 670 220 0.34 280 0.17 450 0.17 450 0.22 670 330 0.17 450 0.17 450 0.09 670 --- --- 470 0.17 450 0.09 670 --- --- --- ---
rdcr resr Pind
Pcap max 3.10
-
48
Po D ISrms rp,min P
20mm/0.35 m rn,min N
10mm/0.35 m
Step III 94% 91.55%
3.20 rp rn
P W=10 L=0.35 m M=1596
N W=10 L=0.35 M=798
W L M W M
P N
3.22 P N
3.25 3.26 Driver
N A
P driver N=7, A=3
N driver N=6, A=3
P
N
-
49
Step IV fs
5MHz PM
3-5 3.39 50kHz
MCT -12.01dB Mp 3.45
-8.3dB MEA
-90.8 PM
45 boost 3.52
3.53 3.54 TSMC
0.18m CMOS Rsh
7.9 RW1 m RL RW RL
MIM
S Acom
3.55 R1 R2
20.8k 258k C1 C2 30.4pF 6pF
-
50
Step V buck converter 0.5MHz
EA
ApowerMOS A logic Driver
APWM PWM AEA
Acom
Step VI HSpice
3-6
3-7
3-6
Item Value
Duty cycle 0.43
Load resistance 4
Inductor DC resistance 27 0.12
Capacitor Series resistance 10 0.76
Power PMOS size W = 10um L = 0.35um M = 1596
Power NMOS size W = 10um L = 0.35um M = 798
EA unity-gain frequency MHz 5
Compensation parameters R1 =20.8k R2 =258k
C1 =30.4pF C2=6pF
Area m2
94107.89
-
51
3-7
Efficiency Specification Simulation Difference d
% 91.55 90.85 -0.7
d -0.7
3.56 r
p
3-8 0.15
3-8
Efficiency Specification Revision Simulation Difference d
% 91.55 92.25 91.70 0.15
3-9 buck converter EA EA
EA
[13] EA EA
0.5 3-10
3-9 EA
Efficiency With EA Without EA
% 91.70 91.93
-
52
3-10
Specification Simulation Difference
[13] Efficiency % 91.55
91.86 0.31
This Work Efficiency % 91.70 0.15
3-11 3-6
M
M
3-11
Item Value
Duty cycle 0.43
Load resistance 4
Inductor DC resistance 27 0.12
Capacitor Series resistance 10 0.76
Power PMOS size W = 10um L = 0.35um M = 1872
Power NMOS size W = 10um L = 0.35um M = 936
EA unity-gain frequency MHz 5
Compensation parameters R1 =20.8k R2 =258k
C1 =30.4pF C2=6pF
Area m2
95556.89
3-11 d P S1
N S2 Vo d P
S1 P S2
35.2mV
-
53
d
Vo
3-11
3-12 buck converter
Iout 30mA 150mA 300mA 1.2V
Undershoot 30mA
300mA Overshoot
300mA 30mA
Vo
Io
3-12
-
54
3-12
3-12
Item Specification Simulation
Input voltage V 2.8
Output voltage V 1.2 1.20
Maximum load current mA 300 299.6
Output power mW 360 359.10
Voltage ripple mV 60 35.2
Efficiency % 91.55 91.70
-
55
4- 1
4-1
TSMC 0.1 CMOS 1P6M 1.8V/3.3V LDO
4-1
Technology File Specification LDO
4-1 9 V i V i,rip
-
56
Vo Io Iq Line Load
PM TSMC Rsh
4-1
Item Specification Symbol Unit
1 Input voltage V i V
2 Input voltage ripple V i,rip %
3 Output voltage Vo V
4 Maximum load current IL mA
5 Quiescent current Iq A
6 Line regulation Line mV/V
7 Load regulation Load mV/mA
8 Phase margin PM deg
9 Resistor layout model --- ---
Steady State Analysis
Small Signal Analysis
EA
Spice Netlist HSpice
C
HSpice
Tool Command Language, Tcl LDO
I. Power MOS II. Sample
Resistance III. Output Capacitor IV. Compensation
-
57
Series Resistance, CSR V. EA Unity-gain Frequency
Dropout Voltage
4-2 4-3
Quiescent Current
Line Regulation Load Regulation 4-4 4-5
4-6
Frequency Response
4-7 4-8
LDO
4- 2
Regulation Region 4-2 V i
Vo
Vdo
4-2
-
58
Saturation Region Linear Region LDO
Dropout Region Transconductance
LDO Off Region
LDO 0.6V [17]
P N
2-3 P
Vdo
4.1
eff Carrier Mobility Cox Gate Oxide
Technology File ILmax
L 0.35 LDO
Vdo PMOS
4- 3
Sample Resistance
Vo V fb Vref
-
59
Quiescent Current Ground Current [27] 4-3
LDO Iq Ii Io
4-3
Rs1 Rs2 4-4 Iq
Vo Ohm's
Law Rs1 Rs2 4.2
Vfb Vo 4.3 Vfb
Rs1 Rs2
4-4
4. 2
4. 3
-
60
Iq 4.4 IL
Iq LDO
4. 4
4- 4
Line Regulation Vo V i
[27]
4. 5
4-5 V i
Vo
4-5
-
61
4. 6
RL Rop AEA
gmp Vfb 4.3
4.6
4. 7
4. 8
LDO
LDO AEA
gmp
AEA
4- 5
Load Regulation
-
62
Vo IL [27]
4. 9
4-6 IL
Vo LDO
4-6
IL Vfb
4.10
-
63
RL AEA gmp 4.3
Vfb Vo
4.11
AEA
gmp LDO
gmp
4- 6
LDO Vfb
AC 4-7[28]
4-7 AC [28]
-
64
AC A EA gea
EA Transconductance Rp B MP
gmp MP Cp MP Rop
On-resistance C Rs1 Rs2 D Co
Compensation Series Resistance, CSR rcsr rcsr
Equivalent Series Resistance, ESR resr
Additional Resistance radd
AC vsig
4.12
Zout
4.13
RL 4.12 4.13
[17]
Rp Cp
4.14
-
65
MP Rop Co
4.15
Co rcsr
4.16
10pF 200pF [28]
PEA PMP
Rop rcsr Zout
PEA PMP
Zout
4-8
4-8
-
66
4-8 PEA PMP 180 Zout
Unity-gain Frequency Phase Margin, PM
0
rcsr Zout 4-9 Zout PM
4-9
rcsr resr radd
4.17 resr
radd radd
resr Zout radd
4.17
LDO EA
LDO
-
67
Folded Cascade
500MHz[29] Co EA
500MHz LDO radd
Co radd
Macro Model
4- 7
HSpice
4.8
Line AEA
4.18
Line Lines AEA
AEA,r
4.11 Load
AEA
4.19
Load Loads
-
68
AEA,r
AEA,r AEA,max
4.20
Line Linelower
4.21
Load Loadlower
4- 8
4-2 LDO
AEA,max 60dB fEAunity,max
500MHz AEA,max fEAunity,max
LDO PM PM
500MHz LDO I.
II. III. V. 4-2 4-7
-
69
4-2
Item Specification Constrain
Input voltage V 2 1.8~5
Input ripple % 10 < 40
Output voltage V 1.2 < Input voltage
Maximum load current mA 200 50~600
Quiescent current A 100 50~600
Line regulation mV/V 3 > 0
Load regulation mV/A 6 > 0
Phase Margin deg 50 60
Rsh square RW 7.9 1 From PDK
Step I Vdo 1.9V
4.1
MP W=10 m L=0.35 m M=675
W L M W 10 m L
0.35 m M
MP W M
Step I I Rs1 Rs2 4.2 Rs1
Rs2
-
70
4.3 Vfb Vo
Rs1 Rs2
Vfb Vref
4.14 4.16 LDO
49 60
Step II I
4.14 4.16
resr radd
fEAunity fEAunity 500MHz radd Co
Co=72pF, resr=3.55 , radd=0 , fEAunity=456MHz
W L TSMC 0.18m CMOS
Rsh 7.9 RW 1 m
RL Rsh RW RW RL
MIM
-
71
AMP ARs ACo Aradd
1000V/V EA 100V/V 1000V/V
Step IV 4-3
4-3
Item Value
Load resistance 6
Pass element W = 10um L = 0.35um M = 675
Sample resistance k Rs1 = 3
Rs2 = 9
EA Gain dB 40
Unity-gain frequency MHz 456
Capacitor pF series resistance 72 3.55
Additional resistance 0
Area m2
73625.55
HSpice
4-4
Specification Simulation Difference
Line regulation mV/V 3 14.06 -11.06
Load regulation mV/A 6 52.40 -46.4
-
72
4-4
4.18 4.19
867V/V
EA 867V/V 1000V/V
4-5
Specification Simulation Difference(%)
Line regulation mV/V 3 1.62 1.38
Load regulation mV/A 6 5.98 0.02
4-5
Over Design
4-6 LDO 4-3
LDO
-
73
4-6
Item Value
Load resistance 6
Pass element W = 10um L = 0.35um M = 675
Sample resistance k Rs1 = 3
Rs2 = 9
EA Gain dB 58.76
Unity-gain frequency MHz 327
Capacitor pF series resistance 126 4.56
Additional resistance 0
Area m2
126146.5
[14]LDO 200pF
200pF
200pF 4-7
126pF 200pF 37.6% LDO Atotal
96.9%
4-7
Co pF ACo m2
[14] 200 194287.7
This work 126 126146.5
4-10 Line regulation Load
regulation 0.4mV
1.5mV
-
74
Line regulation
Load regulation
4-10
4-11 LDO Vout ILoad
20mA 100mA 200mA 1.5mV
buck converter
Vout
ILoad
4-11
-
75
4-8 LDO
4-8
Item Specification Simulation
Input voltage V 2.0
Input voltage ripple % 10
Output voltage V 1.2 1.20
Maximum load current mA 200 200.2
Quiescent current A 100 100.1
Effic iency % 60 60.02
Line regulation mV/V 3 1.62
Load regulation mV/A 6 5.98
-
76
5- 1
Linux
5-1 Option
Buck Converter Low Dropout Regulator
Buck converter
5-1
Specification Generate HSpice
Netlist Parameters Performance
-
77
Please press Specification
Netlist
Parameters
Performance
5- 2
5-2
Please input value
5-2
Input voltage Output voltage
Max load current Current ripple Voltage
ripple Switching Efficiency Phase margin
Rsh Resistor width TSMC 0.1 CMOS
-
78
1P6M 1.8V/3.3V 1.8V 5V
600mA
4MHz buck converter
45 60 PDK
OK
5-3
Confirmation
5-3
5-4
V i Vo Io