PDACSPDACS

Midterm Presentation

Michelle Berger

John Curtin

Trey Griffin

Aaron King

Michael Nordfelt

Jeffrey Whitted

PDACSPDACS

Getting Started

• Finalized components– Harris Semiconductor 8-bit A/D Converter (ADC804 )

– Texas Instruments 8-bit D/A Converter (TLC7524)

– National Semiconductor 16550 UART

– Maxim 232 Chip

– Atmel Serial DataFlash Memory (AT45D161)

• Established electronic log and expenditures files

PDACSPDACS

Team Assignments

• A/D - D/A Team (Michelle & Aaron)• Serial / GUI Team (Mike & Trey)• Memory Team (John & Jeffrey) • Compression (Michelle, John, & Aaron)

After we obtained our components and our collectivegroup decisions were made, we split ourselves up into three distinct teams:

PDACSPDACS

D/A - A/D Team

Progress:• A/D handled by ADC0804

• Test circuit indicates A/D provides expected response

• D/A handled by TLC7524

• Test circuit indicates D/A provides expected response

• A/D - D/A test circuit built and provides expected response

• Numerous problems encountered with D/A before settling on TLC7524 chip

PDACSPDACS

D/A Problems

• The DAC0830 worked correctly but its conversion rate was too slow to keep up with the A/D.

• The DAC0800 was a troublesome chip. – Five separate test circuits built with the 0800

– Example: one test circuit behaved correctly until the output voltage approached 0.7 volts; beyond that point the output voltage was unpredictable

– Result: none of the test circuits worked correctly, so we moved to another chip

PDACSPDACS

D/A Solutions

These are possible solutions we considered for D/A:• Work with resistor values to get the 0800 to work

• Try another chip we had just received: the TLC7524

• Reduce sampling rate so the 0830 is fast enough

• Build our own D/A converter using discrete components

We chose to try the TLC7524, which proved to be a viable solution.

PDACSPDACS

A/D-D/A Test Circuit

PDACSPDACS

Memory Subsystem• Atmel 16-Megabit 5-volt Serial DataFlash

Memory

SO

Buffer 1 (528 Bytes) Buffer 2 (528 Bytes)

Page (528 Bytes)

Flash Memory Array

I/O Interface

SI

PDACSPDACS

Memory SubsystemVerilog module flow:• Determine read, buffer write, or main memory

program and set matching opcode• Clock in the necessary bits one at a time• Update control variables and test the edge

conditions

PDACSPDACS

• Read command

• Buffer write command

• Main memory program command

Memory Subsystem

Opcode Page address Byte address Don’t Care [X](10 bits) (12 bits) (10 bits) (32 bits)

Opcode Don’t Care [X] Buffer address (10 bits) (12 bits) (10 bits)

Opcode Page address Don’t Care [X](10 bits) (12 bits) (10 bits)

PDACSPDACS

Memory Subsystem

Problems:• Large number of values to track• SCK pin

To do:• Test read functionality• Test write functionality

PDACSPDACS

Serial Subsystem

Specs:• Consists of two chips(16550 UART and Max232)

and a 9-pin serial jack• Pin count to the Xilinx stands at 18

Progress:• Logical layout for pins and chips determined• Ordering of signals for communication determined

PDACSPDACS

Serial Subsystem

To do:• Xilinx control module for the 16550 UART• Physical layout• Testing

– Interfacing with memory access module

– Interfacing with the GUI

PDACSPDACS

Serial Subsystem

Picture goes here, maybe a communications diagram

D0D1D2D3D4D5D6D7

A0 A1 A2

INTR RD__

WR__

XILINX

D0D1D2D3D4D5D6D7RCLK

SIN

SOUTCS0CS1

CS2___

__________BAUDOUT

XIN

XOUT

WR___

WR

Vss

Vdd

RI__

____DCD____DSR____CTS

MR_____OUT1

____DTR____RTS

_____OUT2

INTR______RXRDY

A0A1A2

____ADS

______TXRDY

DDIS

RD__RD

PC16550DN

RX

MAX232

Vcc

GNDT1out

R1in

R1out

T1in

T2in

R2out

C1+

V+

C1-

C0+

C2+

V-

T2out

R2in

GND

DSR

DTR

Vcc

GND

Vcc

GND

MR

TX

CLK

RXRDY_______

TXRDY_______

PDACSPDACS

Serial Subsystem

Memory XILINX 16550 ApplicationMaster Reset

DSRInterrupt

Check MSR

DSR ActiveNotify GetData

Data

Last Block

DataData

DataData

Set DTR

DTR

DTR (Data finished) DSR

Max232(Computer Ready)

PDACSPDACS

GUI

• Allows user to access the serial port and download the data from the device.

• The GUI was developed in Visual Basic (to allow rapid development)

• Visual Basic allows read/writing to all control lines for serial communication.

PDACSPDACS

GUI

Future considerations:• Decompresses sound files through software,

output to a .wav file• Allow user to play a

compressed file

through the Windows

soundplayer.

PDACSPDACS

Serial/GUI Integration

• Used a Basic Stamp II to simulate serial port activity.

• GUI effectively captures all serial port traffic and dumps it to a binary file.

• GUI is capable of setting and reading all of the necessary control lines.

PDACSPDACS

Compression Algorithms

• Companding Algorithm– written in Verilog

– achieves 2:1 compression ratio

– very lossy

• DCT Algorithm– Experimented with in C

– In progress

PDACSPDACS

Breakdown of Work

• Michelle Berger - Compression & A/D & D/A systems

• John Curtin - Compression & Memory systems

• Trey Griffin - GUI & Serial Interface systems

• Aaron King - A/D & D/A systems

• Michael Nordfelt - GUI & Serial Interface systems

• Jeffrey Whitted - Memory system

Division of Labor to date

PDACSPDACS

Schedule of Work

• Weeks 1-3– A/D and D/A

– Compression Research

– Finalize Components

• Weeks 4-6– Serial Port Interface Researched/GUI Developed

– Memory Module Finalized/Hardware Wrapped

– A/D and D/A Developed

PDACSPDACS

Schedule of Work

• Weeks 7-10– Compression Research/XILINX Implementation

– A/D and D/A Finalization

– Serial Hardware Finalization

• Weeks 11-12– Final System Integration

– Testing

– Final Presentation and Product Delivery

PDACSPDACS

Ratings

• Level of difficulty– 1

• Coordination among team members– 1

• Support from the lab– 1

PDACSPDACS

And Remember…

Xilinx is cool, but it’s occasionally bogus.

-Scott