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IRFR/U9024NPRELIMINARYHEXFET Power MOSFET

Parameter Typ. Max. UnitsRJC Junction-to-Case 3.3RJA Junction-to-Ambient (PCB mount)** 50 C/WRJA Junction-to-Ambient 110

Thermal Resistance

D-PakTO - 2 5 2 A A

I-PakTO-251AA

l Ultra Low On-Resistancel P-Channell Surface Mount (IRFR9024N)l Straight Lead (IRFU9024N)l Advanced Process Technologyl Fast Switchingl Fully Avalanche Rated

Description

Parameter Max. UnitsID @ TC = 25C Continuous Drain Current, V GS @ -10V -11ID @ TC = 100C Continuous Drain Current, V GS @ -10V -8 AIDM Pulsed Drain Current -44PD @T C = 25C Power Dissipation 38 W

Linear Derating Factor 0.30 W/CVGS Gate-to-Source Voltage 20 VEAS Single Pulse Avalanche Energy 62 mJIAR Avalanche Current -6.6 AEAR Repetitive Avalanche Energy 3.8 mJdv/dt Peak Diode Recovery dv/dt -10 V/nsTJ Operating Junction and -55 to + 150TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds 300 (1.6mm from case )C

Absolute Maximum Ratings

Fifth Generation HEXFETs from International Rectifierutilize advanced processing techniques to achieveextremely low on-resistance per silicon area. Thisbenefit, combined with the fast switching speed andruggedized device design that HEXFET PowerMOSFETs are well known for, provides the designerwith an extremely efficient and reliable device for usein a wide variety of applications.

The D-Pak is designed for surface mounting usingvapor phase, infrared, or wave soldering techniques.The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levelsup to 1.5 watts are possible in typical surface mountapplications.

PD - 9.1506

VDSS = -55V

R DS(on) = 0.175

ID = -11AS

D

G

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IRFR/U9024N

Fig 4. Normalized On-ResistanceVs. Temperature

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

0.1

1

10

100

0.1 1 10 100

20s PULSE WIDTHT = 25 CJ

TOP

BOTTOM

VGS-15V-10V-8.0V-7.0V-6.0V-5.5V-5.0V-4.5V

-V , Drain-to-Source Voltage (V)

- I

, D r a

i n - t o - S o u r c e

C u r r e n

t ( A )

DS

D

-4.5V

0.1

1

10

100

0.1 1 10 100

20s PULSE WIDTHT = 150 C

J

TOP

BOTTOM

VGS-15V-10V-8.0V-7.0V-6.0V

-5.5V-5.0V-4.5V

-V , Drain-to-Source Voltage (V)

- I

, D r a

i n - t o - S o u r c e

C u r r e n

t ( A )

DS

D

-4.5V

-60 -40 -20 0 20 40 60 80 100 120 140 1600.0

0.5

1.0

1.5

2.0

2.5

T , Junction Temperature( C)

R

, D r a

i n - t o - S o u r c e

O n

R e s

i s t a n c e

( N o r m a

l i z e

d )

J

D S ( o n )

V =

I =

GS

D

-10V

-11A

0.1

1

10

100

4 5 6 7 8 9 10

V = -25V20s PULSE WIDTH

DS

-V , Gate-to-Source Voltage (V)

- I

, D r a

i n - t o - S o u r c e

C u r r e n

t ( A )

GS

D

T = 150 CJ

T = 25 CJ

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IRFR/U9024N

Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.Gate-to-Source Voltage

Fig 5. Typical Capacitance Vs.Drain-to-Source Voltage

Fig 7. Typical Source-Drain DiodeForward Voltage

0.1

1

10

100

0.2 0.6 0.9 1.3 1.6-V ,Source-to-Drain Voltage (V)

- I

, R e v e r s e

D r a

i n C u r r e n

t ( A )

SD

S

D

V = 0 VGS

T = 25 CJ

T = 150 CJ

0.1

1

10

100

1000

1 10 100

OPERATION IN THIS AREA LIMITED

BY RDS(on)

Single PulseTT

= 150 C= 25 C

JC

-V , Drain-to-Source Voltage (V)

- I ,

D r a

i n C u r r e n

t ( A )

I ,

D r a

i n C u r r e n

t ( A )

DS

D

10us

100us

1ms

10ms

0

1 0 0

2 0 0

3 0 0

4 0 0

5 0 0

6 0 0

7 0 0

1 1 0 1 0 0

C ,

C a p a c i t a n c e ( p F )

D SV , Drain-to-Source Voltage (V)

A

V = 0V, f = 1MHzC = C + C , C SHORTEDC = CC = C + C

GSiss gs gd dsrss gdoss ds gd

C is s

C o s s

C r s s

0

4

8

1 2

1 6

2 0

0 5 1 0 1 5 2 0 2

G

G S

- V

, G a t e - t

o - S

o u r c e V o l t a g e ( V )

Q , Total Gate Charge (nC)

FOR TEST CIRCU I

SEE FIGURE 13

I = -7.2A

V = -44VV = -28V

D

DSDS

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IRFR/U9024N

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current Vs.Case Temperature

Fig 10a. Switching Time Test Circuit

Fig 10b. Switching Time Waveforms

VDS

-10VPulse Width 1 sDuty Factor 0.1 %

RD

VGS

VDDR G

D.U.T.

+

-

V DS

90%

10%

V GS

td(on) tr td(off) tf

25 50 75 100 125 1500.0

3.0

6.0

9.0

12.0

T , Case Temperature ( C)

- I ,

D r a

i n C u r r e n

t ( A )

C

D

0.01

0.1

1

10

0.00001 0.0001 0.001 0.01 0.1

Notes:1. Duty factor D = t / t2. Peak T =P x Z + T

1 2

J DM thJC C

P

t

t

DM

1

2

t , Rectangular Pulse Duration (sec)

T h e r m a

l R e s p o n s e

( Z

)

1

t h J C

0.010.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE(THERMAL RESPONSE)

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IRFR/U9024N

Fig 13b. Gate Charge Test CircuitFig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche EnergyVs. Drain Current

QG

QGS QGD

VG

Charge

-10V

D.U.T.VDS

IDIG

-3mA

VGS

.3F

50K

.2F12V

Current RegulatorSame Type as D.U.T.

Current Sampling Resistors

+

-

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

tp

V( B R ) D S S

IAS

R G

IA S

0 .01tp

D.U.T

LVD S

VD D

D R I V E RA

15 V

-20V

-+

VDD

25 50 75 100 125 1500

20

40

60

80

100

120

Starting T , Junction Temperature ( C)

E

, S i n g

l e P u

l s e

A v a

l a n c h e

E n e r g y

( m J )

J

A S

IDTOP

BOTTOM

-3.0A-4.2A-6.6A

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IRFR/U9024NPeak Diode Recovery dv/dt Test Circuit

P.W.Period

di/dt

Diode Recoverydv/dt

Ripple 5%

Body Diode Forward DropRe-AppliedVoltage

ReverseRecoveryCurrent

Body Diode ForwardCurrent

VGS =10V

VDD

ISD

Driver Gate Drive

D.U.T. I SD Waveform

D.U.T. V DS Waveform

Inductor Curent

D = P.W.Period

+

-

+

+

+-

-

-

R GVDD

dv/dt controlled by R G ISD controlled by Duty Factor "D" D.U.T. - Device Under Test

D.U.T*Circuit Layout Considerations

Low Stray Inductance

Ground Plane Low Leakage InductanceCurrent Transformer

* Reverse Polarity of D.U.T for P-Channel

VGS

[ ]

[ ]

***VGS = 5.0V for Logic Level and 3V Drive Devices

[ ] ***

Fig 14. For P-Channel HEXFETS

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IRFR/U9024N

Package OutlineTO-252AA OutlineDimensions are shown in millimeters (inches)

TO-252AA (D-Pak)

Part Marking Information

6.73 (.265)6.35 (.250)

- A -

4

1 2 3

6.22 (.245)5.97 (.235)

- B -

3X 0.89 (.035)0.64 (.025)

0.25 (.010) M A M B

4.57 (.180)

2.28 (.090)

2X1.14 (.045)0.76 (.030)

1.52 (.060)1.15 (.045)

1.02 (.040)1.64 (.025)

5.46 (.215)5.21 (.205)

1.27 (.050)0.88 (.035)

2.38 (.094)2.19 (.086)

1.14 (.045)0.89 (.035)

0.58 (.023)0.46 (.018)

6.45 (.245)5.68 (.224)

0.51 (.020)MIN.

0.58 (.023)0.46 (.018)

LEAD AS SIGNMENTS1 - GATE2 - DRAIN3 - SOURCE4 - DRAIN

10.42 (.410)9.40 (.370)

NOTES:1 DIMENSIONING & TOLER ANCING PER ANSI Y14.5M, 1982.2 CONTRO LLING DIMENSION : INCH.3 CONFORMS TO JEDEC OUTLINE TO-252AA.4 DIMENSIONS SHO WN ARE BEFORE SOLDER DIP,

SOLDER DIP MA X. +0.16 (.006).

INTERNATIONAL

RECTIFIERL O G O

ASSEMBLYLOT CODE

EXAM PLE : THIS IS AN IRFR120WIT H A SSEMB LYLOT CODE 9U1P FIRST PORTION

OF PART NUMBER

SECOND PORTIONO F PA RT N U M B E R

12 0IRFR

9U 1P

A

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IRFR/U9024N

Package OutlineTO-251AA Outline

Dimensions are shown in millimeters (inches)

TO-251AA (I-Pak)

Part Marking Information

INTERNATIONALRECTIFIER

LOGO

ASSEMBLYL O T C O D E

FIRST PORTION

OF PART NUMBER

SECOND PORTIONO F PA RT N U M B E R

1209 U 1 P

EXAM PLE : THIS IS AN IRFU120WIT H A S SEMB LYLOT CODE 9U1P

IRFU

6.73 (.265)6.35 (.250)

- A -

6.22 (.245)5.97 (.235)

- B -

3X 0.89 (.035)0.64 (.025)

0.25 (.010) M A M B2.28 (.090)

1.14 (.045)0.76 (.030)

5.46 (.215)5.21 (.205)

1.27 (.050)0.88 (.035)

2.38 (.094)2.19 (.086)

1.14 (.045)0.89 (.035)

0.58 (.023)0.46 (.018)

LEAD AS SIGNMENTS1 - GATE2 - DRAIN3 - SOURCE4 - DRAIN

NOTES:1 DIMENSIONING & TOLER ANCING PER ANSI Y14.5M, 1982.2 CONTRO LLIN G DIMENSION : INCH.3 CONFORMS TO JEDEC OUTLINE TO-252AA.4 DIMENSIONS SHOW N ARE BEFORE SOLDER DIP,

SOLDER DIP MA X. +0.16 (.006).

9.65 (.380)8.89 (.350)

2X

3X

2.28 (.090)1.91 (.075)

1.52 (.060)1.15 (.045)

4

1 2 3

6.45 (.245)5.68 (.224)

0.58 (.023)0.46 (.018)

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