PCS IP Core (HIP500)
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Overview External Interfaces Blocks description REG_FILE: holds configuration and status registers CLK_DIV: Clock divider which divides functional clock and provides referent clock for Ser/Des Lane’s PLLs. SF_GEN: This is a Super Frame (SF) generation module which takes an incoming stream of data from the ILB block, and packs it into SF structure (eight 8-bits output data streams) that are ready to be encoded. Each Super Frame starts with Lane Marker character that is transmitted over all 8 Lanes. In case when there is no SF on its input, SF_GEN is responsible for insertion of idle charac- ters. 8B10B_ ENC: The 8B10B encoder converts payload and control octets into 10 bit words. There are 8 instances of this block, one per lane, denoted 8B10B_ENC0 – 8B10B_ENC7. The usage of 8B10B code improves the transmission characteristics of information to be transferred across the link. It ensures that sufficient transitions are present in the PHY bit stream to make clock recovery possi- ble at the receiver. The encoding also greatly increases the likelihood of detecting any single or multiple bit errors that may occur during reception of information. SF_REC: This module performs the super frame recovery function, and unpacks the data stream received from the 8 channels into a data output bus. It contains lane alignment logic which com- pensates for the skew accommodated by each lane. SF_REC ignores idle characters; it starts to reconstruct frames upon detection of lane marker character. PCS IP Core (HIP500) HDL Design House, Golsvortijeva 35, Belgrade, Serbia Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com HIP500 DS.REV.1.0 30.01.2013 Key Features: • Highly configurable, more than 30 registers available • Supports 8 Lanes in TX and 8 Lanes in RX path • Lane misalignment of up to 8 octets is sup- ported • 8B10B encoding/decoding applied • PRBS generation/verification support (both per Lane and per SF payload) • Per Lane Loopback supported • Various reference clock support for Ser/Des Lane’s PLL • Fully synchronous design The Physical Coding Sublayer (PCS) IP Core enables trans- mission and reception of data via 8-Lanes SerDes inter- face. It is able to multiplex a synchronous digital stream of data over 8 Lanes, while guaranteeing data alignment and super-frame synchronization. The PCS is responsible for idle sequence generation, lane striping and encoding for transmission and decoding, lane alignment and restriping on reception. The PCS uses an 8B/10B encoding for trans- mission over the link. This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow APB interface: APB interface is used for configuration of PCS IP core. It is compatible with AMBA APBv1.0. It allows external access to core’s (and Ser/Des) configuration, status and error counters. SerDes interface: This interface is used to transfer/receive 10-bit data to Ser/from Des. It provides 10-bit clock for Ser/Des and contains a number of signals used for Ser/Des configuration. Data interface: Parallel interface through which PCS IP receives super frames to be processed and through which PCS delivers reconstructed frames received from Des Lanes.
Transcript of PCS IP Core (HIP500)
Overview
External Interfaces
Blocks descriptionREG_FILE: holds configuration and status registersCLK_DIV: Clock divider which divides functional clock and provides referent clock for Ser/DesLane’s PLLs.SF_GEN: This is a Super Frame (SF) generation module which takes an incoming stream of datafrom the ILB block, and packs it into SF structure (eight 8-bits output data streams) that are readyto be encoded. Each Super Frame starts with Lane Marker character that is transmitted over all 8Lanes. In case when there is no SF on its input, SF_GEN is responsible for insertion of idle charac-ters.8B10B_ ENC: The 8B10B encoder converts payload and control octets into 10 bit words. There are8 instances of this block, one per lane, denoted 8B10B_ENC0 – 8B10B_ENC7. The usage of 8B10Bcode improves the transmission characteristics of information to be transferred across the link. Itensures that sufficient transitions are present in the PHY bit stream to make clock recovery possi-ble at the receiver. The encoding also greatly increases the likelihood of detecting any single ormultiple bit errors that may occur during reception of information. SF_REC: This module performs the super frame recovery function, and unpacks the data streamreceived from the 8 channels into a data output bus. It contains lane alignment logic which com-pensates for the skew accommodated by each lane. SF_REC ignores idle characters; it starts toreconstruct frames upon detection of lane marker character.
PCS IP Core (HIP500)
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIP500 DS.REV.1.0
30.01.2013
Key Features:
• Highly configurable, more than 30 registersavailable
• Supports 8 Lanes in TX and 8 Lanes in RXpath
• Lane misalignment of up to 8 octets is sup-ported
• 8B10B encoding/decoding applied
• PRBS generation/verification support (bothper Lane and per SF payload)
• Per Lane Loopback supported
• Various reference clock support for Ser/DesLane’s PLL
• Fully synchronous design
The Physical Coding Sublayer (PCS) IP Core enables trans-mission and reception of data via 8-Lanes SerDes inter-face. It is able to multiplex a synchronous digital stream ofdata over 8 Lanes, while guaranteeing data alignment andsuper-frame synchronization. The PCS is responsible foridle sequence generation, lane striping and encoding fortransmission and decoding, lane alignment and restripingon reception. The PCS uses an 8B/10B encoding for trans-mission over the link.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow
APB interface: APB interface is used for configuration ofPCS IP core. It is compatible with AMBA APBv1.0. It allowsexternal access to core’s (and Ser/Des) configuration, status and error counters. SerDes interface: This interface is used to transfer/receive 10-bit data to Ser/from Des. It provides10-bit clock for Ser/Des and contains a number of signals used for Ser/Des configuration.Data interface: Parallel interface through which PCS IP receives super frames to be processed andthrough which PCS delivers reconstructed frames received from Des Lanes.
PCS IP Core (HIP500)
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIP500 DS.REV.1.0
30.01.2013.
8B10B_ DEC: This block first performs the framing functionality, aligns the bit-stream received fromthe Des to 8B10B block boundaries. The second function of this block is 10B8B decoding, conver-sion of 10-bit code words into 8 bit words. There are 8 instances of this block, one per lane, denot-ed 8B10B_DEC0 – 8B10B_DEC7. ELB: The external-facing loopback block (ELB) provides per-lane loopback, and per-lane PRBS gen-eration and verification functionality. PRBS polynomial used is PRBS31: 1+x^28+x^31. In case whenneither PRBS nor Loopback is enabled the ELB is transparent for data generated bySF_GEN/8B10B_DEC.ILB: The internal-facing loopback block (ILB) provides PRBS generation and verification on the pay-load, including super-frame alignment and verification of the PRBS sequence. PRBS polynomialused here is PRBS31: 1+x^28+x^31. In case when PRBS is not enabled, the ILB block is transparentfor SF_REC data or data received on RX Data interface.
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Contact Information
HDL Design HouseGolsvortijeva 35,Belgrade, Serbia Phone: +381 11 414 55 55Fax: +381 11 414 55 59Email: [email protected]://www.hdl-dh.com
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Figure 1. PCS architecture diagram
