PCPC addr instr INSTR MEM R1 R2 WR W Data R Data 1 R Data 2 ALU DATA MEM ALU CTRL rs rt op +4 shift...
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P C addr ins tr INSTR MEM R1 R2 WR W Data R Data 1 R Data 2 ALU DATA MEM ALU CTRL r s r t op +4 shift 2 zer o BRANCH CTRL m u x sign extend immed 16 32 A D D A D D Single Cycle Datapath m u x m u x add r w data r data rd
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19-Dec-2015 -
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Transcript of PCPC addr instr INSTR MEM R1 R2 WR W Data R Data 1 R Data 2 ALU DATA MEM ALU CTRL rs rt op +4 shift...
PC addr
instr
INSTR MEM
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
DATA MEM
ALU CTRLALU CTRL
rs
rt
op
+4
shift 2
zero
BRANCH CTRL
mux
sign extendimmed
16 32
ADD
ADD
Single Cycle
Datapath
mux
mux
addr
w data
r datard
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
Multicycle Datapath
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
fetch
decode
execute (1..3)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
CONTROLCONTROL
rs
rt
rd
fctnop shamt
Multicycle with Exception/Interrupt Handling
A
B
w data
immed sign extend
shift 2
+4
IR
MR
zero
alu out
shift 2jump addr
EPC
CAUSE
PC - 4
handler addr
00
01
10
11
to?
overflow
to?
Pipelined Datapath
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
IF ID EX MEM WB
add rd, rt, rs: Fetch
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Instruction Fetch: Load IR, PC = PC + 4 IF Register
Contains IR and PC, and other values
add rd, rt, rs: Decode
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Instruction Decode: Load data1, data2 into A, B (part of ID)
ID register contains A, B, and other values
add rd, rt, rs: Execute
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Execute: sum of A, B into ALUout (part of EX)
add rd, rt, rs: MEM
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
MEM: (no memory access) save ALU result in MEM
add rd, rt, rs: WB
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Write Back: write sum to register rd
sw rt, offset(rs): Fetch
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
sw rt, offset(rs): Decode
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
ID gets rs, rt, and immed+sign ext
sw rt, offset(rs): Execute
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
EX gets rs+offset, and rt
sw rt, offset(rs): MEM
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Write Data Memory [address] with rt value; nothing of interest in WD
sw rt, offset(rs): WB
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Registers not written in this instruction
A program fragment with 6 instructions
1. add r1, r2, r3
2. sw r4, 2232 ( r5 )
3. addi r6, 55
4. lw r7, 1001 (r8)
5. bneq r7, r6, -3
6. add r1, r7, r0
A program fragment with 6 instructions
1. add r1, r2, r3
2. sw r4, 2232 ( r5 )
3. addi r6, 55
4. lw r7, 1001 (r8)
5. slti r7, r6, -3
6. add r1, r7, r0
Six instructions 1,2,3,4,5,6: Step 1
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 1
Six instructions 1,2,3,4,5,6: Step 2
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 2 Decode 1
Six instructions 1,2,3,4,5,6: Step 3
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 3 Decode 2 Execute 1
Six instructions 1,2,3,4,5,6: Step 4
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 4 Decode 3 Execute 2 Mem 1
Six instructions 1,2,3,4,5,6: Step 5
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 5 Decode 4 Execute 3
WB 1 (add)
Mem 2 (sw)
Six instructions 1,2,3,4,5,6: Step 6
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 6 Decode 5Execute 4 Mem 3
(addi)
WB 2 (sw: no write)
Six instructions 1,2,3,4,5,6: Step 7
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Decode 6 Execute 5 Mem 4 (lw)
WB 3 (addi)
Six instructions 1,2,3,4,5,6: Step 8
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Execute 6 Mem 5 (slti)
WB 4 (lw)
Six instructions 1,2,3,4,5,6: Step 9
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Mem 6 (add)
WB 5 (slti)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
add rd, rs, rt
fetch: load ir, pc=pc+4
decode
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
Multicycle Datapath
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
fetch
decode
execute
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
add rd, rs, rt
fetch
decode:load A,B registers
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
add rd, rs, rt
fetch
decode
execute (2 cycles) load alu out; load register
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
bne rs, rt, addr
fetch: load IR, pc=pc+4
decode
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
bne rs, rt, addr
fetch
decode: load A B, aluout = immediate (extendx2)+pc
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
bne rs, rt, addr
fetch:
decode:
execute: (1 cycle) compare A, B (holding rs, rt); if neq, load pc with aluout (holding branch addr)
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
lw rt, offset ( rs)
fetch: load IR, pc=pc+4
decode
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
lw rt, offset ( rs)
fetch
decode: load A B; offset is ready
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
lw rt, offset ( rs)
fetch
decode
execute: (3 cycles): load aluout with addr, load mr with data, load register rt
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
Multicycle Datapath
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
Try these:
sw rt, off(rs)
j addr
andi rd,rs,rt
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
Multicycle Datapath
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
PC addr
instr
INSTR MEM
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
DATA MEM
ALU CTRLALU CTRL
rs
rt
rd
fctn
op
shamt
R-Format: add, slt, sll
PC addr
instr
INSTR MEM
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
DATA MEM
ALU CTRLALU CTRL
rs
rt
op
+4
shift 2
zero
BRANCH CTRL
mux
sign extendimmed
16 32
ADD
ADD
I-Format bne
PC addr
instr
INSTR MEM
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
DATA MEM
ALU CTRLALU CTRL
rs
rt
op
zero
sign extendimmed
16 32
I-Format lw, sw
addr
W Data
mux
R Data
PC addr
instr
INSTR MEM
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
DATA MEM
ALU CTRLALU CTRL
op
+4
shift 2
zero
BRANCH CTRL
mux
ADD
ADD
J-Format
address
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
Multicycle Datapath
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
fetch
decode
execute
