PCIRF_3_2_MOS_1

7/29/2019 PCIRF_3_2_MOS_1

1/21

Agenda

MOS Transistor ModelingThreshold Voltage, VTDC I-V Equations

Body Effect

Subthreshold Region

4

7/29/2019 PCIRF_3_2_MOS_1

2/21

- 5 -

TAMU-474-09 J. Silva-Martinez

MOS Transistor

D

S

BG

P-type transistor

Substrate or well

P+ P+

S G D

P-channel

N

N+

B

Thick oxideThin oxide

Polysilicon (heavily doped)

BASIC IDEA:

SOURCE-DRAIN CURRENT IS

CONTROLLED BY THE

SOURCE-GATE VOLTAGE.

The system is isolated if the

diodes are biased in reverse region

by using the Bulk terminal.

7/29/2019 PCIRF_3_2_MOS_1

3/21

Threshold Voltage, VT

Before a channel forms, the device acts as 2 series caps from theoxide cap and the depletion cap

If VG is increased to a sufficient value the area below the gate isinverted and electrons flow from source to drain

6

[Razavi]

Applying a positive voltage to the gate repels holes in the p-substrate

under the gate, leaving negative ions (depletion region) to mirror thegate charge

7/29/2019 PCIRF_3_2_MOS_1

4/21

ox

oxoxox

subFsidepdep

i

subFF

MS

FFMS

ox

dep

FMST

tCC

NqQQ

nN

qkT

C

QV

=

=

=

++=++=

cap/area,gatetheis

4charge,regiondepletiontheis

lnpotential,Fermitheis

substratesilicontheandgatenpolysilicotheoffunctionsworkebetween thdifferencetheis

222

VT Definition

The threshold voltage, VT,is the voltage at which aninversion layer is formed For an NMOS this is when the

concentration of electrons

equals the concentration ofholes in the p- substrate

7

[Silva]

Note, will be defined later

7/29/2019 PCIRF_3_2_MOS_1

5/21

- 8 -


MOS Transistor

substrate

N+ N+

VS=0VG0

P

P+

BD

S

BG

N-type transistor

+ + + + + + + + + +

Accumulation: Two diodes back to back

D-S current is zero

P+

Substrate

N+ N+

VS=0

VG>0

VD>0

P

P+

B

- - - - - - - - - -

Inversion: Channel is connecting D and S

D-S current is possible

IDS

Under this condition, there are 3 possible

applications:

Subthreshold(extremely low-voltage low-

power applications)

Linear region (voltage controlled resistor,

linear OTAs, multipliers, switches)

Saturation region (Amplifiers)

Quasi free electrons

N+

7/29/2019 PCIRF_3_2_MOS_1

6/21

- 9 -


MOS Transistor

D

S

BG

N-type transistorTriode Region (D-S channel is complete)

In this condition, there are 3 possible

applications:


power applications)




substrate

N+ N+

VS=0VG>0

VD ~ 0

P

P+

B

- - - - - - - - - -

Channel

substrate

N+ N+

VS=0VG>0

VD > 0

P

P+

B

Saturation Region (D-S channel is incomplete)

N-channel

7/29/2019 PCIRF_3_2_MOS_1

7/21

- 10 -


MOS Transistor

N-type transistor

substrate

N+ N+

VS=0VT >VG>0 VD>0

P (NA)

P+

B

Subthreshold (weak inversion)

Mobile carriers

concentration< NA

- - - - - - - -

substrate

N+ N+

VS=0VG>VT

VD>0

P (NA)

P+

B

Saturation (Strong inversion)

Mobile carriers

Concentration> NA

- - - - - - - -

Subthreshold

Linear region

Saturation

VD

S

IDS


power applications)




VGS2

VGS3

VGS1

7/29/2019 PCIRF_3_2_MOS_1

8/21

MOS Equations in Triode Region (Small VDS)

11

[Sedra/Smith]

( )

( )

( )( )

( )

( )

DSDSTGSOXnDS

V

CSTGSOXn

L

DS

nTCSGSOXDS

nn

TCSGSTGC

TGCOXd

d

VVVVL

WCI

xdvxVVVWCdxI

dx

xdvVxVVWCII

dx

xdvxE

VxVVVxV

VxVWCxQ

xQdt

dx

dx

dQ

dt

dQI

DS

=

=

==

==

=

=

===

2

1

))((

))((

:VelocityElectron

)(:VoltageChannel-to-Gate

)()(:DensityChargelIncrementa

)(:DraintoSourcefromCurrent

00

DSII =

n:mobilityElectron

:areagateunitpereCapacitanc

ox

oxox

tC =

7/29/2019 PCIRF_3_2_MOS_1

9/21

Triode or Linear Region

Channel depth and transistor current is a function of the overdrivevoltage, VGS-VT, and VDS Because VDS is small, VGC is roughly constant across channel length

and channel depth is roughly uniform

12

x=0 x=L

VDS

( ) DSDSTnGSOXnDS VVVVCL

WI 5.0=

( ) 00 =V ( )DS

VLV =( )L

xVxVDS

=

( ) ( )L

xVVxVVxVDSGSGSGC

==

( )TnGSox

DS

VVCL

WR

1

For small VDS

[Silva]

7/29/2019 PCIRF_3_2_MOS_1

10/21

- 13 -


MOS Equations in Linear Region

L

W

tox

N+ N+

VDSGNDVGS Drain current: Expression used in SPICE level 1

( ) DSDSTGSOXnD VV5.0VVCL

WI =

W

tox

N+ N+

VDSGNDVGS

Non-linear channel

Linear approximation

VDS

ID

VDSAT

IDSAT

VGS > VT

7/29/2019 PCIRF_3_2_MOS_1

11/21

Triode Region Channel Profile

14

[Sedra/Smith] ( ) ( ) Lx

VVxVVxV DSGSGSGC ==

If VGC is always above VT throughout the channel length, the

transistor current obeys the triode region current equation

7/29/2019 PCIRF_3_2_MOS_1

12/21

Saturation Region Channel Profile

15

[Sedra/Smith]

( ) ( )L

xVVxVVxV DSGSGSGC ==

When VDS VGS-VT=VOV,VGC no longer exceeds VT,

resulting in the channelpinching off and thecurrent saturating to avalue that is no longer afunction of VDS (ideally)

7/29/2019 PCIRF_3_2_MOS_1

13/21

Saturation Region

Channel pinches-off when VDS=VGS-VT and the current saturates

After channel charge goes to 0, the high lateral field sweeps thecarriers to the drain and drops the extra VDS voltage

16

x=0 x=L

VDSsat=VGS-VT

( ) 00 =V ( )DS

VLV =( )L

xVxVDS

=

( ) ( )L

xVVxVVxVDSGSGSGC

==VDS-VDSsat

TnGSDSsatVVV =

[Silva]

( )2

2TnGS

OXn

DSVV

L

WCI =

TnGSDS VVV

DS

DS

TnGSOXnDSV

VVV

L

WCI

=

=

2

7/29/2019 PCIRF_3_2_MOS_1

14/21

NMOS ID VDS Characteristics

17

TNGSOV VVV = [Sedra/Smith]

7/29/2019 PCIRF_3_2_MOS_1

15/21

MOS Large-Signal Output Characteristic

18

[Sedra/Smith]

Note: Vov=VGS-VT

7/29/2019 PCIRF_3_2_MOS_1

16/21

What about the PMOS device?

The current equations for the PMOS device arethe same as the NMOS EXCEPT you swap thecurrent direction and all the voltage polarities

19

( ) DSDSTnGSOXnDS VVVVCL

WI 5.0= ( ) SDSDTpSGOXpSD VVVVC

L

WI 5.0=

( )22

TnGSOXnDS VVCL

WI = ( )2

2TpSGOXpSD VVC

L

WI =

Linear:

Saturation:

NMOS PMOS

NMOS PMOS

[Silva]

7/29/2019 PCIRF_3_2_MOS_1

17/21

PMOS ID VSD Characteristics

20

[Karsilayan]

(Saturation)

TPSGOV VVV =

7/29/2019 PCIRF_3_2_MOS_1

18/21

Body Effect

As VS becomes positive w.r.t.VB, a larger depletion regionforms, which requires a higherVG to form a channel

The net result is that VTincreases due to this bodyeffect

Note, it also works in reverse,as if you increase VB w.r.t. VS,then VT lowers

21

[Razavi] If the body and source potential are

equal, a certain VG=VT0 is required toform an inversion layer

FFMS

ox

dep

FMSTC

QV ++=++= 222 00

21

0

0.4Vto0.3fromrangestypically

2t,coefficieneffectBody

22

ox

subsi

FSBFTT

C

Nq

VVV

=

++=

7/29/2019 PCIRF_3_2_MOS_1

19/21


- 22 -

MOS MODEL: SPICE LEVEL-II

Drain current, Triode region

Drain Current, Saturation region

Threshold voltage (zero bias)

Threshold voltage

KP and (Spice Model)

( ) DSDSTnGSOXnDS VVVVCLW

I 5.0:NMOS =

( )SDSDTpSGOXpSD

VVVVCL

WI 5.0:PMOS =

( )22

:NMOSTnGSOXnDSVVC

L

WI =

( )2

2:PMOSTpSGOXpSD VVCL

WI =

[ ]000

22=

++=SBV

TFSBFTTVVVV

OX

subsi

OXC

NqCKP

2; ==

FFMSTV ++= 22

0

7/29/2019 PCIRF_3_2_MOS_1

20/21

Subthreshold Region

So far we have assumed that ID=0 when VGS

7/29/2019 PCIRF_3_2_MOS_1

21/21

Subthreshold Current & VT Scaling

24

This subthreshold current prevents lowering VT excessively Assuming VT=300mV and has an 80mV subthreshold

slope, then the Ion/Ioff ratio is only on the order of10^(300/80)=5.6e3

Reducing VT to 200mV drops the Ion/Ioffratio to near 316

If we have a large number of off transistors on our chipthese subthreshold currents add up quickly, resulting in

significant power dissipation This is a huge barrier in CMOS technology scaling and one

of the main reasons Vdd scaling has slowed

PCIRF_3_2_MOS_1

Documents

Transcript of PCIRF_3_2_MOS_1