PCIe CEM 4.0 Previews - Welcome to PCI-SIG | PCI-SIG · PCIe® CEM 4.0 Previews Dan Froelich CEM...

PCIe® CEM 4.0 Previews

Dan Froelich

CEM Workgroup Chair

Intel Corporation

PCIe Technology Seminar 2

Disclaimer

The information in this presentation refers to specifications

still in the development process. This presentation reflects

the current thinking of various PCI-SIG® workgroups, but

all material is subject to change before the specifications

are released.

Copyright © 2014, PCI-SIG, All Rights Reserved

PCIe Technology Seminar Copyright © 2014, PCI-SIG, All Rights Reserved 3

Agenda

PCIe® 4.0 CEM Goals

PCIe 4.0 CEM Connector Direction

PCIe 3.0 CEM Simulation Methodology and 4.0 Preview

Summary and Conclusions


PCI Express® 4.0 CEM Goals

Full backwards interoperability with PCIe 1.x, PCIe 2.x, PCIe 3.x

Same channel reach as for PCIe 3.0 with improvements Client: 10-14 inch, one connector

Server: 20 inch, two connectors – requires a Retimer

Minimize required changes to the connectors, card form factors, or material

Minimal changes to the measurement methodologies from those used in the PCIe 3.x specifications

Use eye diagrams (jitter/voltage margin requirements). Minimize additional new requirements.


PCIe Technology Seminar

Minimum 4.0 Target Connector Performance

5

High Degree of Confidence That Backwards Compatible Solutions Possible



4.0 Connector/Card Goals

Mitigate conductor geometry that impairs performance in the PCIe connector at 16GT/s

Preserve full backwards compatibility among combinations of 2.5-5-8-16 GT/s connectors and Add-in Cards (AIC)

Keep the standard thru-hole pinfield, for thru-hole parts

Define a common surface mount connector footprint and related specifications

Build test boards and characterize and correlate models for the proposed performance enablers

Copyright © 2014, PCI-SIG, All Rights Reserved 6


Enabler Impact on Insertion Loss Resonant stubs on single ground traces

Some resonant behavior still present at higher frequency

Stub design should be optimized in simulation



Enabler Impact on Crosstalk

Resonant structures help suppress peak ground resonances by as much as 20dB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Freq [GHz]

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Diffe

ren

tia

l N

EX

T a

nd

FE

XT

Cro

ssta

lk, d

B

NEXT FEXT 96 0Flip Horseshoe Causal

Improved Lane 0↔1

Improved Lane 1↔2

Improved Lane 0↔2

Baseline 1↔2



Connector Enabler Conclusion

These enablers indicate that a thru-hole solution may be feasible with the same motherboard pinoutas 3.0

0.3 CEM references both approaches (improvements to work with existing thru-hole pinoutvs SMT connectors) and ask for feedback on direction

Current plan for 4.0 CEM is to support and specify both thru-hole and SMT connectors for 4.0

Plan to build test boards to obtain lab data for each potential enabler with both through-hole (PTH) and surface mount (SMT) connectors



Signal & Ground Pin Assignment

The pin assignments in the connector are non-uniform

Note that the quantity of ground pins (Black) adjacent to the diff pairs are “Single” or “Double”

The electrical behavior of pairs having “Single” or “Double” grounds differs

Test board experiments target single or double ground, or a combination

Sin

gle

Sin

gle

Sin

gle

Double

Do

ub

le

Sid

eband

Sid

eband

PairTx0

PairTx1

PairTx2



Connector Test Coupon Floorplan

Each x16 connector can fit four 3-pair experiments

Adjacent clusters are separated by three pins

The 11-pin “before notch” region is not used

Each coupon is 4 × 6 pins = 24 ports

Each experiment includes the three different ground configurations

Four 15-pin clusters fit in the x16 connector pinfield.

1 2 3 4

11 pins lie in the“before notch” region



PCIe 4.0 Experiments

On the Add-in Card PCB:

1. Baseline Typical 8GT/s

2. Adjacent ground vias

3. Join the ground edge fingers

4. Narrow the ground fingers

Improves overall insertion loss

Ground finger resistive termination

5. Ground finger resistive termination Suppresses all resonance

6. Place floating subsurface resonant structures beneath ground fingers

Suppresses resonant insertion loss/crosstalk spikes

7. Multi enabler experiments

Baseboard & Connector changes:

1. Surface mount connector

2. Thru Hole with stub

3. Thru Hole with no stub

4. Thru Hole with via stub mitigation Reduces baseboard PCB via resonance



1.30 CHAMFER REGION

4.30

0.70

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

2.00 1.00

Ground traces are 10 mils wide after finger

Ground vias10 mil Drill (0.254mm)20 mil Pad

7.85

4.40

Connector body 2.2mmabove point of contact,

7.85 mm above board edge

2.25

5.60

3.91

Test Layout 1: Baseline

The trace between the via and ground finger is not addressed in the CEM spec

The length, width, and shape of the ground trace has been implementation specific

The ground traces, above the ground finger, may be straight, like here ↗ or hockey-stick, etc.

For this baseline test, use these common PCIe 3.0 edge finger dimensions

2mm long, 0.508mm (20 mil) wide ground trace, as shown

Sin

gle

Sin

gle

Sin

gle

Do

ub

le

Double

Ground traces areunconstrained in spec



Baseboard – Thru-hole, No Via Stub

AIC Baseline cluster. No improvements to card.

FEXT/NEXTspike near 7-8GHz

CHAMFER REGION

0.70

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

2.00 1.00


Ground vias10 mil Drill (0.254mm)18 mil pad



2.25

0.39

TX

4P

TX

4N

GR

OU

ND

2 4 6 8 10 12 14 16 180 20

-25

-20

-15

-10

-5

-30

0

freq, GHz

dB

(S( 1

, 2))

dB

(S( 3

, 4))

dB

(S( 5

, 6))

Differential Deembedded THRU 85 Ohm

1 2 3 4 5 6 7 8 9 10 110 12

-4

-3

-2

-1

-5

0

freq, GHz

dB

(S( 1

, 2))

dB

(S( 3

, 4))

dB

(S( 5

, 6))

m1Differential Deembedded THRU 85 Ohm

m1freq=dB(S(1,2))=-1.168dB(S(3,4))=-1.216dB(S(5,6))=-1.079

8.010GHz

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 190 20

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

0

freq, GHz

dB

(S( 1

, 4))

dB

(S( 1

, 6))

dB

(S( 3

, 6))

dB

(S( 2

, 3))

dB

(S( 2

, 5))

dB

(S( 4

, 5))

m2m6Differential Deembedded FEXT 85 Ohm

m2freq=dB(S(1,4))=-31.946dB(S(1,6))=-34.536dB(S(3,6))=-21.102dB(S(2,3))=-31.599dB(S(2,5))=-41.897dB(S(4,5))=-21.010

7.060GHz


7.410GHz

2 4 6 8 10 12 14 16 180 20

-80

-60

-40

-20

-100

0

freq, GHz

dB

(S( 1

, 3))

dB

(S( 3

, 5))

dB

(S( 1

, 5))

dB

(S( 2

, 4))

dB

(S( 2

, 6))

dB

(S( 4

, 6))

m5Differential Deembedded NEXT 85 Ohm


5.860GHz


Test Layout 2: Adjacent Ground Vias

Test 2a One via per finger Fewest drills

Not joining adjacent grounds

Vias must fall between fingers to permit the escape of signals on the back side

Most vias are reused by the ground fingers on the reverse side of the PCB

Test 2b Two vias per finger More drills, risk of mechanical weakening

Adjacent grounds are joined

Additional vias for backside doubles shown

1mm pitch with 10 mil drills results in 25% reduction in

PCB “web” width (vs. no vias) ↓

1.30

5.60

CHAMFER REGION

4.40

FULL GROUND PLANE

3.45

7.85

RES

ERV

ED

GR

OU

ND

TX0

P

TX0

N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX1

P

TX1

N

TX2

P

TX2

N

GR

OU

ND

GR

OU

ND

GR

OU

ND

0.39

0.70 1.00

1.30

5.60

CHAMFER REGION

4.30

0.70FULL GROUND

PLANE1.00

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PR

ESEN

T

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

0.39

3.91



Test Layout 2: Adjacent Ground Vias

Test 2c One via per finger Fewest drills

Join Adjacent Grounds– But no middle drill

Test 2d Very long ground connection Worst case 6.3mm, taken from real-world layout

Note, most vias are reused by the Rx side grounds on the

reverse side of the PCB

1.30

5.60

CHAMFER REGION

4.30

FULL GROUND PLANE1.00

RE

SER

VE

D

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PR

ESE

NT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

0.39

3.91

0.70

1.30 CHAMFER REGION

4.30

0.70

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX0

P

TX0

N

GR

OU

ND

PR

ESEN

T

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX1

P

TX1

N

TX2

P

TX2

N

GR

OU

ND

GR

OU

ND

GR

OU

ND

6.30

1.00


7.85

4.40



2.25

5.60

3.91

0.39



1.30 CHAMFER REGION

4.30

0.70

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

2.00 1.00



7.85



2.25

5.60

3.91

0.39

GR

OU

ND

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

4.40

1.30 CHAMFER REGION

4.30

0.70

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

2.00 1.00



7.85

4.40



2.25

5.60

3.91

0.39

Test Layout 3: Joined Edge Fingers

Test 3a: Join dual ground pads along their entire 3.9mm length


Test 3b: Join dual grounds along the upper 1.2mm


Baseboard - Thru-hole, No Via Stub

Improved AIC Test

Lower ground

Joined double Gnd

CHAMFER REGION

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

1.00

Ground vias10 mil Drill (0.254mm)18 mil pad



0.39

TX

4P

TX4

N

GR

OU

ND

0.70

FULL GROUND PLANE

Good suppression of FEXT/NEXT

2 4 6 8 10 12 14 16 180 20

-25

-20

-15

-10

-5

-30

0

freq, GHz

dB

(S( 1

, 2))

dB

(S( 3

, 4))

dB

(S( 5

, 6))

Differential Deembedded THRU 85 Ohm

1 2 3 4 5 6 7 8 9 10 110 12

-4

-3

-2

-1

-5

0

freq, GHz

dB

(S( 1

, 2))

dB

(S( 3

, 4))

dB

(S( 5

, 6))

m1Differential Deembedded THRU 85 Ohm

m1freq=dB(S(1,2))=-0.944dB(S(3,4))=-0.941dB(S(5,6))=-0.826

8.010GHz

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 190 20

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

0

freq, GHz

dB

(S( 1

, 4))

dB

(S( 1

, 6))

dB

(S( 3

, 6))

dB

(S( 2

, 3))

dB

(S( 2

, 5))

dB

(S( 4

, 5))

m2m3Differential Deembedded FEXT 85 Ohm


7.060GHz


7.410GHz

2 4 6 8 10 12 14 16 180 20

-80

-60

-40

-20

-100

0

freq, GHz

dB

(S( 1

, 3))

dB

(S( 3

, 5))

dB

(S( 1

, 5))

dB

(S( 2

, 4))

dB

(S( 2

, 6))

dB

(S( 4

, 6))

m6Differential Deembedded NEXT 85 Ohm


5.860GHz


Test Layout 4: Narrow Edge Fingers

The width of the edge fingers contributes a stub capacitance in the AIC

Below the resonant frequency

Fingers are nominally 0.7mm wide, in the baseline

If the fingers are narrowed, the Insertion Loss can be improved

No effect on resonance

Increased risk of zippering with narrow fingers

Test 3a: Narrow all pins to 0.5mm

with 0.5mm spacing

1.30 CHAMFER REGION

4.30

0.50

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

2.00 1.00



7.85



2.25

5.60

3.91

0.39

GR

OU

ND

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

5.60

0.50



Test Layout 5: Resonator

Place a horseshoe shaped resonator beneath the pads on Metal 2 FLOATING

Use this approach for double grounds

This can reduce the resonance in the 8-9GHz region

Alternatively, for some single ground fingers, use the shape below

0.70

2.25

0.40

2.25

0.70

0.70

0.70

0.40



Test Layout 5a: Resonator

Place the resonators as shown beneath the edge fingers

Additional resonator 5b widths will test sensitivity to geometry

1.30 CHAMFER REGION

4.30

0.70

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

2.00 1.00



7.85

4.40



2.25

5.60

3.91

0.39



SMP – Channel Boards

Run live traffic (BERT) experiments using SMP connectors in place of the Terminate-R

Trace lengths designed for ~25 dB of loss at 8 GHz

– Add ~4” of etch on the AIC

– Add ~10” of etch on the baseboard

Length matched

Route Differential

Use thru-hole SMPs, which are mechanically stronger than SMT SMPs

– Ground pins are thru-hole

– Signal is still surface mount, though (no via)



Client Motherboard and adapter

1 PCIe connector

No vias other than connector

Routed as mstrip

Channel length: ~10-14”

Server Motherboard, riser card, and adapter

2 PCIe connectors

Several vias on motherboard

Routed primarily as stripline

Channel length: ~20”

Requires Retimer for 16GT/s

Channel analysis includes corner cases

Seg Description

A MCH PKG (transmitter)

B Break Out

C MB Main 7”

D MB post cap

E Add in card main 3”

F Add in card PKG Break out

G Add in card PKG (receiver)

ACB

DE

G

FTypical Client topology

PCI Express 3.0/4.0 Channel Analysis

2 Connector Server topology

PCIe 4.0 targets support for the same channels and lengths as PCIe 3.0

Longest 2 connector channels will require Retimer



PCIe 4.0 Server Channel Extension with Retimers

AC Cap

Short

Channel

Add In Card

Longer

Channel

Retimer

Root Complex Chip

Baseboard routing <10”


3.0 CEM Simulation Details Channels

Worst case 2 connector 16” server MB

Worst case 1 connecter 10” client MB

4” microstrip Add-in card

TX jitter following base spec limits

Base spec package models for TX and RX packages

Equalization

Adaptive 2-tap (pre/post) TX LE

Reference Equalizer - 1st order Adaptive RX CTLE + 1 Tap DFE

Pass/Fail Decision for End To End (ETE) Simulations

Base Spec RX test stressed eye (25 mV and .3 UI)



PCIe 3.0 CEM Simulation Method Step 1: End to End (E2E) Simulations

Perform E2E simulations

Use target 1 connector and 2 connector solutions

Eye height (EH) and eye width (EW) examined after reference equalizer at eye pad

– CTLE + 1 tap DFE and base spec package structure

– Pass/fail determined by base spec RX test stressed eye

Statistical tools used for all simulations

For each set of MB parameters determine worst case eye across expected add-in card solution space

Repeat with many motherboardsCreate a statistically significant number of MB

descriptions. (Vary channel lengths, Tx

params, etc.)

Various MB descriptions

Sweep add-in card

parameters over

reasonable solution

space



PCIe 3.0 CEM Simulation MethodStep 2: Test Fixture Simulations

Choose a test fixture

2.0 CLB Test Fixture Used For Initial Investigation

CEM spec pathfinding work showed better correlation with worst case E2E results with fixture with package model vs 2.0 CLB

Repeat previous MB simulations with test fixture

Determine an eye mask at compliance Test Point

Find correlation between EH and EW at Test Point vs. E2E results

Use TX presets only to match expected compliance test

Optimize number of False Passes and False FailsText fixture with SMP Connectors to

‘scope (CLB 3.0)

Statistically significant number of MB

Descriptions (same as E2E simulations)



Package Test Fixture Topology 4” test fixture

CEM spec pathfinding work showed better correlation with worst case E2E results with fixture with package model on test fixture

Parameters shown for current CEM 3.0 CLB

4.0 CLB Potential Changes

Package model will change to ~.3/.4 pf Cpad

Trace length could be reduced from 4”

CPAD

.8 pfCPIN

.25 pf

Package Parameters

CPAD = .8 pf

CPIN = 0.25 pf

Len = 1.3”

Z0 = 85 Ohms

T-line defined by

length, Z0, fixed/unit length loss

Source: Intel Corporation

Base Spec RX Package Structure



Interpreting Simulation Results

Passing Results

Failing Results

“False Failures”

“False Passes”




Client Tx E2E to CLB EyeHeight Correlation

E2E threshold at 25.0mV

CLB threshold range

43 mv. No False Passes

27 mv. No False Failures




Server Tx E2E to CLB Eye Height Correlation

E2E threshold at 25mV

CLB threshold range

42 mv. No False Passes

22 mv. No False Failures




CEM TX Limits Test Channels

MB TX Test Channel

– 4” 85 ohm trace + reference RX package

AIC TX Test Channel

– 16” and 2 connectors + reference RX package

CTLE + 1 Tap DFE reference Equalizer

BER E-12 Limits (Same for AIC and MB)

34 mV

.33 UI

BER E-6 (Same for AIC and MB)

46 mV

Informative – for simplified lab measurement use


4.0 direction – BER E -12 Limits of 25 mV and .3 UI

No need for simulation process


Calibrating Stressed Eye: Base Rev 0.5 Direction


16 GT/s PRBS Generator

Combiner Test EquipmentReplica Channel

CEM Connector

Fixed TX EQ

TP1 TP2

Post Processing Scripts:Rx pkg modelBehaviorial CTLE/DFEBehavioral CDR

TP2P

Rj Source

Sj Source

Diff Interfer

ence

CM Interfer

ence

Calibration ChannelEH or EW Adjust

Small EW Adjust

Small EH Adjust

25 mV / .3 UI at E-12 BER


CEM Connector must improve for PCIe 4.0 at 16GT/s Add-in card PCB enablers for existing PTH connector

SMT connectors

Direction to support existing PTH connectors with add-in card improvements and SMT connectors bending connector test board data

Same channel reach as for PCIe 3.0 Client: 14 inch, one connector

Server: 20 inch, two connectors – with a Retimer

Direction to make CEM reference channel same as Base RX stressed eye channel for 4.0 CEM RX call channel/limits match Base RX without need for CEM simulation process

For latest PCIe 4.0 specifications, visit www.pcisig.com

0.3 CEM 4.0

Summary and Conclusions


http://www.pcisig.com/


Thank you for attending the PCIe Technology Seminar.

For more information please go to www.pcisig.com


PCIe CEM 4.0 Previews - Welcome to PCI-SIG | PCI-SIG · PCIe® CEM 4.0 Previews Dan Froelich CEM...

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Transcript of PCIe CEM 4.0 Previews - Welcome to PCI-SIG | PCI-SIG · PCIe® CEM 4.0 Previews Dan Froelich CEM...