PCI Final Presentation 2

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PCI Simulation over Opnet

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Technion - Israel Institute of Technology

Computer Networks Laboratory

Spring 2002

Midterm Presentation



Project Goals Study of the PCI Local-Bus protocol

Learning the various aspects of the OPNET simulator

Design of the basic units in the PCI Architecture

(Initiator, Target, Arbiter) using the OPNET software

Implementation of a Generator unit & Simulation of anoperational PCI bus



PCI Local Bus

Advantages:

PCI stands for P eripheral

C omponent

I nterconnect

Defined by Intel in 1992

32-bit, 33MHz data transfer (64bit, 66MHz

expansion)

Multiplexing - Address/Data Bus,

Command/Byte Enable Bus.

Parity Error Checking.

Flexible Architecture - CPU Independent.

Enables some simultaneous actions(CPU Memory + LAN SCSI Host)

Burst transactions

Supports up to 256 PCI buses (connected by

Bridges)

Supports up to 80 Devises per PCI Bus

plug & play

L AN

E x p an t i onB u s

North

Bridge

L o c al

B u s

S C S I B u s

SouthBridge

Graphics

Accelerator MemoryMemory BusAGP

LAN Adapter

SCSIHBA

Expantion slot

Expantion slot

PCI Bus

P C I s l o t

P C I s l o t

CPU



PCI ArchitectureWe have developed 4 different kind of OPNET nodes:

Master ± Initiates read & write transfer requests and also busrequests to the arbiter as needed.

Slave ± Waits for transfer requests initiated by a master andreplies to the requests which refers to the slave¶s address space.

Arbiter ± The unit which keeps track of transfer requests bydifferent masters and decides which master can start the nexttransfer.

Generator ±Although this unit is not part of the PCI protocol itis necessary in order to drive the system simulation. Thegenerator reads a text file which contains a list of tasks, andtriggers the master. When parity error is discovered during a datatransfer the generator receives an interrupt from its master.



PCI transactions Initiator places the

command and an address

on the bus. The Target that identifies

the address in its addressspace Acknowledges by

asserting DEVSEL signal. Data transfer commences,

when both TRDY &IRDY are asserted.



PCI ArbitrationPCI Arbitration

Initiator requests bus by asserting the Req signal

Arbiter holds a queue of bus requests

Arbiter grants ownership of the bus on a First

Come First Served basis.

Hidden Arbitration ± Arbitration takes place

during the data transfer ± no special PCI cyclesused for the arbitration.



Implementation Flower type State Machine

design.

Address/Data bus is modeled as

a packet in opnet. IRDY, TRDY & FRAME

signals are held as local

attributes of the Arbiter.

DEVSEL, PERR & STOP

signals are asserted using aremote interrupt triggered by the

Target.

Arbiter awakens sleeping master

by remote interrupt.

Master



Difficulties Trying to simulate continuous

and transparent bus data flowand signals on an event

driven simulator ± mightresult in long simulation runtime.

OPNET was not designed for high speed digital systemssimulations.

OPNET stations wereoccupied 95% of work hours.

Solutions Using the ³need to know´

basis - every node receives

information about the bus

signals it needs only when itneeds them.

While everyone (except the

arbiter) sees the packet flow

on the bus.

Scaling ± Downscaling the basic time unit of the

simulator from 1sec to 1nsec.

Implementing the project in

long bursts during

unconventional hours.



Simulations First we fed the two masters two different packet sizes:

Master0 - long burst transfers.

Master1 - short burst transfers.

we tested this

topology with

various bit error

rates.



Write & Write BurstMaster0 - short burst transfers

Number of short bursts 35

Number of long bursts 25

bit error rate = 1e-5

Master1 - long burst transfers



Conclusions

www.comnet.technion.ac.il/~cn7s02

FOR MORE INFO...

PCI simulator operational.

PCI protocol throughput is a tradeoff between

short bursts = large overhead

long bursts = large probability of error per burst. Probability of error in burst is proportional to the

burst length

Arbitration is fair only in the aspect of the

amount of bursts for each master but not in the

aspect of bus time

PCI Final Presentation 2

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