PCI Express-to-Generic Local Bus Bridge Data Book · – PCI to PCI Bridge Architecture...

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Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 0.95 March, 2007 ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book Version 0.95 March 2007 Website www.plxtech.com Technical Support www.plxtech.com/support Phone 800 759-3735 408 774-9060 FAX 408 774-2169 PLX CONFIDENTIAL - NDA REQUIRED CONFIDENTIAL NDA REQUIRED
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Transcript of PCI Express-to-Generic Local Bus Bridge Data Book · – PCI to PCI Bridge Architecture...

  • Copyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95

    March, 2007

    ExpressLane PEX 8311AA

    PCI Express-to-Generic Local Bus Bridge

    Data Book

    Version 0.95

    March 2007

    Website www.plxtech.com

    Technical Support www.plxtech.com/support

    Phone 800 759-3735

    408 774-9060

    FAX 408 774-2169

    PLX CONFIDENTIAL - NDA REQUIREDCONF

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    http://www.plxtech.com/support/http://www.plxtech.com
  • Copyright Information

    Copyright 2005 2007 PLX Technology, Inc. All Rights Reserved. The information in this documentis proprietary to PLX Technology. No part of this document may be reproduced in any form or by anymeans or used to make any derivative work (such as translation, transformation, or adaptation) withoutwritten permission from PLX Technology.

    PLX Technology provides this documentation without warranty, term or condition of any kind, eitherexpress or implied, including, but not limited to, express and implied warranties of merchantability,fitness for a particular purpose, and non-infringement. While the information contained herein isbelieved to be accurate, such information is preliminary, and no representations or warranties ofaccuracy or completeness are made. In no event will PLX Technology be liable for damages arisingdirectly or indirectly from any use of or reliance upon the information contained in this document. PLXTechnology may make improvements or changes in the product(s) and/or the program(s) described inthis documentation at any time.

    PLX Technology retains the right to make changes to this product at any time, without notice. Productsmay have minor variations to this publication, known as errata. PLX Technology assumes no liabilitywhatsoever, including infringement of any patent or copyright, for sale and use of PLX Technologyproducts.

    PLX Technology, the PLX logo, and Data Pipe Architecture are registered trademarks and ExpressLaneis a trademark of PLX Technology, Inc.

    PCI Express is a trademark of the PCI Special Interest Group (PCI-SIG).

    All product names are trademarks, registered trademarks, or servicemarks of their respective owners.

    Order Number: 8311-SIL-DB-P1-0.95

    Data Book PLX Technology, Inc.

    ii ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data BookCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

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  • March, 2007 Revision History

    ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book iiiCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    Revision History

    Version Date Description of Changes

    0.10 October, 2005 Initial data book content for Silicon Revision AA.

    0.50 November, 2005 Yellow Book release Silicon Revision AA.

    0.75 December, 2005 Yellow Book update Silicon Revision AA.

    0.85 December, 2005 Initial Blue Book release, Silicon Revision AA.

    0.90 April, 2006

    Blue Book update.

    Corrected device description, to PCI Express-to-Generic Local Bus Bridge. Rewrote Chapters 1, 2, 3, and 13. Chapter 2 Added missing PMEIN# signal at C16 (was marked as N/C). Chapter 5 Clarified 64-bit addressing limitations. Section 12.1.2 Changed PME references to PME_IN# and PME_OUT#.

    Added PCI Express and Local Configuration Space register clarification.

    Chapter 18 split into two chapters, 18 and 19, and renumbered subsequent chapters. Other changes include: Clarified primary and secondary interface references. Table 18-5 Added MAININDEX/MAINDATA information to

    Main Control Register row. Corrected Endpoint mode Bridge Control register (BRIDGECTL)

    bit 6 description to indicate Local Bus Reset. Added missing, blank and corrupted serial EEPROM-handling information

    to the Serial EEPROM Control register Serial EEPROM Address Width field (EECTL[24:23]) description,

    Chapter 22 (was Chapter 21) Rewrote Section 22.1 and added new Table 22-3 (renumbered all

    subsequent tables). Removed VDDQ references. Removed second paragraph of Section 22.3. Removed (PCI) references from Tables 22-2 and 22-3

    (were Tables 21-1 and 21-2, respectively). Table 22-2 (was Table 21-1) Changed VOUT and Maximum Power

    Consumption values. Table 22-3 (was Table 21-2) Changed VDD2.5 and VIH values.

    Removed Table 21-3. Removed Table 21-5, and moved its new Thetaj-a text and value to the

    beginning of Section 22.5. Table 22-5 (was Table 21-6) Changed VIH maximum value.

    Applied miscellaneous changes and corrections.

    0.95 March, 2007

    Blue Book update.Added M mode globally throughout data book.Applied miscellaneous changes, corrections, and enhancements throughout data book.CO

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    iv ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data BookCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    Preface

    The information contained in this data book is subject to change without notice. This data book will beupdated periodically as new information is made available.

    ScopeThis data book is the primary source of technical documentation describing the features, functions andoperations of the PLX Technology PEX 8311 PCI Express-to-Generic Local Bus Bridge.

    Intended AudienceThis data book is intended for hardware and software engineers developing systems hardware andsoftware for the PEX 8311 device, as well as engineering managers evaluating the PEX 8311 for use intheir designs.

    Supplemental DocumentationThis data book assumes that the reader is familiar with the following documents:

    PLX Technology, Inc.

    870 W Maude Avenue, Sunnyvale, CA 94085 USATel: 800 759-3735 (domestic only) or 408 774-9060, Fax: 408 774-2169, www.plxtech.com

    PEX 8311AA Errata

    The PLX PEX 8311 Toolbox includes other PEX 8311 documentation as well.

    PCI Special Interest Group (PCI-SIG)

    3855 SW 153rd Drive, Beaverton, OR 97006 USA

    Tel: 503 619-0569, Fax: 503 644-6708, www.pcisig.com

    PCI Local Bus Specification, Revision 3.0

    PCI Local Bus Specification, Revision 2.2

    PCI Local Bus Specification, Revision 2.1

    PCI to PCI Bridge Architecture Specification, Revision 1.1

    PCI Bus Power Management Interface Specification, Revision 1.1

    PCI Hot Plug Specification, Revision 1.1

    PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0

    PCI Express Base Specification, Revision 1.0a

    PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0

    PCI Express Card Electromechanical Specification, Revision 1.1

    The Institute of Electrical and Electronics Engineers, Inc.

    445 Hoes Lane, Piscataway, NJ 08854-4141 USA

    Tel: 800 701-4333 (domestic only) or 732 981-0060, Fax: 732 981-9667, www.ieee.org

    IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990

    IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture

    IEEE Standard 1149.1b-1994, Specifications for Vendor-Specific Extensions

    I2O Special Interest Group (I2O SIG)

    www.developer.osdl.org/dev/opendoc/Online/Local/I20/index.html

    Intelligent I/O (I2O) Architecture Specification, Revision 1.5

    Other References

    Advanced Configuration and Power Interface (ACPI) Specification, Revision 2.0

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  • March, 2007 Supplemental Documentation Abbreviations

    ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book vCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    Supplemental Documentation Abbreviations

    Note: In this data book, shortened titles are provided to the previously listed documents. The following table defines these abbreviations.

    Data Assignment Conventions

    Abbreviation Document

    PCI r3.0 PCI Local Bus Specification, Revision 3.0

    PCI r2.2 PCI Local Bus Specification, Revision 2.2

    PCI r2.1 PCI Local Bus Specification, Revision 2.1

    PCI-to-PCI Bridge r1.1 PCI to PCI Bridge Architecture Specification, Revision 1.1

    PCI Power Mgmt. r1.1 PCI Bus Power Management Interface Specification, Revision 1.1

    PCI Hot Plug r1.1 PCI Hot Plug Specification, Revision 1.1

    PCI Standard Hot Plug r1.0PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0

    PCI Express Base 1.0a PCI Express Base Specification, Revision 1.0a

    PCI Express-to-PCI/PCI-X Bridge r1.0

    PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0

    PCI Express CEM 1.1 PCI Express Card Electromechanical Specification, Revision 1.1

    I2O r1.5 Intelligent I/O (I2O) Architecture Specification, Revision 1.5

    IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture

    Data Width PEX 8311 Convention

    Half byte (4 bits) Nibble

    1 byte (8 bits) Byte

    2 bytes (16 bits) Word

    4 bytes (32 bits) DWORD/DWord/Dword

    8 bytes (64 bits) QWORD/QWord/Qword

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    vi ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data BookCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    Terms and Abbreviations

    The following table provides common terms and abbreviations used in this data book. Terms andabbreviations defined in the PCI Express r1.0a are not included in this table.

    Terms and Abbreviations Definition

    # Indicates an Active-Low signal.

    ACK Acknowledge Control Packet. A control packet used by a destination to acknowledge data packet receipt. A signal that acknowledges the signal receipt.

    ADB Allowable Disconnect Boundary.

    Asynchronous Inputs and Outputs can be asynchronous to a clock. Level-sensitive signals.

    BAR Base Address Register.

    CA Completion with Completer Abort status.

    CFG Access initiated by PCI Express Configuration transactions on the primary interface.

    Clock cycle One period of the clock.

    Completer Device addressed by a requester.

    CRS Configuration Retry Status.

    CSR Configuration Status register; Control and Status register; Command and Status register.

    DACDual Address cycle. A PCI Express transaction wherein a 64-bit address is transferred across a 32-bit data path in two Clock cycles.

    Destination Bus Target of a transaction that crosses a bridge is said to reside on the destination bus.

    DLLPData Link Layer Packet (originates at the Data Link Layer); can contain Flow Control (FCx DLLPs) acknowledge packets (ACK and NAK DLLPs); and power management (PMx DLLPs).

    DMDirect Master. A type of transfer that originates from an external Local Bus Master and addresses a device in PCI Express Space.

    DMA Direct Memory Access. Method of transferring data between a device and main memory, without CPU intervention.

    Downstream Transactions that are forwarded from the primary interface to the secondary interface of a bridge are said to be flowing downstream.

    DSDirect Slave. A type of transfer that originates from PCI Express Space and addresses a device on the Local Bus.

    ECRC End-to-end Cyclic Redundancy Check (CRC)

    EE Access initiated by the Serial EEPROM Controller during initialization.

    Endpoint mode The primary interface is the PCI Express interface.The secondary interface is the Local Bus interface.

    Endpoints

    Devices, other than the Root Complex and switches, that are requesters or completers of PCI Express transactions, as follows:

    Endpoints can be PCI Express endpoints or Conventional PCI endpoints. Conventional PCI endpoints can support I/O and Locked transaction

    semantics. PCI Express endpoints do not support I/O nor Locked transaction semantics.

    FCPFlow Control Packet devices on each link exchange FCPs, which carry header and data payload credit information for one of three packet types Posted requests, Non-Posted requests, and Completions.

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  • March, 2007 Terms and Abbreviations

    ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book viiCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    HostComputer that provides services to computers that connect to it on a network. Considered in charge of the other devices connected to the bus.

    I CMOS Input.

    I/O CMOS Bi-Directional Input/Output.

    JTAG Joint Test Action Group

    Lane A PCI Express physical data link consisting of a differential signal pair in each direction.

    Layers

    PCI Express defines three layers: Transaction Layer The primary function of the Transaction Layer is

    TLP assembly and disassembly. The major components of a transaction layer packet (TLP) are Header, Data Payload, and an optional Digest field.

    Data Link Layer The primary task of the Data Link Layer is to provide link management and data integrity, including error detection and correction. This layer defines the data control for PCI Express.

    Physical Layer The primary value to users is that this layer appears to the upper layers as PCI. It connects the lower protocols to the upper layers.

    LCPU Local Bus Central Processing Unit (Local Bus Intelligent Device).

    LCS Local Configuration Space.

    Local Bus Interface that provides an interconnect of other components to a PLX device.

    Local Bus Modes

    The PEX 8311 supports three Local Bus modes C, J, and M: C Non-Multiplexed Local Bus interface based on 80960CX

    Processor Protocol J Multiplexed Local Bus interface based on 80960JX RISC

    Processor Protocol M TBA

    Local Bus Master Local Bus device that initiates transfers.

    Local Bus Slave (Target) Bus device that responses to Local Bus Master-initiated transactions.

    Local Configuration Space (LCS)

    The register set used to configure and control operations on the PEX 8311 Local Bus.

    LTSSM Link Training and Status State Machine.

    MMPCI Express Configuration Space (PECS) Register access initiated by PCI Express Memory transactions on the primary or secondary interface, using the address range defined by the PECS_PCIBASE0 register.

    MSI Message Signaled Interrupt.

    MWI Memory Write and Invalidate.

    NAK Negative Acknowledge.

    NMI Non-Maskable Interrupt the highest-priority interrupt recognized.

    Non-Posted TransactionMemory Read, I/O Read or Write, or Configuration Read or Write that returns a completion to the master.

    NS No Snoop.

    O CMOS Output.

    OD Open Drain Output.

    Originating Bus Master of a transaction that crosses a bridge is said to reside on the originating bus.

    Packet Types

    There are three packet types: TLP, Transaction Layer Packet DLLP, Data Link Layer Packet PLP, Physical Layer Packet

    Terms and Abbreviations Definition

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    PCIPeripheral Component Interconnect. The original 32/64-bit parallel interconnect standard, defined in the PCI r2.2.When listed in the signal tables, indicates PCI compliance.

    PCI Express Configuration Space (PECS)

    The register set used to initialize, enumerate, and operate the PEX 8311s PCI Express interface.

    PCI Express Requester Generates a Request packet, thereby initiating a transaction on the PCI Express interface.

    PCI Express Target Returns data and/or completions on the PCI Express interface, to the Requester.

    PCI Express Transaction Read, write, read burst, or write burst operation on the PCI Express interface. Includes an Address phase, followed by one or more Data phases.

    PCI Express Transfer During a transfer, data is moved from the source to the destination on the PCI Express interface or Local Bus.

    PECS PCI Express Configuration Space.

    Port

    Interface between a PCI Express component and the link. Consists of transmitters and receivers, as follows:

    An ingress port receives a packet. An egress port transmits a packet. A link is a physical connection between two devices that consists of xN

    lanes. An x1 link consists of one Transmit and one Receive signal, wherein each

    signal is a differential pair. This is one lane. There are four lines or signals in an x1 link.

    Posted Transaction Memory Write that does not return a completion to the master.

    Preempt Ongoing transaction is interrupted to perform another transaction.

    Primary Interface Interface closest to the PCI Express Root Complex (Endpoint mode) or the Local host CPU (Root Complex mode).

    PU Signal is internally pulled up.

    QoS Quality of Service.

    RC Root Complex.

    RCB Read Boundary Completion.

    Request packet

    A Non-Posted Request packet transmitted by a requester contains a completion packet returned by the associated completer.A Posted Request packet transmitted by a requester does not contain a completion packet returned by the completer.

    Terms and Abbreviations Definition

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    ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book ixCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    RequesterDevice that originates a transaction or places a transaction sequence into the PCI Express fabric.

    RO Relaxed Ordering.

    RoHS Restrictions on the use of certain Hazardous Substances (RoHS) Directive.

    Root ComplexDenotes the device that connects the CPU and memory subsystem to the PCI Express fabric. It can support one or more PCI Express ports.

    Root Complex Mode The primary interface is the Local Bus interface.The secondary interface is the PCI Express interface.

    RX Received Packet.

    SC Successful Completion.

    Secondary InterfaceThe interface farthest from the PCI Express Root Complex (Endpoint mode) or the Local host CPU (Root Complex mode).

    SPI Serial Peripheral Interface

    STRAPStrapping pads (such as, BAR0ENB#, IDDQN#, MODE[1:0], and USERi) must be connected to H or L on the board.

    STS Sustained Three-State Output, Driven High for One CLK before Float.

    Switch Device that appears to software as two or more logical bridges.

    TAP Test Access Port.

    TC Traffic Class.

    TLP Translation Layer Packet.

    TP Totem Pole.

    TS Three-State Bi-Directional.

    TX Transmitted Packet.

    Upstream Transactions that are forwarded from the secondary interface to the primary interface of a bridge are said to be flowing upstream.

    UR Unsupported request.

    VC Virtual Channel.

    Terms and Abbreviations Definition

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    x ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data BookCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    Data Book Notations and Conventions

    Notation / Convention Description

    Blue text

    Indicates that the text is hyperlinked to its description elsewhere in the data book. Left-click the blue text to learn more about the hyperlinked information. This format is often used for register names, register bit and field names, register offsets, chapter and section titles, figures, and tables.

    XXXp0 The lowercase p = positive or n = negative suffix indicates the differential pair of signal, which are always used together.

    # = Active-Low signals Unless specified otherwise, Active-Low signals are identified by a # appended to the term (for example, PERST#).

    Program/code samplesMonospace font (program or code samples) is used to identify code samples or programming references. These code samples are case-sensitive, unless specified otherwise.

    command_done Interrupt format.

    Command/Status Register names.

    Parity Error Detected Register parameter [field] or control function.

    Upper Base Address[31:16] Specific Function in 32-bit register bounded by bits [31:16].

    Number multipliers

    k = 1,000 (103) is generally used with frequency response.

    K = 1,024 (210) is used for memory size references.KB = 1,024 bytes.M = meg.

    = 1,000,000 when referring to frequency (decimal notation)= 1,048,576 when referring to memory sizes (binary notation)

    1Fhh = suffix which identifies hex values.Each prefix term is equivalent to a 4-bit binary value (nibble).Legal prefix terms are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F.

    1010b b = suffix which identifies binary notation (for example, 01b, 010b, 1010b, and so forth). Not used with single-digit values of 0 or 1.

    0 through 9 Decimal numbers, or single binary numbers.

    byte Eight bits abbreviated to B (for example, 4B = 4 bytes)

    LSB Least-Significant Byte.

    lsb Least-significant bit.

    MSB Most-Significant Byte.

    msb Most-significant bit.

    DWord DWord (32 bits) is the primary register size in the PEX 8311.

    Reserved Do not modify reserved bits and words. Unless specified otherwise, these bits read as 0 and must be written as 0.CONF

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  • ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book xiCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    Contents

    Chapter 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

    1.2.1 PCI Express Endpoint Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.2.2 High-Speed Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

    1.2.2.1 Direct Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.2.2.1.1 Direct Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.2.2.1.2 Direct Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

    1.2.2.2 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.2.2.2.1 Block DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.2.2.2.2 Scatter/Gather DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.2.2.2.3 Hardware DMA Controls EOT and Demand Mode . . . . . . . . . . . . 10

    1.2.3 Intelligent Messaging Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.2.4 Register Compatibility with PCI 9x56 I/O Accelerators . . . . . . . . . . . . . . . . . . . 101.2.5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

    1.2.5.1 High-Performance PCI Express Endpoint Boards . . . . . . . . . . . . . . . . . . . 111.2.5.2 High-Performance Embedded Root Complex Designs . . . . . . . . . . . . . . . 121.2.5.3 High-Performance Motorola MPC850 and MPC860

    PowerQUICC Designs M Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.2.6 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141.2.7 Messaging Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151.2.8 Root Complex Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151.2.9 Electrical/Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.2.10 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

    1.3 Compatibility with Other PLX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.3.1 Ball Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.3.2 Register Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

    Chapter 2 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.2 Ball Description Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.3 PCI Express Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

    2.3.1 PCI Express Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.3.1.1 PCI Express Layout and Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

    2.3.2 PCI Express Configuration Space Serial EEPROM Support Signals . . . . . . . . 192.4 Local Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

    2.4.1 Local Bus Signal Pull-Up and Pull-Down Resistor Requirements . . . . . . . . . . . 212.4.2 Local Bus Interface C Mode Signals (Non-Multiplexed) . . . . . . . . . . . . . . . . . . 252.4.3 Local Bus Interface J Mode Signals (Multiplexed) . . . . . . . . . . . . . . . . . . . . . . 312.4.4 Local Bus Interface M Mode Signals (Non-Multiplexed) . . . . . . . . . . . . . . . . . . 372.4.5 Local Configuration Space Serial EEPROM Interface Signals . . . . . . . . . . . . . 42

    2.5 Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432.6 JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442.7 Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452.8 No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462.9 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462.10 Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

    2.10.1 Ball Assignments by Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482.11 PEX 8311 Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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    Chapter 3 Reset Operation and Initialization Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .593.1 Endpoint Mode Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

    3.1.1 Full Device Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.1.1.1 PCI Express Reset PERST# Input (Hard Reset) . . . . . . . . . . . . . . . . . . . . 603.1.1.2 Link Training and Status State Machine (LTSSM) Hot Reset . . . . . . . . . . 613.1.1.3 Primary Reset Due to Data Link Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.1.1.4 PCI Express Configuration Space Power Management Reset . . . . . . . . . 61

    3.1.2 Local Bus Bridge Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.1.2.1 Local Bus Bridge Full Reset by way of PECS Bridge Control Register . . . 623.1.2.2 Local Bus Bridge Local Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633.1.2.3 Local Configuration Space Power Management Reset . . . . . . . . . . . . . . . 63

    3.2 Root Complex Mode Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643.2.1 Local Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.2.2 PCI Express Bridge Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.2.3 PCI Express Hot Reset by way of PECS Bridge Control Register . . . . . . . . . . 663.2.4 PCI Express Configuration Space Power Management Reset . . . . . . . . . . . . . 66

    3.3 Initialization Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.3.1 PCI Express Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.3.2 Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

    Chapter 4 Serial EEPROM Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .694.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694.2 PCI Express Configuration Space Serial EEPROM Interface

    (SPI-Compatible Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694.2.1 Serial EEPROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704.2.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724.2.3 Serial EEPROM Random Read/Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . 73

    4.2.3.1 Serial EEPROM Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734.2.3.2 Serial EEPROM Low-Level Access Routines . . . . . . . . . . . . . . . . . . . . . . . 734.2.3.3 Serial EEPROM Read Status Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744.2.3.4 Serial EEPROM Write Data Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744.2.3.5 Serial EEPROM Read Data Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

    4.3 Local Configuration Space Serial EEPROM Interface(Micro-Wire-Compatible Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

    4.3.1 PEX 8311 Initialization from Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . 764.3.2 Local Initialization and PCI Express Interface Behavior . . . . . . . . . . . . . . . . . . 78

    4.3.2.1 Long Serial EEPROM Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.3.2.2 Extra Long Serial EEPROM Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

    4.3.3 Serial EEPROM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824.3.4 Serial EEPROM Initialization Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 83

    Chapter 5 Local Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .855.1 Local Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

    5.1.1 Local Bus Arbitration and BREQi C and J Modes . . . . . . . . . . . . . . . . . . . . . 865.1.1.1 Local Bus Arbitration Timing Diagram C and J Modes . . . . . . . . . . . . . . 87

    5.1.2 Local Bus Arbitration M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885.1.2.1 Local Bus Arbitration Timing Diagram M Mode . . . . . . . . . . . . . . . . . . . . 88

    5.2 Big Endian/Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895.2.1 PCI Express Data Bits Mapping onto Local Bus . . . . . . . . . . . . . . . . . . . . . . . . 895.2.2 Local Bus Big/Little Endian Mode Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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    Chapter 6 C and J Modes Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976.2 Recovery States (J Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976.3 Wait State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

    6.3.1 Wait State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986.3.2 Local Bus Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

    6.4 C and J Modes Functional Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006.4.1 Configuration Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

    6.5 C Mode Functional Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066.5.1 C Mode Direct Master Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066.5.2 C Mode Direct Slave Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1116.5.3 C Mode DMA Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

    6.6 J Mode Functional Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326.6.1 J Mode Direct Master Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326.6.2 J Mode Direct Slave Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366.6.3 J Mode DMA Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

    Chapter 7 M Mode Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597.2 Wait State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

    7.2.1 Local Bus Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

    7.3.1 Adapter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617.3.1.1 PCI Bus RST# Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617.3.1.2 JTAG Reset TRST# Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617.3.1.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627.3.1.4 Power Management Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

    7.3.2 Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637.3.2.1 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637.3.2.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637.3.2.3 Power Management Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

    7.4 Direct Data Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647.4.1 Direct Master Operation (Local Master-to-PCI Slave) . . . . . . . . . . . . . . . . . . . 164

    7.4.1.1 Direct Master PCI Dual Address Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . 1647.5 M Mode Functional Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

    7.5.1 Configuration Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667.5.2 M Mode Direct Master Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707.5.3 M Mode Direct Slave Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747.5.4 M Mode DMA Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

    Chapter 8 PCI Express Bridge Transaction Forwarding . . . . . . . . . . . . . . . . . . . . . . . . 1978.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1978.2 Endpoint Configuration Space Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1988.3 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

    8.3.1 Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1998.3.2 I/O Base, Space Base, Range, and Limit Registers . . . . . . . . . . . . . . . . . . . . 200

    8.3.2.1 PECS I/O Base, Space Base, Range, and Limit Registers . . . . . . . . . . . 2008.3.2.2 LCS I/O Base, Space Base, Range, and Limit Registers . . . . . . . . . . . . . 2018.3.2.3 I/O Forwarding Illustrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

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    8.4 Memory-Mapped I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2048.4.1 Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2048.4.2 Memory-Mapped I/O Transaction Forwarding Control Registers . . . . . . . . . . 205

    8.4.2.1 PECS Memory-Mapped I/O Transaction ForwardingControl Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

    8.4.2.2 LCS Memory-Mapped I/O Transaction ForwardingControl Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

    8.4.2.3 Memory-Mapped I/O Forwarding Illustrations . . . . . . . . . . . . . . . . . . . . . 2088.5 Prefetchable Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

    8.5.1 Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2098.5.2 Prefetchable Memory Base and Limit Registers . . . . . . . . . . . . . . . . . . . . . . . 209

    8.5.2.1 PECS Prefetchable Memory Base and Limit Registers . . . . . . . . . . . . . . 2098.5.2.2 LCS Prefetchable Memory Base and Limit Registers . . . . . . . . . . . . . . . 2108.5.2.3 Memory-Mapped I/O and Prefetchable Memory

    Forwarding Illustrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2128.5.3 64-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

    8.5.3.1 Endpoint Mode 64-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2148.5.3.2 Root Complex Mode 64-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . 214

    Chapter 9 Direct Data Transfer Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2179.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

    9.1.1 Dummy Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2179.1.1.1 Dummy Cycles C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2179.1.1.2 Dummy Cycles M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

    9.2 Direct Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2179.2.1 Direct Master Memory and I/O Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2199.2.2 Direct Master FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2199.2.3 Direct Master Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

    9.2.3.1 Direct Master Memory Access C and J Modes . . . . . . . . . . . . . . . . . . . 2229.2.3.1.1 Direct Master Command Codes to PCI Express Address Spaces C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2239.2.3.1.2 Direct Master Writes C and J Modes . . . . . . . . . . . . . . . . . . . . . 2239.2.3.1.3 Direct Master Reads C and J Modes . . . . . . . . . . . . . . . . . . . . . 224

    9.2.3.2 Direct Master Memory Access M Mode . . . . . . . . . . . . . . . . . . . . . . . . . 2259.2.3.2.1 Direct Master Writes M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2259.2.3.2.2 Direct Master Reads M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

    9.2.4 Direct Master I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2279.2.4.1 Direct Master I/O C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2279.2.4.2 Direct Master I/O M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

    9.2.5 Direct Master Delayed Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2289.2.6 Direct Master Delayed Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

    9.2.6.1 Direct Master Delayed Read Mode C and J Modes . . . . . . . . . . . . . . . 2289.2.6.2 Direct Master Delayed Read Mode M Mode . . . . . . . . . . . . . . . . . . . . . 228

    9.2.7 Direct Master Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299.2.8 Direct Master PCI Express Long Address Format . . . . . . . . . . . . . . . . . . . . . . 2319.2.9 Internal PCI Bus Master/Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

    9.2.9.1 Internal PCI Bus Master/Target Abort C and J Modes . . . . . . . . . . . . . 2329.2.9.2 Internal PCI Bus Master/Target Abort M Mode . . . . . . . . . . . . . . . . . . . 232

    9.2.10 Direct Master Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . 2339.2.11 Direct Master Write FIFO Programmable Almost Full, DMPAF Flag

    C and J Modes Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2339.2.12 RETRY# Capability M Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2349.2.13 IDMA Operation M Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2349.2.14 SDMA Operation M Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

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    9.3 Direct Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2359.3.1 Direct Slave Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

    9.3.1.1 Direct Slave Writes C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2369.3.1.2 Direct Slave Writes M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2379.3.1.3 Dummy Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

    9.3.1.3.1 Dummy Cycles C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . 2389.3.1.3.2 Dummy Cycles M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

    9.3.2 Direct Slave Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2399.3.2.1 Direct Slave Reads C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 2409.3.2.2 Direct Slave Reads M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

    9.3.3 Direct Slave Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2429.3.4 PCI Compliance Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

    9.3.4.1 Direct Slave Delayed Read Mode C and J Modes . . . . . . . . . . . . . . . . 2429.3.4.2 Direct Slave Delayed Read Mode M Mode . . . . . . . . . . . . . . . . . . . . . . 2439.3.4.3 215 Internal Clock Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2439.3.4.4 PCI r2.2 16- and 8-Clock Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

    9.3.5 Direct Slave Delayed Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2449.3.5.1 Direct Slave Delayed Write Mode C and J Modes . . . . . . . . . . . . . . . . 2449.3.5.2 Direct Slave Delayed Write Mode M Mode . . . . . . . . . . . . . . . . . . . . . . 244

    9.3.6 Direct Slave Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2449.3.7 Direct Slave Local Bus READY# Timeout Mode C and J Modes Only . . . . 2459.3.8 Direct Slave Local Bus TA# Timeout Mode M Mode Only . . . . . . . . . . . . . . 2469.3.9 Direct Slave Transfer Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2479.3.10 Direct Slave PCI Express-to-Local Address Mapping . . . . . . . . . . . . . . . . . . 248

    9.3.10.1 Direct Slave Local Bus Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2489.3.10.2 Direct Slave PCI Express Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 2499.3.10.3 Direct Slave PCI Express Initialization Example . . . . . . . . . . . . . . . . . . 2509.3.10.4 Direct Slave Byte Enables C and J Modes Only . . . . . . . . . . . . . . . . . 2509.3.10.5 Direct Slave Transfer Size M Mode Only . . . . . . . . . . . . . . . . . . . . . . 251

    9.3.11 Direct Slave Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2529.3.11.1 Direct Slave Priority C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 2529.3.11.2 Direct Slave Priority M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

    9.3.12 Local Bus Direct Slave Data Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . 2539.3.12.1 Local Bus Direct Slave Data Transfer Modes C and J Modes . . . . . . 2539.3.12.2 Local Bus Direct Slave Data Transfer Modes M Mode . . . . . . . . . . . . 2549.3.12.3 Single Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

    9.3.12.3.1 Single Cycle Mode C and J Modes . . . . . . . . . . . . . . . . . . . . . 2559.3.12.3.2 Single Cycle Mode M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2559.3.12.3.3 Partial Data Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

    9.3.12.4 Burst-4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2559.3.12.4.1 Burst-4 Mode C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 2559.3.12.4.2 Burst-4 Mode M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2569.3.12.4.3 Partial Data (

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    xvi ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data BookCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    9.4 Deadlock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599.4.1 Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

    9.4.1.1 Backoff C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2609.4.1.2 Backoff M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2619.4.1.3 Software/Hardware Solution for Systems without

    Backoff Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2619.4.1.4 Preempt Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2629.4.1.5 Software Solutions to Deadlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

    9.5 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2639.5.1 Dual Address Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

    9.5.1.1 Dual Address Cycles C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 2649.5.1.2 Dual Address Cycles M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

    9.5.2 Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2659.5.3 DMA PCI Express Long Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2659.5.4 Block DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

    9.5.4.1 Block DMA Mode PCI Express Dual Address Cycles . . . . . . . . . . . . . . . 2709.5.5 Scatter/Gather DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

    9.5.5.1 Scatter/Gather DMA PCI Express Long Address Format . . . . . . . . . . . . . 2739.5.5.2 DMA Clear Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2759.5.5.3 Ring Management DMA (Valid Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

    9.5.6 DMA Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2779.5.7 DMA Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2779.5.8 DMA Channel Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2789.5.9 DMA Channel x Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2789.5.10 DMA Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2799.5.11 DMA Local Bus Error Condition M Mode Only . . . . . . . . . . . . . . . . . . . . . . 2819.5.12 DMA Unaligned Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2819.5.13 Demand DMA Mode, Channel x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

    9.5.13.1 Demand DMA Mode, Channel x C and J Modes . . . . . . . . . . . . . . . . . 2829.5.13.2 Demand DMA Mode, Channel x M Mode . . . . . . . . . . . . . . . . . . . . . . 2849.5.13.3 Fast Terminate Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

    9.5.13.3.1 Fast Terminate Mode Operation C and J Modes . . . . . . . . . . . 2869.5.13.3.2 Fast Terminate Mode Operation M Mode . . . . . . . . . . . . . . . . . 287

    9.5.13.4 Slow Terminate Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2879.5.13.4.1 Slow Terminate Mode Operation C and J Modes . . . . . . . . . . . 2879.5.13.4.2 Slow Terminate Mode Operation M Mode . . . . . . . . . . . . . . . . 288

    9.5.14 End of Transfer (EOT#) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2899.5.14.1 End of Transfer (EOT#) Input C and J Modes . . . . . . . . . . . . . . . . . . . 2899.5.14.2 End of Transfer (EOT#) Input M Mode . . . . . . . . . . . . . . . . . . . . . . . . 290

    9.5.15 DMA Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2919.5.15.1 DMA Arbitration C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2919.5.15.2 DMA Arbitration M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

    9.5.16 Local Bus DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2929.5.16.1 Local Bus DMA Priority C and J Modes . . . . . . . . . . . . . . . . . . . . . . . 2929.5.16.2 Local Bus DMA Priority M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

    9.5.17 Local Bus Latency and Pause Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2949.5.17.1 Local Bus Latency and Pause Timers C and J Modes . . . . . . . . . . . . 2949.5.17.2 Local Bus Latency and Pause Timers M Mode . . . . . . . . . . . . . . . . . . 294

    9.5.18 DMA FIFO Programmable Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2959.5.19 DMA Internal Interface Master/Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . 2969.5.20 Local Bus DMA Data Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

    9.5.20.1 Local Bus DMA Data Transfer Modes C and J Modes . . . . . . . . . . . . 2989.5.20.2 Local Bus DMA Data Transfer Modes M Mode . . . . . . . . . . . . . . . . . . 299

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    ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book xviiCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    9.5.20.3 Single Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3009.5.20.3.1 Single Cycle Mode C and J Modes . . . . . . . . . . . . . . . . . . . . . 3009.5.20.3.2 Single Cycle Mode M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 3009.5.20.3.3 Partial Data Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

    9.5.20.4 Burst-4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3019.5.20.4.1 Burst-4 Mode C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 3019.5.20.4.2 Burst-4 Mode M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3019.5.20.4.3 Partial Data (

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    xviii ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data BookCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    11.1.2 Local Bus Originating Interface (Internal to PCI Express) . . . . . . . . . . . . . . . 32511.1.2.1 Received Internal Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

    11.1.2.1.1 Uncorrectable Data Error on Non-Posted Write . . . . . . . . . . . . . 32611.1.2.1.2 Uncorrectable Data Error on Posted Write . . . . . . . . . . . . . . . . . 32611.1.2.1.3 Uncorrectable Data Error on Internal

    Delayed Read Completions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32711.1.2.1.4 Uncorrectable Address Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

    11.1.2.2 Unsupported Request (UR) Completion Status . . . . . . . . . . . . . . . . . . . 32811.1.2.2.1 Master Abort Mode Bit Cleared . . . . . . . . . . . . . . . . . . . . . . . . . . 32811.1.2.2.2 Master Abort Mode Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

    11.1.2.3 Completer Abort (CA) Completion Status . . . . . . . . . . . . . . . . . . . . . . . . 32811.1.3 Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

    11.1.3.1 PCI Express Completion Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . 32911.1.3.2 Internal PCI Bus Delayed Transaction Timeout Errors . . . . . . . . . . . . . . 330

    11.1.4 Other Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33011.2 Root Complex Mode Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

    11.2.1 PCI Express Originating Interface (PCI Express-to-Local Bus) . . . . . . . . . . . 33111.2.1.1 Received Poisoned TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33211.2.1.2 Internal Uncorrectable Data Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

    11.2.1.2.1 Immediate Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33311.2.1.2.2 Non-Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33311.2.1.2.3 Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

    11.2.1.3 Internal Address Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33411.2.1.4 Internal Master Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . . 33411.2.1.5 Internal Master Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . . 33411.2.1.6 Internal Target Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . . 33411.2.1.7 Internal Target Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . . 33511.2.1.8 Internal Retry Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . . . 33511.2.1.9 Internal Retry Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . . . 335

    11.2.2 Local Originating Interface (Local-to-PCI Express) . . . . . . . . . . . . . . . . . . . . 33611.2.2.1 Received Internal Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

    11.2.2.1.1 Uncorrectable Data Error on Non-Posted Write . . . . . . . . . . . . . 33811.2.2.1.2 Uncorrectable Data Error on Posted Write . . . . . . . . . . . . . . . . . 33811.2.2.1.3 Uncorrectable Data Error on Internal

    Delayed Read Completions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33811.2.2.1.4 Uncorrectable Address Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33911.2.2.1.5 Internal Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

    11.2.2.2 Unsupported Request (UR) Completion Status . . . . . . . . . . . . . . . . . . . 34011.2.2.2.1 Master Abort Mode Bit Cleared . . . . . . . . . . . . . . . . . . . . . . . . . . 34011.2.2.2.2 Master Abort Mode Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

    11.2.2.3 Completer Abort (CA) Completion Status . . . . . . . . . . . . . . . . . . . . . . . . 34011.2.3 Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

    11.2.3.1 PCI Delayed Transaction Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . 34111.2.3.2 Internal Delayed Transaction Timeout Errors . . . . . . . . . . . . . . . . . . . . . 341

    11.2.4 Other Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34111.2.4.1 Other Errors C and J Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34111.2.4.2 Other Errors M Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

    11.2.5 PCI Express Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

    CONF

    IDEN

    TIAL

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  • March, 2007 PLX Technology, Inc.

    ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book xixCopyright 2007 by PLX Technology, Inc. All Rights Reserved Version 0.95 PLX CONFIDENTIAL - NDA REQUIRED

    Chapter 12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34312.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34312.2 Endpoint Mode PCI Express Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34612.3 Endpoint Mode Local Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

    12.3.1 Local Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34612.3.1.1 Local Configuration Space Mailbox Register Interrupts . . . . . . . . . . . . . 34712.3.1.2 Doorbell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

    12.3.1.2.1 Local-to-PCI Express Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 34812.3.1.2.2 PCI Express-to-Local Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 348

    12.3.1.3 Internal Master/Target Abort Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 34912.3.2 PCI Express Bridge Internally Generated Interrupts . . . . . . . . . . . . . . . . . . . 349

    12.3.2.1 PCI Express Configuration Space Mailbox Register Interrupts . . . . . . . 34912.4 PCI Express Interrupt Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

    12.4.1 Virtual Wire Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35012.4.1.1 Virtual INTx Wire Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

    12.4.2 Message Signaled Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35112.4.2.1 PCI Express MSI Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

    12.4.2.1.1 MSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35112.4.3 Local Interrupt Output (LINTo#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

    12.4.3.1 Additional LINTo# Interrupts M Mode Only . . . . . . . . . . . . . . . . . . . . . 35212.4.4 Local Bus System Error, LSERR# (Local NMI) C and J Modes Only . . . . 35312.4.5 Built-In Self-Test Interrupt (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35312.4.6 DMA Channel x Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

    12.5 Root Complex Mode PCI Express Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35412.5.1 Local Interrupt Output (LINTo#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

    12.5.1.1 Internal INTA# Wire Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35512.5.1.2 Message Signaled Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

    12.5.2 PCI Express Configuration Space Mailbox Register Interrupts . . . . . . . . . . . 35612.5.3 Local Configuration Space Mailbox Register Interrupts . . . . . . . . . . . . . . . . 35612.5.4 Doorbell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

    12.5.4.1 Local-to-PCI Express Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35712.5.4.1.1 Local-to-PCI Express Interrupt C and J Modes . . . . . . . . . . . . 35712.5.4.1.2 Local-to-PCI Express Interrupt M Mode . . . . . . . . . . . . . . . . . . 357

    12.5.4.2 PCI Express-to-Local Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35712.5.5 DMA Channel x Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35812.5.6 Local Interrupt Input (LINTi#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

    12.6 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35912.6.1 M Mode Local Bus TEA# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35912.6.2 M Mode PCI SERR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

    Chapter 13 Exclusive (Locked) Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36113.1 Endpoint Mode Exclusive Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

    13.1.1 Lock Sequence across PEX 8311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36113.1.2 General Master Rules for Supporting Internal LOCK# Transactions . . . . . . 36213.1.3 Acquiring Exclusive Access across PEX 8311 . . . . . . . . . . . . . . . . . . . . . . . 36213.1.4 Non-Posted Transactions and Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36213.1.5 Continuing Exclusive Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36213.1.6 Completing Exclusive Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36213.1.7 Invalid PCI Express Requests while Locked . . . . . . . . . . . . . . . . . . . . . . . . . 36313.1.8 Locked Transaction Originating on Local Bus . . . . . . . . . . . . . . . . . . . . . . . . 36313.1.9 Internal PCI Bus Errors while Locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

    13.1.9.1 Internal Master Abort during Posted Transaction . . . . . . . . . . . . . . . . . . 36313.1.9.2 Internal Master Abort during Non-Posted Transaction . . . . . . . . . . . . . . 363

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    13.1.9.3 Internal Target Abort during Posted Transaction . . . . . . . . . . . . . . . . . . 36313.1.9.4 Internal Target Abort during Non-Posted Transaction . . . . . . . . . . . . . . 363

    13.2 Root Complex Mode Exclusive Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36413.2.1 Internal Target Rules for Supporting LLOCKi# . . . . . . . . . . . . . . . . . . . . . . . 36413.2.2 Acquiring Exclusive Access across PEX 8311 . . . . . . . . . . . . . . . . . . . . . . . 36413.2.3 Completing Exclusive Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36413.2.4 PCI Express Locked Read Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

    Chapter 14 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36514.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36514.2 Endpoint Mode PCI Express Power Management . . . . . . . . . . . . . . . . . . . . . . . . 366

    14.2.1 Endpoint Mode PCI Express Power Management Configuration Registers . 36614.2.2 Endpoint Mode PCI Express-PM Link Power States (L-States) . . . . . . . . . . 36614.2.3 Endpoint Mode Link State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36814.2.4 Endpoint Mode PCI Express-PM Device Power States (D-States) . . . . . . . . 37014.2.5 Endpoint Mode Power Management Event Signaling . . . . . . . . . . . . . . . . . . 37114.2.6 Set Slot Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

    14.3 Endpoint Mode Local Bus Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . 37214.3.1 Local Bus Bridge Power Management Configuration Registers . . . . . . . . . . 37214.3.2 Local Bus Bridge Device Power States (D-States) . . . . . . . . . . . . . . . . . . . . 37314.3.3 Local Interrupt (LINTo#) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37414.3.4 D0-to-D3hot Power-Down Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

    14.4 Root Complex Mode PCI Express Power Management . . . . . . . . . . . . . . . . . . . 37514.4.1 Root Complex Active State Power Management (ASPM) . . . . . . . . . . . . . . . 375

    14.4.1.1 ASPM Link Power States (L-States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37514.4.2 Root Complex PCI Express-PM Device Power Management . . . . . . . . . . . . 377

    14.4.2.1 Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37714.4.3 Root Complex PMEOUT# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37814.4.4 Root Complex Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37814.4.5 Root Complex Set Slot Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

    Chapter 15 PCI Express Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38115.1 Endpoint Mode PCI Express Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

    15.1.1 PCI INTA# Virtual Wire Interrupt Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . 38115.1.2 Power Management Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38115.1.3 Error Signaling Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38115.1.4 Locked Transactions Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38115.1.5 Slot Power Limit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38215.1.6 Hot Plug Signaling Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

    15.2 Root Complex Mode PCI Express Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . 38315.2.1 PCI INTA# Virtual Wire Interrupt Message Support . . . . . . . . . . . . . . . . . . . 38315.2.2 Power Management Message Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

    15.2.2.1 PME Handling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38315.2.3 Error Signaling Message Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38415.2.4 Locked Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38415.2.5 Slot Power Limit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

    Chapter 16 Intelligent I/O (I2O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38516.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38516.2 I2O-Compatible Messaging Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

    16.2.1 Inbound Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38716.2.2 Outbound Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38716.2.3 I2O Pointer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38816.2.4 Inbound Free List FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

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    16.2.5 Inbound Post Queue FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39016.2.6 Outbound Post Queue FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39116.2.7 Outbound Post Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39116.2.8 Inbound Free Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39116.2.9 Outbound Free List FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39216.2.10 I2O Enable Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

    Chapter 17 Vital Product Data (VPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39517.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39517.2 Local Configuration Space VPD Capabilities Registers . . . . . . . . . . . . . . . . . . . . 395

    17.2.1 VPD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39517.2.2 VPD Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

    17.3 VPD Serial EEPROM Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39617.4 Sequential Read-Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39617.5 Random Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

    Chapter 18 General-Purpose I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39918.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39918.2 USERi and USERo Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39918.3 GPIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

    Chapter 19 PCI Express Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40119.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40119.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

    19.2.1 Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40119.3 PCI Express Configuration Space Configuration Access Types . . . . . . . . . . . . . 40219.4 PCI Express Configuration Space Register Attributes . . . . . . . . . . . . . . . . . . . . . 40319.5 PCI Express Configuration Space Register Summary . . . . . . . . . . . . . . . . . . . . . 40319.6 PCI Express Configuration Space Register Mapping . . . . . . . . . . . . . . . . . . . . . 404

    19.6.1 PCI Express Configuration Space PCI-Compatible Configuration Registers (Type 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

    19.6.2 PCI Express Configuration Space PCI-Compatible Capability Registers . . . 40519.6.3 PCI Express Configuration Space PCI Express

    Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40619.6.4 PCI Express Configuration Space Main Control Registers . . . . . . . . . . . . . . 407

    19.7 PCI Express Configuration Space PCI-Compatible Configuration Registers (Type 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

    19.8 PCI-Compatible Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 43119.9 PCI Express Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

    19.9.1 PCI Express Power Budgeting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45419.9.2 PCI Express Serial Number Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

    19.10 Main Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

    Chapter 20 Local Configuration Space Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47520.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47520.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47520.3 PEX 8311 Local Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

    20.3.1 Local Configuration Space Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47620.3.2 New Capabilities Function Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47720.3.3 Local Bus Access to Local Configuration Space Registers . . . . . . . . . . . . . . 477

    20.4 Local Configuration Space Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47820.5 Local Configuration Space PCI Configuration Registers . . . . . . . . . . . . . . . . . . . 48420.6 Local Configuration Space Local Configuration Registers . . . . . . . . . . . . . . . . . . 499

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    20.7 Local Configuration Space Runtime Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 52020.8 Local Configuration Space DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52920.9 Local Configuration Space Messaging Queue (I2O) Registers . . . . . . . . . . . . . . 540

    Chapter 21 Testability and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54521.1 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

    21.1.1 IEEE Standard 1149.1 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54521.1.2 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54621.1.3 JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54821.1.4 JTAG Reset Input TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

    Chapter 22 Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54922.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54922.2 PCI Express Serial EEPROM Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54922.3 PCI Express Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54922.4 Local Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54922.5 Scatter/Gather DMA Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

    Chapter 23 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55123.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55123.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55123.3 3.3V and 5V Mixed-Voltage Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55123.4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55223.5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55323.6 Operating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55523.7 Local Bus Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55523.8 Local Bus Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55723.9 ALE Output Delay Timing for Local Bus Clock Rates . . . . . . . . . . . . . . . . . . . . . 560

    Chapter 24 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56124.1 PEX 8311 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56124.2 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56124.3 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

    Appendix A General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .563A.1 Product Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563A.2 United States and International Representatives and Distributors . . . . . . . . . . . . 564A.3 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

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  • Registers

    19-1. Offset 00h PECS_PCIVENDID PCI Vendor ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40819-2. Offset 02h PECS_PCIDEVID PCI Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40819-3. Offset 04h PECS_PCICMD PCI Command (Endpoint Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40819-4. Offset 04h PECS_PCICMD PCI Command (Root Complex Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . .41019-5. Offset 06h PECS_PCISTAT PCI Status (Endpoint Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41119-6. Offset 06h PECS_PCISTAT PCI Status (Root Complex Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41219-7. Offset 08h PECS_PCIDEVREV PCI Device Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41319-8. Offset 09h PECS_PCICLASS PCI Class Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41319-9. Offset 0Ch PECS_PCICACHESIZE PCI Cache Line Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41419-10. Offset 0Dh PECS_PCILATENCY Internal PCI Bus Latency Timer . . . . . . . . . . . . . . . . . . . . . . . . . . .41419-11. Offset 0Eh PECS_PCIHEADER PCI Header Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41419-12. Offset 0Fh PECS_PCIBIST PCI Built-In Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41419-13. Offset 10h PECS_PCIBASE0 PCI Express Base Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41519-14. Offset 14h PECS_PCIBASE1 PCI Express Base Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41519-15. Offset 18h PECS_PRIMBUSNUM Primary Bus Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41619-16. Offset 19h PECS_SECBUSNUM Secondary Bus Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41619-17. Offset 1Ah PECS_SUBBUSNUM Subordinate Bus Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41619-18. Offset 1Bh PECS_SECLATTIMER Secondary Latency Timer (Endpoint Mode Only). . . . . . . . . . . . .41619-19. Offset 1Ch PECS_IOBASE I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41719-20. Offset 1Dh PECS_IOLIMIT I/O Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41719-21. Offset 1Eh PECS_SECSTAT Secondary Status (Endpoint Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . .41819-22. Offset 1Eh PECS_SECSTAT Secondary Status (Root Complex Mode) . . . . . . . . . . . . . . . . . . . . . . .41919-23. Offset 20h PECS_MEMBASE Memory Base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42019-24. Offset 22h PECS_MEMLIMIT Memory Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42019-25. Offset 24h PECS_PREBASE Prefetchable Memory Base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42119-26. Offset 26h PECS_PRELIMIT Prefetchable Memory Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42119-27. Offset 28h PECS_PREBASEUPPER Prefetchable Memory Base Upper 32 Bits . . . . . . . . . . . . . . . .42219-28. Offset 2Ch PECS_PRELIMITUPPER Prefetchable Memory Limit Upper 32 Bits . . . . . . . . . . . . . . . .42219-29. Offset 30h PECS_IOBASEUPPER I/O Base Upper 16 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42319-30. Offset 32h PECS_IOLIMITUPPER I/O Limit Upper 16 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42319-31. Offset 34h PECS_PCICAPPTR PCI Capabilities Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42319-32. Offset 3Ch PECS_PCIINTLINE Internal PCI Interrupt Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42419-33. Offset 3Dh PECS_PCIINTPIN Internal PCI Wire Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42419-34. Offset 3Eh PECS_BRIDGECTL Bridge Control (Endpoint Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . .42519-35. Offset 3Eh PECS_BRIDGECTL Bridge Control (Root Complex Mode) . . . . . . . . . . . . . . . . . . . . . . . .42819-36. Offset 40h PECS_PWRMNGID Power Management Capability ID . . . . . . . . . . . . . . . . . . . . . . . . . . .43119-37. Offset 41h PECS_PWRMNGNEXT Power Management Next Capability Pointer . . . . . . . . . . . . . . . .43119-38. Offset 42h PECS_PWRMNGCAP Power Management Capabilities (Endpoint Mode) . . . . . . . . . . . .43119-39. Offset 42h PECS_PWRMNGCAP Power Management Capabilities (Root Complex Mode) . . . . . . . .43219-40. Offset 44h PECS_PWRMNGCSR Power Management Control/Status (Endpoint Mode) . . . . . . . . . .43319-41. Offset 44h PECS_PWRMNGCSR Power Management Control/Status (Root Complex Mode) . . . . . .43419-42. Offset 46h PECS_PWRMNGBRIDGE Power Management Bridge Support (Endpoint Mode) . . . . . .43519-43. Offset 46h PECS_PWRMNGBRIDGE Power Management Bridge Support (Root Complex Mode) . .43519-44. Offset 47h PECS_PWRMNGDATA Power Management Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43519-45. Offset 48h PECS_DEVSPECCTL Device-Specific Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43619-46. Offset 50h PECS_MSIID Message Signaled Interrupts Capability ID . . . . . . . . . . . . . . . . . . . . . . . . .43719-47. Offset 51h PECS_MSINEXT Message Signaled Interrupts Next Capability Pointer . . . . . . . . . . . . . .43719-48. Offset 52h PECS_MSICTL Message Signaled Interrupts Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .43819-49. Offset 54h PECS_MSIADDR Message Signaled Interrupts Address . . . . . . . . . . . . . . . . . . . . . . . . .43819-50. Offset 58h PECS_MSIUPPERADDR Message Signaled Interrupts Upper Address . . . . . . . . . . . . . .43919-51. Offset 5Ch PECS_MSIDATA Message Signaled Interrupts Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .439

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    ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book xxiiiCopyrig