PCI Express Hard IP Quick Start Guide with SOPC … Express Hard IP Quick Start Guide with SOPC...

Exercise Manual

For

PCI Express Hard IP Quick Start Guide

with SOPC Builder

Software and Hardware Requirements to Complete Exercise

Software Requirements: 1) The Quartus® II software version 9.0 2) ModelSim®-Altera® Edition tool version 6.4a OR ModelSim-Altera Starter

Edition tool version 6.4a (ModelSim SE is also supported)

Exercise PCI Express Hard IP Quick Start Guide with SOPC Builder

Copyright © 2009 Altera Corporation

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PCI Express Hard IP Quick Start Guide with SOPC Builder Exercise


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Objectives:

Implement a PCI Express system from to design to working model in under 45 minutes using an Arria II GX devices & SOPC Builder

Design Details:

The SOPC Builder design (shown above) that you will build in this exercise will implement a PCI Express endpoint. It contains the following blocks:

The PCI Express MegaCore function implements the protocol layers. It provides communication between the PCI Express link and components connected to the system interconnect fabric. The MegaCore function makes use of the PCI Express Hard IP blocks and the Arria II GX embedded transceivers.

The DMA can transfer data between the on-chip memory and the PCI Express MegaCore function. Its control port is mapped into PCI Express memory space so that it can be controlled by the root port to set up and configure data transfers.

The On-Chip Memory block is used to store data received from the PCI Express MegaCore function that was received from over the link or data that is to be sent over the link. Like the DMA control port, the on-chip memory is mapped into PCI Express memory space so that it is accessible by the root port.

The System Interconnect Fabric is the “bus” generated by SOPC Builder which connects the components inside the FPGA together and enables transfers between them.

You will use 8 simple steps to build this complete system.



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Step 1 (Create Quartus II project)

The first step is to create a Quartus II project. A Quartus II project is required in order to open SOPC Builder and begin building an embedded system.

1. Open the Quartus II software.

2. Run the New Project Wizard. From the Quartus II File menu, select New Project Wizard.

3. If the Introduction page appears, click Next to continue.

4. Set the working directory. On Page 1 (Directory, Name, Top-Level Entity) of the Wizard, in the field “What is the working directory for this project?”, type in or use

the browse button to select a directory in which you want to build your design.

5. Specify the top-level enity. In the field “What is the name of this project?”, type in pcie_top.

Notice the wizard assumes that pcie_top is name for the top-level design-entity too. Do not change the name. You will use this name as the name of your SOPC Builder system later as this simplifies the design process.

Your wizard window should look simiilar to the above.

6. Click Next to continue to page 2 of the wizard.



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7. On Page 2 (Add Files) of the wizard, you can add design and support files to the project. Since SOPC Builder will be generating all of the necessary design files, you have no files to add at this time.

8. Click Next to continue to page 3 of the wizard.

9. Select the target device family. On Page 3 (Family & Device) of the wizard, in the Device Family section, use the Family: drop-down menu to select the Arria II GX device family.

10. Use the filters to limit the Available devices list to 1152-pin FPGA devcies in the fastest speed grade. In the Show in ‘Available device’ list section, use the drop-down menus to select FBGA for Package:, 1152 for Pin Count: and 4 for Speed Grade:.

This will limit the Available Devices list to just for 4 part numbers.

11. Select the EP2AGX125EF35C4 from the Available devices list.

Your wizard window should look like as above.

12. Finish the wizard. Since you will be using the defaults for the remaining wizard settings, click Finish to complete the wizard.

The last two pages of the wizard are the EDA Tools page, which allow you to specify additional 3rd-party EDA tools for synthesis or simulation, and the Summary page.



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Step 2 (Start SOPC Builder)

1. Open SOPC Builder. From the Quartus II Tools menu, select SOPC Builder, or click

on the button in the Quartus II toolbar.

SOPC Builder will now open. The Create New System dialog box appears.

2. Name the system pcie_top. In the Create New System dialog box, type pcie_top as the System Name.

Remember that pcie_top is the top-level entity of your Quartus II project.

3. Choose a design language. In the Create New System dialog box, choose Verilog as your Target HDL:.

SOPC Builder does support both VHDL and Verilog. To simplify the instructions used for this tutorial, you will use Verilog HDL.

Your Create New System dialog box should look like the above.

4. Click OK to close the Create New System dialog box.



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Your SOPC Builder window should be open and look like the above.

Step 3 (Use PCI Express Compiler to add PCI Express MegaCore block to system)

You will now add your first component to your embedded system, the PCI Express MegaCore function, using the PCI Express Compiler opened from within SOPC Builder.

1. Select the PCI Express Compiler from the SOPC Builder Component Library. In SOPC Builder with the System Contents tab selected, go to the Component Library. Expand Interface Protocols and then PCI. Highlight PCI Express Compiler.



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Your SOPC Builder Component Library should look like the above.

2. Click on the Add button to start the PCI Express Compiler.

You will now see the pci_compiler_0 module added to your system and the PCI Express Compiler will immediately open starting on the System Settings tab.

3. Configure the general, system-related settings. On the System Settings tab of the PCI Express Compiler, choose the following options.

a. Select PCI Express hard IP for the PCIe Core Type.

b. Select Arria II GX for the PHY type (the PCIe System Parameters section).

c. Select x4 for the number of Lanes.

d. Select 1.1 for the PCI Express version.

The remainder of the options on this page (e.g. port type, clock rates, application interface) are mandatory when using the PCI Express MegaCore function with SOPC Builder. You also have the option of clicking on the Configure transceiver block button and disabling the receiver channels’ rate match FIFOs, but for this exercise you will leave them enabled.



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Your System Settings page should look like the above.

4. Configure the PCIe BARs for this endpoint. Click on the PCI Registers tab of the PCI Express Compiler and choose the following options:

a. Click on the BAR Type field for BAR 2 (row 2 in the PCI Base Address Registers section) where it says “Select Type to Enter”.

b. From the drop-down menu that appears, select 32-bit Non-Prefetchable Memory.

c. Leave the BAR Size and Avalon Base Address fields set to Auto.

These settings control the PCI Express to Avalon-MM translation. The settings you chose mean this endpoint will present 2 address spaces to the PCIe link, a 64-bit memory space and a 32-bit memory space. Choosing Auto lets SOPC Builder decide the size of each BAR and the Avalon-MM base addresses within SOPC Builder system to which the BARs will be translated. Each BAR maps to a specific Avalon-MM address range. You can manually map the BAR/Avalon-MM address



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ranges, but it may require several iterations to eliminate any possible address conflicts.

d. Leave the other settings (PCI Read-Only Registers) at their defaults.

Your PCI Registers page should look like the above.

For the Capabilities, Buffer Setup and Power Management pages of the compiler, you will leave the default settings.

5. Configure the Avalon-MM interface to the embedded system. Click on the Avalon Configuration tab of the PCI Express Compiler. Choose the following options:

a. Select Use separate clock for the Avalon Clock Domain. This means the embedded system will run on its own clock, not one generated by the PCIe MegaCore function.

b. Select Requester/Completer for the PCIe Peripheral Mode. This creates an additional TX interface for the SOPC Builder system so that internal system masters, like the DMA, can initiate PCIe requests to the PCI link. Otherwise the core could only complete requests received from over the link.

c. Select Dynamic translation table for Address Translation Table Configuration.



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d. Select 2 for the Number of address pages (in the Address Translation Table Size section).

e. Select 1 MByte – 20 bits for the Size of address pages.

These settings control the Avalon-MM to PCI Express address translation, meaning how transfers originating inside the SOPC Builder system are converted into PCI Express requests. You have indicated that your DMA will see two 1-MByte address ranges. These addresses start at the base address defined for the Tx_Interface port, shown in the Base address column of the system contents tab of SOPC Builder. That address is currently 0x00000000 (as you will see later), so the 2 address ranges are (1) 0x0000000-0x000FFFFF and (2) 0x00100000-0x001FFFFF. Since you have chosen dynamic address translation, then the translation of these address ranges into their corresponding PCI Express address ranges is under software control by means of the control register port.

Your Avalon Configuration page should look like the above.

6. Click Finish to close the compiler and return to the SOPC Builder system.

Your PCI Express MegaCore function is added to SOPC Builder and named pcie_compiler_0. It has two master ports representing the two BARs that you configured. This allows PCIe request transactions from the link to access slaves in



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local address space that you connect to the BAR masters. The Control Register Access slave port provides MegaCore internal register access to other Avalon-MM masters and PCI Express devices. The Tx_Interface allows internal masters to access PCI Express address space.

Your SOPC Builder window should appear as above. Do not worry about the error messages. They will disappear as you add other components.

Step 4 (Add remaining components to system)

You will now add the remaining components, the DMA and on-chip memory, to complete your SOPC Builder-generated PCI Express endpoint.

1. Select the DMA from the SOPC Builder Component Library. In SOPC Builder with the System Contents tab selected, go to the Component Library. Expand Memories and Memory Controllers and then DMA. Highlight DMA Controller.



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2. Click on the Add button to start the DMA Controller wizard.

Like with the PCI Express Compiler, you will see a DMA component added to your system and then the wizard will open to allow you to configure the component.

3. Configure your DMA controller as follows:

a. Choose 13 for the Width of the DMA length register (Transfer Size section). This configures the maximum number of transfers for which you can program the DMA to execute. So, 13 means up to 8191 (2**13 – 1) transfers.

b. Set the Enable burst transfers option under Burst transactions. This allows the DMA to use Avalon-MM bursting transactions to increase system performance.

c. Set the Maximum burst size to 1024 words.

d. Choose to Construct FIFO from embedded memory blocks (under FIFO Implementation).

The settings on the Advanced tab will be left at their defaults.



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Your DMA Controller wizard should look like above.

4. Click Finish to close the DMA Controller wizard.

Your DMA is now added to SOPC Builder and named dma_0. It has two master ports to intiate read and write trasnfers within the subsystem. It also has a control port slave to program the DMA.



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Your SOPC Builder window should appear as above.

5. Select the on-chip memory from the SOPC Builder Component Library. In the SOPC Builder Component Library, look under the Memories and Memory Controllers folder and expand On-Chip. Highlight On-Chip Memory (RAM or ROM).



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6. Click on the Add button to start the On-Chip Memory wizard.

7. Configure your on-chip memory parameters as follows:

a. Under Memory type options, choose RAM (Writable).

b. Choose Auto for the Block type. This lets the compiler choose which of the 3 Arra II GX embedded RAM types to use for this memory.

c. Choose 64 as the Data width: (Size section). This is done since the PCIe MegaCore uses a 64-bit data bus.

d. Select 4096 Bytes as the Total memory size. This creates a 4096 x 64 RAM inside of pcie_top to store data for transfer.

The rest of the On-Chip Memory wizard you will leave at their defaults.



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Your On-Chip Memory wizard should look like the above.

8. Click Finish to close the On-Chip Memory wizard.

Your RAM block is now added to SOPC Builder and named onchip_memory2_0. It has a single slave port to access its address space.



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Your SOPC Builder system should look like the above.

Step 5 (Connect component ports together)

In SOPC Builder, you will now use the Connection column on the System Contents tab to connect all of your components together.

1. Connect BAR1_0 Avalon-MM master to onchip_memory2_0. Highlight the bar1_0_Prefectable master port of pcie_compiler_0. Follow the blue line for the master port and click on the empty dot for the s1 port of onchip_memory2_0.

Your connection panel should look like the above as you connect the two components.



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2. Use the following table to connect the remaining components:

From To

Module Master Port Module Slave Port

pcie_compiler0 bar2_Non_Prefectable pcie_compiler0 Control_Register_Access

pcie_compiler0 bar2_Non_Prefectable dma_0 control_port_slave

dma_0 read_master onchip_memory2_0 s1

dma_0 read_master pcie_compiler0 Tx_Interface

dma_0 write_master onchip_memory2_0 s1

dma_0 write_master pcie_compiler0 Tx_Interface

When complete, your connection panel should like the above when you move the mouse over the connection panel.

Step 6 (Add calibration clock and adjust addresses)

Arria II GX devices require use of a separate clock input signal called the calibration clock to drive the calibration block. The calibration block calibrates the values of the on-chip termination resisters, transceiver phase-locked loop (PLLs) settings and output buffer settings. This makes their functionality independent of process, voltage and temperature (PVT) variations.

1. Add a new clock to your system. In the Clock Settings section of the SOPC Builder window (System Contents tab), click on the Add button.

A new external clock, clk_1, is added to the list.

2. Change the name of clk_1. In the Clock Settings section, double-click on the name clk_1. Change the name from clk_1 to cal_clk.

3. Change the frequency of cal_clk. In the Clock Settings section, double-click on the 50.0 MHz frequency of cal_clk. Change 50.0 to 100.



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The calibration clock requires an input frequency of 10-125 MHz. Since clk_0 is set to 50 MHz, you could just easily have used clk_0 as your calibration clock. But, we wanted you to perform an example of adding a new clock to your system.

Your Clock Settings window section should look like the above.

4. Check that the calibration clock is connected to the PCI MegaCore function. In the SOPC Builder window, click on the Filters button. In the Filters window that appears, change the Filter from Default to All. This will display clock interfaces as separate ports in the Connection column. Notice that pcie_compiler_0 now displays 2 clock input ports, avalon_clk and cal_blk_clk. Avalon_clk is driven by clk_0 and controls all pcie_compiler_0 Avalon-MM interfaces. Cal_blk_clk is driven by cal_clk and controls the calibration block logic. This is correct so you will leave the settings as they are.

Your pcie_compiler_0 block should be connected like the above.

5. Change the Filter: setting back to Default and close the Filters window.

6. Set the address of the pcie_compiler_0 component’s Control Register Access port to 0x80004000. On the System Contents tab of SOPC Builder, locate the Base address column. For the pcie_compiler_0 Control_Register_Access port, double-click on the address 0x00000000 and change the base address from 0x00000000 to 0x80004000.



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7. Use the following table to change three other base addresses in the system

Module Port New Base Address

dma_0 control_port_slave 0x80001000

onchip_memory2_0 s1 0x80000000

When complete, your Base address column should look like the above.

So, let’s review this system. Looking at these connections, PCI Express requests accessing an address assigned to BAR0/1 will be converted to Avalon-MM read and write transfers sent to onchip_memory2_0. PCI Express requests accessing a BAR2 address will be converted to Avalon-MM read and write transfers sent to the control registers of pcie_compiler_0 and dma_0. BAR0/1 accesses Avalon-MM addresses 0x80000000-0x80000fff. BAR2 accesses Avalon-MM addresses 0x80001000-0x80007fff. The dma_0 component can originate Avalon-MM read and write transfers to the Tx_Interface for conversion into PCI Express requests.

Step 7 (Generate the SOPC Builder system)

You will now use SOPC Builder to generate files needed to continue both hardware and software development.

1. Go the System Generation tab. At the bottom of the SOPC Builder window, click on the Next button to go to the System Generation tab.

2. Enable SOPC Builder to create ModelSim simulation files. In the Options section, click to enable Simulation. Create project simulator files.

This tells SOPC Builder to create a testbench to exercise your system, a ModelSim project file (.MPF) and script files to accelerate setting up and running a simulation.

3. Generate the system. At the bottom of the SOPC Builder window, click on the Generate button to generate all files. Click Save to save the system.

System generation may take 5-10 minutes. The message “System generation was successful” will appear when complete.



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Step 8 (Simulate SOPC Builder system in ModelSim tool)

For this exercise, you are going to simulate your system in the ModelSim simulation tool using its command line mode.

1. Open a command window. From the Start menu, choose Run. In the Run window, type cmd and click OK (or hit the Enter key).

SOPC Builder has automatically created a .DO, or ModelSim macro file, called setup_sim.do. This macro file creates aliases that you can use to compile and load your design as well as open the wave or list window with pre-loaded signals you can monitor to verify simulation.

2. Edit the setup_sim.do file generated by SOPC Builder.

a. Using a text editor, browse to the directory <sopc_system_directory>/pcie_top_sim and open the file setup_sim.do.

b. Go to line 22.

c. Type the following on line 22 of the file setup_sim.do IN BETWEEN “+nowarnTFMPC” and “-L lpm_ver”. (It should all be on a single line.)

-L stratixiv_pcie_hip_ver –L arriaii_hssi_ver –L arriaii_pcie_hip_ver

d. Close and save setup_sim.do.

Currently, the setup_sim.do file is missing the above library references which accelerate simulation in ModelSim-Altera tools. This behavior will be fixed in the Quartus II software version 9.1.

3. Change the working directory. In the command window, type cd <sopc_system_directory>\pcie_top_sim at the command prompt and hit the Enter key.

Your window should look similar to the above.

4. Start the ModelSim simulation tool in command-line mode. At the command prompt, type vsim –c and hit the Enter key.

When the ModelSim tool is started in your working directory in command-line mode, the tool automatically reads a modelsim.tcl file that was created and placed in the _sim directory by SOPC Builder. This TCL file loads the setup_sim.do ModelSim macro file. If you were running the GUI, you would load this macro file manually.



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Above is an image of the command window with the macro file loaded. As you can see from the commented section, these defined aliases are ‘s’, ‘c’, ‘w’. ‘l’ and ‘h’.

5. Open and edit the testbench file.

a. Using a text editor, browse to the directory <sopc_system_directory>/pcie_compiler_0_examples/sopc/testbench and open the file altpcietb_bfm_driver.v.

b. Go to lines 34 & 35.

c. Change the parameter setting for RUN_TGT_MEM_TST to 1.

d. Change the parameter setting for RUN_DMA_MEM_TST to 1.

e. Save the file altpcietb_bfm_driver.v.

This enables the testbench bus functional model (BFM) to simulate writing to the target (on-chip) memory and the DMA during the simulation. Remember the BFM represents the other end of the PCI Express link. So, this means that your simulation will show the initiation of the PCI Express link followed by requests that will exercise the DMA.

6. Type ‘s’ (without the quotes) at the command prompt and hit the Enter key.



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‘S’ is an alias defined in the setup_sim.do macro file which causes the ModelSim tool to compile all design files and then load the simulator with the testbench as the top-level module.

7. Advance simulation. Type run –all at the command prompt and hit the Enter key.

This command executes simulation until all testbench stimulus is complete. This can take about 25-30 minutes. To verify correct operation of the PCIe endpoint, check the messages displayed in the command prompt window. You should see messages indicating the following operations.

Event

Configuring endpoint and reading configuration registers

Endpoint MSI capability read

Lane width negotiated

BAR address assignments

BAR0/1 write/read test to on-chip RAM

BAR2 write to program DMA to transfer 4 KBytes of data

DMA Read/Write test completed



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Summary

Use SOPC Builder and PCI Express Compiler to build a PCI Express endpoint in an Arria II GX device, taking advantage of the Arria II GX PCI Express Hard IP bock

This design was built in 8 easy steps:

1. Create Quartus II project

2. Start SOPC Builder

3. Use the PCI Express Compiler to add the PCI Express MegaCore function to system

4. Add remaining components (e.g. DMA, on-chip memory)

5. Connect component ports connections

6. Add calibration clock and adjust addresses

7. Generate SOPC Builder system

8. Simulate SOPC Builder system in ModelSim tool

END OF EXERCISE

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