PCI Express® Base Specification Revision 4.0 Version 0.3

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Revision Revision History DATE 1.0 Initial release. 07/22/2002 1.0a Incorporated Errata C1-C66 and E1-E4.17. 04/15/2003 1.1 Incorporated approved Errata and ECNs. 03/28/2005 2.0 Added 5.0 GT/s data rate and incorporated approved Errata and ECNs. 12/20/2006 2.1 Incorporated Errata for the PCI Express Base Specification, Rev. 2.0
(February 27, 2009), and added the following ECNs: • Internal Error Reporting ECN (April 24, 2008) • Multicast ECN (December 14, 2007, approved by PWG May 8, 2008) • Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008) • Resizable BAR Capability ECN (January 22, 2008, updated and approved by
PWG April 24, 2008) • Dynamic Power Allocation ECN (May 24, 2008) • ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008) • Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008) • Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated
June 4, 2007) • Extended Tag Enable Default ECN (September 5, 2008) • TLP Processing Hints ECN (September 11, 2008) • TLP Prefix ECN (December 15, 2008)
03/04/2009
3.0 Added 8.0 GT/s data rate, latest approved Errata, and the following ECNs: • Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009) • ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009) • Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol
Multiplexing ECN (17 June 2010)
11/10/2010
3.1 Incorporated Errata for the PCI Express® Base Specification Revision 3.0 (November 7, 2013) Incorporated the following ECNs: • ECN: Downstream Port containment (DPC) • ECN: Separate Refclk Independent SSC (SRIS) Architecture • ECN: Process Address Space ID (PASID) • ECN: Lightweight Notification (LN) Protocol • ECN: Precision Time Measurement • ECN: Enhanced DPC (eDPC) • ECN: 8.0 GT/s Receiver Impedance • ECN: L1 PM Substates with CLKREQ • ECN: Change Root Complex Event Collector Class Code • ECN: M-PCIe • ECN: Readiness Notifications (RN)
11/7/2013
4.0 Version 0.3: Based on PCI Express® Base Specification Revision 3.1 (November 7, 2013) with some editorial feedback received in December 2013. • Added Chapter 9, Electrical Sub-block: Separated Section 4.3 of the 3.1 Base
Specification to create Chapter 9.Added Chapter 9 (Rev0.3-11-30-13_final.docx) • Changes related to Revision 0.3 release •
2/19/2014
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Membership Services www.pcisig.com E-mail: [email protected] Phone: 503-619-0569 Fax: 503-644-6708
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DISCLAIMER This PCI Express Base Specification is provided “as is” with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.
Copyright © 2002-2014 PCI-SIG
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DOCUMENT ORGANIZATION.............................................................................................. 35
1. INTRODUCTION............................................................................................................... 46
1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 46 1.2. PCI EXPRESS LINK ......................................................................................................... 49 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 50
Root Complex ........................................................................................................ 50 1.3.1. Endpoints .............................................................................................................. 51 1.3.2. Switch .................................................................................................................... 54 1.3.3. Root Complex Event Collector .............................................................................. 55 1.3.4. PCI Express to PCI/PCI-X Bridge ........................................................................ 55 1.3.5.
1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 55 1.5. PCI EXPRESS LAYERING OVERVIEW .............................................................................. 56
Transaction Layer ................................................................................................. 57 1.5.1. Data Link Layer .................................................................................................... 57 1.5.2. Physical Layer ...................................................................................................... 58 1.5.3. Layer Functions and Services ............................................................................... 58 1.5.4.
2. TRANSACTION LAYER SPECIFICATION ................................................................. 62
2.1. TRANSACTION LAYER OVERVIEW .................................................................................. 62 Address Spaces, Transaction Types, and Usage ................................................... 63 2.1.1. Packet Format Overview ...................................................................................... 65 2.1.2.
2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION ............................................... 67 Common Packet Header Fields ............................................................................ 67 2.2.1. TLPs with Data Payloads - Rules ......................................................................... 70 2.2.2. TLP Digest Rules .................................................................................................. 74 2.2.3. Routing and Addressing Rules .............................................................................. 74 2.2.4. First/Last DW Byte Enables Rules ........................................................................ 78 2.2.5. Transaction Descriptor ......................................................................................... 81 2.2.6. Memory, I/O, and Configuration Request Rules ................................................... 87 2.2.7. Message Request Rules ......................................................................................... 94 2.2.8. Completion Rules ................................................................................................ 115 2.2.9.
TLP Prefix Rules ................................................................................................. 118 2.2.10. 2.3. HANDLING OF RECEIVED TLPS .................................................................................... 123
Request Handling Rules ...................................................................................... 126 2.3.1. Completion Handling Rules ................................................................................ 138 2.3.2.
2.4. TRANSACTION ORDERING ............................................................................................ 142 Transaction Ordering Rules ............................................................................... 142 2.4.1.
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3
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Update Ordering and Granularity Observed by a Read Transaction ................ 145 2.4.2. Update Ordering and Granularity Provided by a Write Transaction ................ 146 2.4.3.
2.5. VIRTUAL CHANNEL (VC) MECHANISM ........................................................................ 147 Virtual Channel Identification (VC ID) .............................................................. 149 2.5.1. TC to VC Mapping .............................................................................................. 150 2.5.2. VC and TC Rules ................................................................................................. 151 2.5.3.
2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 152 Flow Control Rules ............................................................................................. 153 2.6.1.
2.7. DATA INTEGRITY ......................................................................................................... 164 ECRC Rules ........................................................................................................ 165 2.7.1. Error Forwarding ............................................................................................... 169 2.7.2.
2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 171 2.9. LINK STATUS DEPENDENCIES ...................................................................................... 172
Transaction Layer Behavior in DL_Down Status ............................................... 172 2.9.1. Transaction Layer Behavior in DL_Up Status ................................................... 173 2.9.2. Transaction Layer Behavior During Downstream Port Containment ............... 174 2.9.3.
3. DATA LINK LAYER SPECIFICATION ...................................................................... 176
3.1. DATA LINK LAYER OVERVIEW .................................................................................... 176 3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 178
Data Link Control and Management State Machine Rules ................................ 179 3.2.1. 3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 181
Flow Control Initialization State Machine Rules ............................................... 182 3.3.1. 3.4. DATA LINK LAYER PACKETS (DLLPS) ........................................................................ 185
Data Link Layer Packet Rules ............................................................................ 185 3.4.1. 3.5. DATA INTEGRITY ......................................................................................................... 190
Introduction......................................................................................................... 190 3.5.1. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 190 3.5.2. LCRC and Sequence Number (TLP Receiver) .................................................... 203 3.5.3.
4. PHYSICAL LAYER SPECIFICATION ........................................................................ 213
4.1. INTRODUCTION ............................................................................................................ 213 4.2. LOGICAL SUB-BLOCK ................................................................................................... 213
Encoding for 2.5 GT/s and 5.0 GT/s Data Rates ................................................ 214 4.2.1. Encoding for 8.0 GT/s and Higher Data Rates................................................... 222 4.2.2. Link Equalization Procedure for 8.0 GT/s and Higher Data Rates ................... 241 4.2.3. Link Initialization and Training .......................................................................... 251 4.2.4. Link Training and Status State Machine (LTSSM) Descriptions ........................ 270 4.2.5. Link Training and Status State Rules .................................................................. 273 4.2.6. Clock Tolerance Compensation .......................................................................... 342 4.2.7. Compliance Pattern in 8b/10b Encoding ............................................................ 347 4.2.8. Modified Compliance Pattern in 8b/10b Encoding ............................................ 348 4.2.9.
Compliance Pattern in 128b/130b Encoding ...................................................... 350 4.2.10. Modified Compliance Pattern in 128b/130b Encoding ...................................... 352 4.2.11.
5. POWER MANAGEMENT .............................................................................................. 353
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Statement of Requirements .................................................................................. 354 5.1.1. 5.2. LINK STATE POWER MANAGEMENT ............................................................................. 354 5.3. PCI-PM SOFTWARE COMPATIBLE MECHANISMS ......................................................... 360
Device Power Management States (D-States) of a Function .............................. 360 5.3.1. PM Software Control of the Link Power Management State .............................. 364 5.3.2. Power Management Event Mechanisms ............................................................. 369 5.3.3.
5.4. NATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS ....................................... 376 Active State Power Management (ASPM) .......................................................... 376 5.4.1.
5.5. L1 PM SUBSTATES ...................................................................................................... 396 Entry conditions for L1 PM Substates and L1.0 Requirements .......................... 400 5.5.1. L1.1 Requirements .............................................................................................. 401 5.5.2. L1.2 Requirements .............................................................................................. 402 5.5.3. L1 PM Substates Configuration .......................................................................... 406 5.5.4. L1 PM Substates Timing Parameters ................................................................. 408 5.5.5.
5.6. AUXILIARY POWER SUPPORT ....................................................................................... 408 Auxiliary Power Enabling ................................................................................... 408 5.6.1.
5.7. POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS ............................................. 410
6. SYSTEM ARCHITECTURE .......................................................................................... 411
6.1. INTERRUPT AND PME SUPPORT ................................................................................... 411 Rationale for PCI Express Interrupt Model........................................................ 411 6.1.1. PCI Compatible INTx Emulation ........................................................................ 412 6.1.2. INTx Emulation Software Model ........................................................................ 412 6.1.3. Message Signaled Interrupt (MSI/MSI-X) Support ............................................. 412 6.1.4. PME Support ....................................................................................................... 413 6.1.5. Native PME Software Model .............................................................................. 414 6.1.6. Legacy PME Software Model ............................................................................. 414 6.1.7. Operating System Power Management Notification ........................................... 415 6.1.8. PME Routing Between PCI Express and PCI Hierarchies ................................ 415 6.1.9.
6.2. ERROR SIGNALING AND LOGGING ................................................................................ 415 Scope ................................................................................................................... 416 6.2.1. Error Classification ............................................................................................ 416 6.2.2. Error Signaling ................................................................................................... 418 6.2.3. Error Logging ..................................................................................................... 426 6.2.4. Sequence of Device Error Signaling and Logging Operations .......................... 432 6.2.5. Error Message Controls ..................................................................................... 434 6.2.6. Error Listing and Rules ...................................................................................... 435 6.2.7. Virtual PCI Bridge Error Handling .................................................................... 440 6.2.8. Internal Errors .................................................................................................... 442 6.2.9.
Downstream Port Containment (DPC) ............................................................... 442 6.2.10. 6.3. VIRTUAL CHANNEL SUPPORT ...................................................................................... 453
Introduction and Scope ....................................................................................... 453 6.3.1. TC/VC Mapping and Example Usage ................................................................. 453 6.3.2. VC Arbitration .................................................................................................... 455 6.3.3. Isochronous Support ........................................................................................... 463 6.3.4.
6.4. DEVICE SYNCHRONIZATION ......................................................................................... 466 6.5. LOCKED TRANSACTIONS .............................................................................................. 467
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Introduction......................................................................................................... 467 6.5.1. Initiation and Propagation of Locked Transactions - Rules ............................... 468 6.5.2. Switches and Lock - Rules................................................................................... 469 6.5.3. PCI Express/PCI Bridges and Lock - Rules ....................................................... 469 6.5.4. Root Complex and Lock - Rules .......................................................................... 470 6.5.5. Legacy Endpoints ................................................................................................ 470 6.5.6. PCI Express Endpoints ....................................................................................... 470 6.5.7.
6.6. PCI EXPRESS RESET - RULES ....................................................................................... 470 Conventional Reset ............................................................................................. 470 6.6.1. Function-Level Reset (FLR) ................................................................................ 473 6.6.2.
6.7. PCI EXPRESS HOT-PLUG SUPPORT .............................................................................. 478 Elements of Hot-Plug .......................................................................................... 478 6.7.1. Registers Grouped by Hot-Plug Element Association ........................................ 484 6.7.2. PCI Express Hot-Plug Events ............................................................................. 486 6.7.3. Firmware Support for Hot-Plug ......................................................................... 489 6.7.4. Async Removal .................................................................................................... 489 6.7.5.
6.8. POWER BUDGETING CAPABILITY ................................................................................. 491 System Power Budgeting Process Recommendations ......................................... 491 6.8.1.
6.9. SLOT POWER LIMIT CONTROL ..................................................................................... 492 6.10. ROOT COMPLEX TOPOLOGY DISCOVERY ..................................................................... 495 6.11. LINK SPEED MANAGEMENT ......................................................................................... 497 6.12. ACCESS CONTROL SERVICES (ACS) ............................................................................ 498
ACS Component Capability Requirements ......................................................... 499 6.12.1. Interoperability ................................................................................................... 503 6.12.2. ACS Peer-to-Peer Control Interactions .............................................................. 504 6.12.3. ACS Violation Error Handling ........................................................................... 505 6.12.4. ACS Redirection Impacts on Ordering Rules ..................................................... 505 6.12.5.
6.13. ALTERNATIVE ROUTING-ID INTERPRETATION (ARI) .................................................. 508 6.14. MULTICAST OPERATIONS ............................................................................................. 512
Multicast TLP Processing ................................................................................... 512 6.14.1. Multicast Ordering.............................................................................................. 515 6.14.2. Multicast Capability Structure Field Updates .................................................... 515 6.14.3. MC Blocked TLP Processing .............................................................................. 516 6.14.4. MC_Overlay Mechanism .................................................................................... 516 6.14.5.
6.15. ATOMIC OPERATIONS (ATOMICOPS) ........................................................................... 520 AtomicOp Use Models and Benefits ................................................................... 521 6.15.1. AtomicOp Transaction Protocol Summary ......................................................... 521 6.15.2. Root Complex Support for AtomicOps ................................................................ 523 6.15.3. Switch Support for AtomicOps ............................................................................ 524 6.15.4.
6.16. DYNAMIC POWER ALLOCATION (DPA) CAPABILITY ................................................... 525 DPA Capability with Multi-Function Devices .................................................... 526 6.16.1.
6.17. TLP PROCESSING HINTS (TPH) ................................................................................... 526 Processing Hints ................................................................................................. 526 6.17.1. Steering Tags ...................................................................................................... 527 6.17.2. ST Modes of Operation ....................................................................................... 528 6.17.3. TPH Capability ................................................................................................... 529 6.17.4.
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6.18. LATENCY TOLERANCE REPORTING (LTR) MECHANISM .............................................. 530 6.19. OPTIMIZED BUFFER FLUSH/FILL (OBFF) MECHANISM ................................................ 536 6.20. PASID TLP PREFIX ..................................................................................................... 540
Managing PASID TLP Prefix Usage .................................................................. 540 6.20.1. PASID TLP Layout ............................................................................................. 541 6.20.2.
6.21. LIGHTWEIGHT NOTIFICATION (LN) PROTOCOL ............................................................ 545 LN Protocol Operation ....................................................................................... 546 6.21.1. LN Registration Management ............................................................................. 547 6.21.2. LN Ordering Considerations .............................................................................. 548 6.21.3. LN Software Configuration ................................................................................. 548 6.21.4. LN Protocol Summary ......................................................................................... 549 6.21.5.
6.22. PRECISION TIME MEASUREMENT (PTM) MECHANISM ................................................ 551 Introduction......................................................................................................... 551 6.22.1. PTM Link Protocol ............................................................................................. 553 6.22.2. Configuration and Operational Requirements ................................................... 556 6.22.3.
6.23. READINESS NOTIFICATIONS (RN) ................................................................................ 562 Device Readiness Status (DRS) .......................................................................... 562 6.23.1. Function Readiness Status (FRS) ........................................................................ 563 6.23.2. FRS Queuing ....................................................................................................... 564 6.23.3.
7. SOFTWARE INITIALIZATION AND CONFIGURATION ...................................... 565
7.1. CONFIGURATION TOPOLOGY ........................................................................................ 565 7.2. PCI EXPRESS CONFIGURATION MECHANISMS ............................................................. 566
PCI 3.0 Compatible Configuration Mechanism ................................................. 567 7.2.1. PCI Express Enhanced Configuration Access Mechanism (ECAM) .................. 568 7.2.2. Root Complex Register Block ............................................................................. 572 7.2.3.
7.3. CONFIGURATION TRANSACTION RULES ....................................................................... 573 Device Number.................................................................................................... 573 7.3.1. Configuration Transaction Addressing............................................................... 574 7.3.2. Configuration Request Routing Rules ................................................................. 574 7.3.3. PCI Special Cycles .............................................................................................. 575 7.3.4.
7.4. CONFIGURATION REGISTER TYPES .............................................................................. 576 7.5. PCI-COMPATIBLE CONFIGURATION REGISTERS ........................................................... 577
Type 0/1 Common Configuration Space ............................................................. 577 7.5.1. Type 0 Configuration Space Header ................................................................... 585 7.5.2. Type 1 Configuration Space Header ................................................................... 587 7.5.3.
7.6. PCI POWER MANAGEMENT CAPABILITY STRUCTURE .................................................. 591 7.7. MSI AND MSI-X CAPABILITY STRUCTURES ................................................................ 593
Vector Control for MSI-X Table Entries ............................................................. 593 7.7.1. 7.8. PCI EXPRESS CAPABILITY STRUCTURE ........................................................................ 594
PCI Express Capability List Register (Offset 00h) ............................................. 595 7.8.1. PCI Express Capabilities Register (Offset 02h) ................................................. 596 7.8.2. Device Capabilities Register (Offset 04h) .......................................................... 598 7.8.3. Device Control Register (Offset 08h) ................................................................. 603 7.8.4. Device Status Register (Offset 0Ah) .................................................................... 610 7.8.5. Link Capabilities Register (Offset 0Ch) .............................................................. 612 7.8.6. Link Control Register (Offset 10h) ..................................................................... 617 7.8.7.
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Link Status Register (Offset 12h) ........................................................................ 625 7.8.8. Slot Capabilities Register (Offset 14h) ............................................................... 629 7.8.9.
Slot Control Register (Offset 18h) ...................................................................... 631 7.8.10. Slot Status Register (Offset 1Ah) ......................................................................... 635 7.8.11. Root Control Register (Offset 1Ch) .................................................................... 637 7.8.12. Root Capabilities Register (Offset 1Eh) ............................................................. 638 7.8.13. Root Status Register (Offset 20h) ........................................................................ 639 7.8.14. Device Capabilities 2 Register (Offset 24h) ....................................................... 640 7.8.15. Device Control 2 Register (Offset 28h) .............................................................. 646 7.8.16. Device Status 2 Register (Offset 2Ah) ................................................................. 650 7.8.17. Link Capabilities 2 Register (Offset 2Ch) ........................................................... 650 7.8.18. Link Control 2 Register (Offset 30h) .................................................................. 653 7.8.19. Link Status 2 Register (Offset 32h) ..................................................................... 658 7.8.20. Slot Capabilities 2 Register (Offset 34h) ............................................................ 663 7.8.21. Slot Control 2 Register (Offset 38h) ................................................................... 663 7.8.22. Slot Status 2 Register (Offset 3Ah)...................................................................... 663 7.8.23.
7.9. PCI EXPRESS EXTENDED CAPABILITIES ....................................................................... 663 Extended Capabilities in Configuration Space ................................................... 664 7.9.1. Extended Capabilities in the Root Complex Register Block ............................... 664 7.9.2. PCI Express Extended Capability Header .......................................................... 664 7.9.3.
7.10. ADVANCED ERROR REPORTING CAPABILITY ............................................................... 665 Advanced Error Reporting Extended Capability Header (Offset 00h) ............... 666 7.10.1. Uncorrectable Error Status Register (Offset 04h) .............................................. 667 7.10.2. Uncorrectable Error Mask Register (Offset 08h) ............................................... 669 7.10.3. Uncorrectable Error Severity Register (Offset 0Ch) .......................................... 671 7.10.4. Correctable Error Status Register (Offset 10h) .................................................. 673 7.10.5. Correctable Error Mask Register (Offset 14h) ................................................... 674 7.10.6. Advanced Error Capabilities and Control Register (Offset 18h) ....................... 675 7.10.7. Header Log Register (Offset 1Ch) ...................................................................... 677 7.10.8. Root Error Command Register (Offset 2Ch) ...................................................... 678 7.10.9.
Root Error Status Register (Offset 30h) .......................................................... 679 7.10.10. Error Source Identification Register (Offset 34h) .......................................... 682 7.10.11. TLP Prefix Log Register (Offset 38h) ............................................................. 682 7.10.12.
7.11. VIRTUAL CHANNEL CAPABILITY ................................................................................. 683 Virtual Channel Extended Capability Header (Offset 00h) ................................ 685 7.11.1. Port VC Capability Register 1 (Offset 04h) ........................................................ 685 7.11.2. Port VC Capability Register 2 (Offset 08h) ........................................................ 687 7.11.3. Port VC Control Register (Offset 0Ch) ............................................................... 688 7.11.4. Port VC Status Register (Offset 0Eh) .................................................................. 689 7.11.5. VC Resource Capability Register ....................................................................... 690 7.11.6. VC Resource Control Register ............................................................................ 692 7.11.7. VC Resource Status Register .............................................................................. 694 7.11.8. VC Arbitration Table .......................................................................................... 695 7.11.9.
Port Arbitration Table .................................................................................... 696 7.11.10. 7.12. DEVICE SERIAL NUMBER CAPABILITY ......................................................................... 698
Device Serial Number Extended Capability Header (Offset 00h) ...................... 698 7.12.1.
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Serial Number Register (Offset 04h)................................................................... 699 7.12.2. 7.13. PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ................................ 700
Root Complex Link Declaration Extended Capability Header (Offset 00h) ...... 702 7.13.1. Element Self Description (Offset 04h) ................................................................ 703 7.13.2. Link Entries ......................................................................................................... 704 7.13.3.
7.14. PCI EXPRESS ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY ....................... 708 Root Complex Internal Link Control Extended Capability Header (Offset 00h) 708 7.14.1. Root Complex Link Capabilities Register (Offset 04h) ....................................... 709 7.14.2. Root Complex Link Control Register (Offset 08h) .............................................. 713 7.14.3. Root Complex Link Status Register (Offset 0Ah) ................................................ 714 7.14.4.
7.15. POWER BUDGETING CAPABILITY ................................................................................. 715 Power Budgeting Extended Capability Header (Offset 00h) .............................. 716 7.15.1. Data Select Register (Offset 04h) ....................................................................... 716 7.15.2. Data Register (Offset 08h) .................................................................................. 717 7.15.3. Power Budget Capability Register (Offset 0Ch) ................................................. 719 7.15.4.
7.16. ACS EXTENDED CAPABILITY ...................................................................................... 720 ACS Extended Capability Header (Offset 00h) .................................................. 720 7.16.1. ACS Capability Register (Offset 04h) ................................................................. 721 7.16.2. ACS Control Register (Offset 06h) ..................................................................... 722 7.16.3. Egress Control Vector (Offset 08h) .................................................................... 723 7.16.4.
7.17. PCI EXPRESS ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY 725
Root Complex Event Collector Endpoint Association Extended Capability Header 7.17.1. (Offset 00h) ......................................................................................................................... 725
Association Bitmap for Root Complex Integrated Endpoints (Offset 04h) ......... 726 7.17.2. 7.18. MULTI-FUNCTION VIRTUAL CHANNEL CAPABILITY .................................................... 727
MFVC Extended Capability Header (Offset 00h) ............................................... 728 7.18.1. Port VC Capability Register 1 (Offset 04h) ........................................................ 728 7.18.2. Port VC Capability Register 2 (Offset 08h) ........................................................ 730 7.18.3. Port VC Control Register (Offset 0Ch) ............................................................... 731 7.18.4. Port VC Status Register (Offset 0Eh) .................................................................. 731 7.18.5. VC Resource Capability Register ....................................................................... 732 7.18.6. VC Resource Control Register ............................................................................ 734 7.18.7. VC Resource Status Register .............................................................................. 736 7.18.8. VC Arbitration Table .......................................................................................... 737 7.18.9.
Function Arbitration Table ............................................................................. 737 7.18.10. 7.19. VENDOR-SPECIFIC CAPABILITY ................................................................................... 739
Vendor-Specific Extended Capability Header (Offset 00h) ................................ 740 7.19.1. Vendor-Specific Header (Offset 04h) .................................................................. 741 7.19.2.
7.20. RCRB HEADER CAPABILITY ....................................................................................... 742 RCRB Header Extended Capability Header (Offset 00h) ................................... 742 7.20.1. Vendor ID (Offset 04h) and Device ID (Offset 06h) ........................................... 743 7.20.2. RCRB Capabilities (Offset 08h) .......................................................................... 744 7.20.3. RCRB Control (Offset 0Ch) ................................................................................ 744 7.20.4.
7.21. MULTICAST CAPABILITY ............................................................................................. 745 Multicast Extended Capability Header (Offset 00h) .......................................... 745 7.21.1.
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Multicast Capability Register (Offset 04h) ......................................................... 746 7.21.2. Multicast Control Register (Offset 06h) ............................................................. 747 7.21.3. MC_Base_Address Register (Offset 08h) ........................................................... 748 7.21.4. MC_Receive Register (Offset 10h)...................................................................... 748 7.21.5. MC_Block_All Register (Offset 18h) .................................................................. 749 7.21.6. MC_Block_Untranslated Register (Offset 20h) .................................................. 749 7.21.7. MC_Overlay_BAR (Offset 28h) .......................................................................... 750 7.21.8.
7.22. RESIZABLE BAR CAPABILITY ...................................................................................... 751 Resizable BAR Extended Capability Header (Offset 00h) .................................. 753 7.22.1. Resizable BAR Capability Register ..................................................................... 753 7.22.2. Resizable BAR Control Register ......................................................................... 755 7.22.3.
7.23. ARI CAPABILITY ......................................................................................................... 756 ARI Capability Header (Offset 00h) ................................................................... 757 7.23.1. ARI Capability Register (Offset 04h) .................................................................. 757 7.23.2. ARI Control Register (Offset 06h) ...................................................................... 758 7.23.3.
7.24. DYNAMIC POWER ALLOCATION (DPA) CAPABILITY ................................................... 759 DPA Extended Capability Header (Offset 00h) .................................................. 759 7.24.1. DPA Capability Register (Offset 04h) ................................................................ 760 7.24.2. DPA Latency Indicator Register (Offset 08h) ..................................................... 761 7.24.3. DPA Status Register (Offset 0Ch) ....................................................................... 761 7.24.4. DPA Control Register (Offset 0Eh) .................................................................... 762 7.24.5. DPA Power Allocation Array ............................................................................. 762 7.24.6.
7.25. LATENCY TOLERANCE REPORTING (LTR) CAPABILITY ............................................... 763 LTR Extended Capability Header (Offset 00h) ................................................... 763 7.25.1. Max Snoop Latency Register (Offset 04h) .......................................................... 764 7.25.2. Max No-Snoop Latency Register (Offset 06h) .................................................... 764 7.25.3.
7.26. TPH REQUESTER CAPABILITY ..................................................................................... 765 TPH Requester Extended Capability Header (Offset 00h) ................................. 766 7.26.1. TPH Requester Capability Register (Offset 04h) ................................................ 766 7.26.2. TPH Requester Control Register (Offset 08h) .................................................... 768 7.26.3. TPH ST Table (Starting from Offset 0Ch) .......................................................... 769 7.26.4.
7.27. SECONDARY PCI EXPRESS EXTENDED CAPABILITY .................................................... 770 Secondary PCI Express Extended Capability Header (Offset 00h) .................... 770 7.27.1. Link Control 3 Register (Offset 04h) .................................................................. 771 7.27.2. Lane Error Status Register (Offset 08h) ............................................................. 772 7.27.3. Lane Equalization Control Register (Offset 0Ch) .............................................. 773 7.27.4. Lane Equalization Control 2 Register (Offset TBD)........................................... 777 7.27.5.
7.28. M-PCIE EXTENDED CAPABILITY ................................................................................. 781 M-PCIe Extended Capability Header (Offset 00h) ............................................. 781 7.28.1. M-PCIe Capabilities Register (Offset 04h) ......................................................... 783 7.28.2. M-PCIe Control Register (Offset 08h) ................................................................ 784 7.28.3. M-PCIe Status Register (Offset 0Ch) .................................................................. 785 7.28.4. M-PCIe LANE Error Status Register (Offset 10h) ............................................. 786 7.28.5. M-PCIe Phy Control Address Register (Offset 14h) ........................................... 787 7.28.6. M-PCIe Phy Control Data Register (Offset 18h) ............................................... 788 7.28.7.
7.29. PASID EXTENDED CAPABILITY STRUCTURE ............................................................... 789
12
PASID Extended Capability Header (Offset 00h) .............................................. 790 7.29.1. PASID Capability Register (Offset 04h) ............................................................. 791 7.29.2. PASID Control Register (Offset 06h) ................................................................. 792 7.29.3.
7.30. LNR EXTENDED CAPABILITY ...................................................................................... 793 LNR Extended Capability Header (Offset 00h) .................................................. 793 7.30.1. LNR Capability Register (Offset 04h) ................................................................. 794 7.30.2. LNR Control Register (Offset 04h) ..................................................................... 795 7.30.3.
7.31. DPC EXTENDED CAPABILITY ...................................................................................... 795 DPC Extended Capability Header (Offset 00h) .................................................. 797 7.31.1. DPC Capability Register (Offset 04h) ................................................................ 798 7.31.2. DPC Control Register (Offset 06h)..................................................................... 800 7.31.3. DPC Status Register (Offset 08h) ....................................................................... 802 7.31.4. DPC Error Source ID Register (Offset 0Ah) ...................................................... 804 7.31.5. RP PIO Status Register (Offset 0Ch) .................................................................. 805 7.31.6. RP PIO Mask Register (Offset 10h) .................................................................... 806 7.31.7. RP PIO Severity Register (Offset 14h) ................................................................ 807 7.31.8. RP PIO SysError Register (Offset 18h) .............................................................. 808 7.31.9.
RP PIO Exception Register (Offset 1Ch) ........................................................ 809 7.31.10. RP PIO Header Log Register (Offset 20h) ..................................................... 810 7.31.11. RP PIO ImpSpec Log Register (Offset 30h) ................................................... 810 7.31.12. RP PIO TLP Prefix Log Register (Offset 34h) ................................................ 811 7.31.13.
7.32. PRECISION TIME MANAGEMENT (PTM) CAPABILITY .................................................. 812 PTM Extended Capability Header (Offset 00h) .................................................. 813 7.32.1. PTM Capability Register (Offset 04h) ................................................................ 814 7.32.2. PTM Control Register (Offset 08h)..................................................................... 815 7.32.3.
7.33. L1 PM SUBSTATES EXTENDED CAPABILITY ................................................................ 817 L1 PM Substates Extended Capability Header (Offset 00h) .............................. 817 7.33.1. L1 PM Substates Capabilities Register (Offset 04h) .......................................... 818 7.33.2. L1 PM Substates Control 1 Register (Offset 08h) .............................................. 820 7.33.3. L1 PM Substates Control 2 Register (Offset 0Ch) .............................................. 822 7.33.4.
7.34. FUNCTION READINESS STATUS (FRS) QUEUING EXTENDED CAPABILITY ................... 823 Function Readiness Status (FRS) Queuing Extended Capability Header (Offset 7.34.1.
00h) 824 FRS Queuing Capability Register (Offset 04h) .................................................. 825 7.34.2. FRS Queuing Status Register (Offset 08h).......................................................... 826 7.34.3. FRS Queuing Control Register (Offset 0Ah) ...................................................... 826 7.34.4. FRS Message Queue Register (Offset 0Ch) ........................................................ 827 7.34.5.
7.35. READINESS TIME REPORTING EXTENDED CAPABILITY ................................................ 828 Readiness Time Reporting Extended Capability Header (Offset 00h) ............... 830 7.35.1. Readiness Time Reporting 1 (Offset 04h) ........................................................... 831 7.35.2. Readiness Time Reporting 2 (Offset 08h) ........................................................... 832 7.35.3.
8. M-PCIE LOGICAL SUB-BLOCK ................................................................................. 833
8.1. PHY REQUIREMENTS ................................................................................................... 835 8.2. CONFIGURATION .......................................................................................................... 836
Link Discovery and Configuration...................................................................... 836 8.2.1. Attributes ............................................................................................................. 837 8.2.2.
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Remote Register Access Protocol (RRAP): ......................................................... 850 8.2.3. 8.3. SYMBOL ENCODING, FRAMING AND SCRAMBLING ...................................................... 862
8b/10b Decode Rules .......................................................................................... 862 8.3.1. Framing and Application of Symbols to LANES ................................................. 862 8.3.2. Data Scrambling ................................................................................................. 863 8.3.3.
8.4. LINK INITIALIZATION AND TRAINING ........................................................................... 863 Training Sequence (TS) Ordered Sets................................................................. 864 8.4.1. Electrical Idle ...................................................................................................... 870 8.4.2. EIEOS for M-PCIe .............................................................................................. 870 8.4.3. Lane Polarity Inversion ...................................................................................... 870 8.4.4. Fast Training Sequence (FTS) ............................................................................ 870 8.4.5. LINK Data RATE ................................................................................................ 871 8.4.6. LINK Width ......................................................................................................... 871 8.4.7. LANE-to-LANE De-skew .................................................................................... 871 8.4.8. LINK Training and Status State Machine (LTSSM) ........................................... 871 8.4.9.
Entry to HIBERN8 .............................................................................................. 893 8.4.10. 8.5. RECEIVER ERROR ......................................................................................................... 893 8.6. CLOCK TOLERANCE COMPENSATION ........................................................................... 894 8.7. DYNAMIC LINK BANDWIDTH MANAGEMENT ............................................................. 894
LINK Rate Series and Speed Management ......................................................... 894 8.7.1. LINK Width Management ................................................................................... 895 8.7.2. Dynamic LINK Re-Configuration ....................................................................... 895 8.7.3.
8.8. M-PHY REGISTERS ..................................................................................................... 898 M-PHY Capability Registers ............................................................................... 898 8.8.1. M-PHY Configuration Attributes ........................................................................ 906 8.8.2.
9. PHYSICAL LAYER ELECTRICAL SUB-BLOCK SPECIFICATION .................... 907
9.1. ELECTRICAL SPECIFICATION ORGANIZATION............................................................... 907 9.2. INTEROPERABILITY CRITERIA ...................................................................................... 908
Data Rates ........................................................................................................... 908 9.2.1. Refclk Architectures ............................................................................................ 908 9.2.2.
9.3. TRANSMITTER SPECIFICATION ..................................................................................... 908 Measurement Setup for Characterizing Transmitters ......................................... 908 9.3.1. Voltage Level Definitions .................................................................................... 910 9.3.2. Tx Voltage Parameters ....................................................................................... 911 9.3.3. Transmitter Margining ....................................................................................... 919 9.3.4. Tx Jitter Parameters ........................................................................................... 920 9.3.5. Tx and Rx Return Loss ........................................................................................ 929 9.3.6. Transmitter PLL Bandwidth and Peaking .......................................................... 930 9.3.7. Data Rate Independent Tx Parameters ............................................................... 931 9.3.8.
9.4. RECEIVER SPECIFICATIONS .......................................................................................... 933 Receiver Stressed Eye Specification ................................................................... 933 9.4.1. Stressed Eye Test ................................................................................................. 938 9.4.2. Common receiver parameters ............................................................................. 944 9.4.3. Low Frequency and Miscellaneous Signaling Requirements ............................. 947 9.4.4.
9.5. CHANNEL TOLERANCING ............................................................................................. 949 Channel Compliance Testing .............................................................................. 949 9.5.1.
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9.6. REFCLK SPECIFICATIONS ............................................................................................. 958 Refclk Test Setup ................................................................................................. 958 9.6.1. Data Rate Independent Refclk Parameters ......................................................... 959 9.6.2. Refclk Architectures Supported ........................................................................... 960 9.6.3. Filtering Functions Applied to Raw Data ........................................................... 960 9.6.4. Common Refclk Rx Architecture (CC) ................................................................ 961 9.6.5. Data Clocked Rx Architecture (DC) ................................................................... 964 9.6.6. Independent Refclks (IR) ..................................................................................... 965 9.6.7. Jitter Limits for Refclk Architectures .................................................................. 967 9.6.8.
A. ISOCHRONOUS APPLICATIONS ................................................................................... 969
A.1. INTRODUCTION ............................................................................................................ 969 A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS ........................................... 971
A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot ............................. 972 A.2.2. Isochronous Payload Size ................................................................................... 973 A.2.3. Isochronous Bandwidth Allocation ..................................................................... 973 A.2.4. Isochronous Transaction Latency ....................................................................... 974 A.2.5. An Example Illustrating Isochronous Parameters .............................................. 975
A.3. ISOCHRONOUS TRANSACTION RULES ........................................................................... 976 A.4. TRANSACTION ORDERING ............................................................................................ 976 A.5. ISOCHRONOUS DATA COHERENCY ............................................................................... 976 A.6. FLOW CONTROL ........................................................................................................... 977 A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION ....................................................... 977
A.7.1. Isochronous Bandwidth of PCI Express Links.................................................... 977 A.7.2. Isochronous Bandwidth of Endpoints ................................................................. 977 A.7.3. Isochronous Bandwidth of Switches ................................................................... 977 A.7.4. Isochronous Bandwidth of Root Complex........................................................... 978
A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS ..................................................... 978 A.8.1. An Endpoint as a Requester ................................................................................ 978 A.8.2. An Endpoint as a Completer ............................................................................... 978 A.8.3. Switches............................................................................................................... 979 A.8.4. Root Complex ...................................................................................................... 980
B. SYMBOL ENCODING ...................................................................................................... 981
C. PHYSICAL LAYER APPENDIX ...................................................................................... 990
C.1. 8B/10B DATA SCRAMBLING EXAMPLE ......................................................................... 990 C.2. 128B/130B DATA SCRAMBLING EXAMPLE ................................................................... 996
D. REQUEST DEPENDENCIES ............................................................................................ 999
E.1. INTRODUCTION .......................................................................................................... 1002 E.2. POTENTIAL BENEFITS WITH IDO USE ........................................................................ 1003
E.2.1. Benefits for MFD/RP Direct Connect ............................................................... 1003 E.2.2. Benefits for Switched Environments ................................................................. 1003 E.2.3. Benefits for Integrated Endpoints ..................................................................... 1004 E.2.4. IDO Use in Conjunction with RO ..................................................................... 1004
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E.3. WHEN TO USE IDO .................................................................................................... 1004 E.4. WHEN NOT TO USE IDO ............................................................................................ 1005
E.4.1. When Not to Use IDO with Endpoints .............................................................. 1005 E.4.2. When Not to Use IDO with Root Ports ............................................................. 1005
E.5. SOFTWARE CONTROL OF IDO USE ............................................................................. 1006 E.5.1. Software Control of Endpoint IDO Use ............................................................ 1006 E.5.2. Software Control of Root Port IDO Use ........................................................... 1007
F. MESSAGE CODE USAGE .............................................................................................. 1008
G. PROTOCOL MULTIPLEXING ................................................................................... 1010
G.1. PROTOCOL MULTIPLEXING INTERACTIONS WITH PCI EXPRESS ................................. 1013 G.2. PMUX PACKETS ........................................................................................................ 1019 G.3. PMUX PACKET LAYOUT ........................................................................................... 1020
G.3.1. PMUX Packet Layout for 8b10b Encoding ...................................................... 1020 G.3.2. PMUX Packet Layout at 128b/130b Encoding ................................................. 1022
G.4. PMUX CONTROL ....................................................................................................... 1025 G.5. PMUX EXTENDED CAPABILITY ................................................................................. 1025
G.5.1. PCI Express Extended Header (Offset 00h) ..................................................... 1026 G.5.2. PMUX Capability Register (Offset 04h) ........................................................... 1027 G.5.3. PMUX Control Register (Offset 08h) ............................................................... 1028 G.5.4. PMUX Status Register (Offset 0Ch) ................................................................. 1030 G.5.5. PMUX Protocol Array (Offsets 10h Through 48h) .......................................... 1033
H. M-PCIE TIMING DIAGRAMS .................................................................................... 1035
H.1. INIT TO L0 .................................................................................................................. 1036 H.2. L0 WITH TRANSMITTER IN STALL ............................................................................ 1037 H.3. L0 TO L1 .................................................................................................................... 1038 H.4. DOWNSTREAM PORT INITIATED LINK BANDWIDTH CHANGE ................................... 1039 H.5. UPSTREAM PORT INITIATED LINK BANDWIDTH CHANGE ......................................... 1040
I. M-PCIE COMPLIANCE PATTERNS ......................................................................... 1041
I.1. RPAT ........................................................................................................................ 1041 I.2. RPAT VARIATION BY LANE ...................................................................................... 1042 I.3. CONTINUOUS MODE CRPAT ..................................................................................... 1042 I.4. BURST MODE CRPAT ............................................................................................... 1043
ACKNOWLEDGEMENTS ...................................................................................................... 1044
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Figures FIGURE 1-1: PCI EXPRESS LINK .................................................................................................... 49 FIGURE 1-2: EXAMPLE TOPOLOGY ................................................................................................ 50 FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 54 FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 56 FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 57 FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER .............................. 62 FIGURE 2-2: SERIAL VIEW OF A TLP ............................................................................................. 65 FIGURE 2-3: GENERIC TLP FORMAT ............................................................................................. 66 FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 67 FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS .................................................................... 68 FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD ................... 73 FIGURE 2-7: 64-BIT ADDRESS ROUTING ........................................................................................ 75 FIGURE 2-8: 32-BIT ADDRESS ROUTING ........................................................................................ 75 FIGURE 2-9: ID ROUTING WITH 4 DW HEADER ............................................................................ 77 FIGURE 2-10: ID ROUTING WITH 3 DW HEADER .......................................................................... 78 FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER ....................................................... 79 FIGURE 2-12: TRANSACTION DESCRIPTOR .................................................................................... 81 FIGURE 2-13: TRANSACTION ID .................................................................................................... 82 FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 84 FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY ........................ 88 FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY ........................ 88 FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS .............................................. 89 FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ........................ 90 FIGURE 2-19: TPH TLP PREFIX .................................................................................................... 91 FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER ............................................. 91 FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER ............................................. 92 FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER ......................... 93 FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS ..... 93 FIGURE 2-24: MESSAGE REQUEST HEADER .................................................................................. 95 FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES ......................................................... 105 FIGURE 2-26: HEADER FOR PCI-SIG-DEFINED VDMS ................................................................ 106 FIGURE 2-27: LN MESSAGE ......................................................................................................... 108 FIGURE 2-28: DRS MESSAGE ...................................................................................................... 109 FIGURE 2-29: FRS MESSAGE ...................................................................................................... 111 FIGURE 2-30: LTR MESSAGE ...................................................................................................... 112 FIGURE 2-31: OBFF MESSAGE ................................................................................................... 113 FIGURE 2-32: PTM REQUEST/RESPONSE MESSAGE ..................................................................... 114 FIGURE 2-33: PTM RESPONSED MESSAGE (4 DW HEADER AND 1 DW PAYLOAD) ...................... 115 FIGURE 2-34: COMPLETION HEADER FORMAT ............................................................................ 116 FIGURE 2-35: (NON-ARI) COMPLETER ID .................................................................................. 117 FIGURE 2-36: ARI COMPLETER ID .............................................................................................. 117 FIGURE 2-37: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................. 124 FIGURE 2-38: FLOWCHART FOR SWITCH HANDLING OF TLPS ..................................................... 126
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FIGURE 2-39: FLOWCHART FOR HANDLING OF RECEIVED REQUEST ........................................... 131 FIGURE 2-40: VIRTUAL CHANNEL CONCEPT – AN ILLUSTRATION .............................................. 148 FIGURE 2-41: VIRTUAL CHANNEL CONCEPT – SWITCH INTERNALS (UPSTREAM FLOW) ............. 148 FIGURE 2-42: AN EXAMPLE OF TC/VC CONFIGURATIONS .......................................................... 151 FIGURE 2-43: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE COMPLETER ..................... 152 FIGURE 2-44: CALCULATION OF 32-BIT ECRC FOR TLP END TO END DATA INTEGRITY
PROTECTION ........................................................................................................................ 168 FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK LAYER ................................ 176 FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE MACHINE .................................. 179 FIGURE 3-3: VC0 FLOW CONTROL INITIALIZATION EXAMPLE WITH 8B/10B ENCODING-BASED
FRAMING ............................................................................................................................. 184 FIGURE 3-4: DLLP TYPE AND CRC FIELDS ................................................................................ 185 FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND NAK ....................................... 187 FIGURE 3-6: DATA LINK LAYER PACKET FORMAT FOR INITFC1 ................................................ 187 FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR INITFC2 ................................................ 187 FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR UPDATEFC ............................................ 188 FIGURE 3-9: PM DATA LINK LAYER PACKET FORMAT ............................................................... 188 FIGURE 3-10: VENDOR SPECIFIC DATA LINK LAYER PACKET FORMAT ...................................... 188 FIGURE 3-11: DIAGRAM OF CRC CALCULATION FOR DLLPS ..................................................... 189 FIGURE 3-12: TLP WITH LCRC AND TLP SEQUENCE NUMBER APPLIED ................................... 190 FIGURE 3-13: TLP FOLLOWING APPLICATION OF TLP SEQUENCE NUMBER AND RESERVED BITS
............................................................................................................................................. 192 FIGURE 3-14: CALCULATION OF LCRC ...................................................................................... 194 FIGURE 3-15: RECEIVED DLLP ERROR CHECK FLOWCHART ...................................................... 202 FIGURE 3-16: ACK/NAK DLLP PROCESSING FLOWCHART .......................................................... 203 FIGURE 3-17: RECEIVE DATA LINK LAYER HANDLING OF TLPS ................................................ 207 FIGURE 4-1: LAYERING DIAGRAM HIGHLIGHTING PHYSICAL LAYER .......................................... 213 FIGURE 4-2: CHARACTER TO SYMBOL MAPPING ......................................................................... 214 FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1 EXAMPLE ............................ 215 FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4 EXAMPLE ............................ 215 FIGURE 4-5: TLP WITH FRAMING SYMBOLS APPLIED ................................................................. 218 FIGURE 4-6: DLLP WITH FRAMING SYMBOLS APPLIED .............................................................. 219 FIGURE 4-7: FRAMED TLP ON A X1 LINK .................................................................................... 219 FIGURE 4-8: FRAMED TLP ON A X2 LINK .................................................................................... 220 FIGURE 4-9: FRAMED TLP ON A X4 LINK .................................................................................... 220 FIGURE 4-10: LFSR WITH SCRAMBLING POLYNOMIAL ............................................................... 222 FIGURE 4-11: EXAMPLE OF BIT TRANSMISSION ORDER IN A X1 LINK SHOWING 130 BITS OF A
BLOCK ................................................................................................................................. 223 FIGURE 4-12: EXAMPLE OF BIT PLACEMENT IN A X4 LINK WITH ONE BLOCK PER LANE ............ 223 FIGURE 4-13: LAYOUT OF FRAMING TOKENS .............................................................................. 227 FIGURE 4-14: TLP AND DLLP LAYOUT ...................................................................................... 229 FIGURE 4-15: PACKET TRANSMISSION IN A X8 LINK ................................................................... 229 FIGURE 4-16: NULLIFIED TLP LAYOUT IN A X8 LINK WITH OTHER PACKETS ............................. 230 FIGURE 4-17: SKP ORDERED SET OF LENGTH 66-BIT IN A X8 LINK ............................................ 230 FIGURE 4-18: LFSR WITH SCRAMBLING POLYNOMIAL IN 8.0 GT/S AND ABOVE DATA RATE .... 238 FIGURE 4-19: ALTERNATE IMPLEMENTATION OF THE LFSR FOR DESCRAMBLING ...................... 240
18
FIGURE 4-20: 8.0 GT/S EQUALIZATION FLOW ............................................................................. 248 FIGURE 4-21: 16.0 GT/S EQUALIZATION FLOW ........................................................................... 249 FIGURE 4-22: ELECTRICAL IDLE EXIT ORDERED SET FOR 8.0 GT/S AND ABOVE DATA RATES ... 260 FIGURE 4-23: MAIN STATE DIAGRAM FOR LINK TRAINING AND STATUS STATE MACHINE ........ 275 FIGURE 4-24: DETECT SUBSTATE MACHINE ............................................................................... 277 FIGURE 4-25: POLLING SUBSTATE MACHINE .............................................................................. 286 FIGURE 4-26: CONFIGURATION SUBSTATE MACHINE .................................................................. 301 FIGURE 4-27: RECOVERY SUBSTATE MACHINE ........................................................................... 325 FIGURE 4-28: L0S SUBSTATE MACHINE ...................................................................................... 332 FIGURE 4-29: L1 SUBSTATE MACHINE ........................................................................................ 334 FIGURE 4-30: L2 SUBSTATE MACHINE ........................................................................................ 336 FIGURE 4-31: LOOPBACK SUBSTATE MACHINE ........................................................................... 341 FIGURE 5-1: LINK POWER MANAGEMENT STATE FLOW DIAGRAM ............................................. 357 FIGURE 5-2: ENTRY INTO THE L1 LINK STATE ............................................................................ 365 FIGURE 5-3: EXIT FROM L1 LINK STATE INITIATED BY UPSTREAM COMPONENT ........................ 368 FIGURE 5-4: CONCEPTUAL DIAGRAMS SHOWING TWO EXAMPLE CASES OF WAKE# ROUTING . 371 FIGURE 5-5: A CONCEPTUAL PME CONTROL STATE MACHINE .................................................. 375 FIGURE 5-6: L1 TRANSITION SEQUENCE ENDING WITH A REJECTION (L0S ENABLED) ................ 388 FIGURE 5-7: L1 SUCCESSFUL TRANSITION SEQUENCE ................................................................ 389 FIGURE 5-8: EXAMPLE OF L1 EXIT LATENCY COMPUTATION ..................................................... 391 FIGURE 5-9: STATE DIAGRAM FOR L1 PM SUBSTATES ................................................................ 397 FIGURE 5-10: DOWNSTREAM PORT WITH A SINGLE PLL ............................................................. 398 FIGURE 5-11: MULTIPLE DOWNSTREAM PORTS WITH A SHARED PLL ......................................... 399 FIGURE 5-12: EXAMPLE: L1.1 WAVEFORMS ILLUSTRATING UPSTREAM PORT INITIATED EXIT ... 401 FIGURE 5-13: EXAMPLE: L1.1 WAVEFORMS ILLUSTRATING DOWNSTREAM PORT INITIATED EXIT
............................................................................................................................................. 402 FIGURE 5-14: L1.2 SUBSTATES .................................................................................................... 403 FIGURE 5-15: EXAMPLE: ILLUSTRATION OF BOUNDARY CONDITION DUE TO DIFFERENT SAMPLING
OF CLKREQ# ...................................................................................................................... 404 FIGURE 5-16: EXAMPLE: L1.2 WAVEFORMS ILLUSTRATING UPSTREAM PORT INITIATED EXIT ... 406 FIGURE 5-17: EXAMPLE: L1.2 WAVEFORMS ILLUSTRATING DOWNSTREAM PORT INITIATED EXIT
............................................................................................................................................. 406 FIGURE 6-1: ERROR CLASSIFICATION .......................................................................................... 416 FIGURE 6-2: FLOWCHART SHOWING SEQUENCE OF DEVICE ERROR SIGNALING AND LOGGING
OPERATIONS ........................................................................................................................ 433 FIGURE 6-3: PSEUDO LOGIC DIAGRAM FOR ERROR MESSAGE CONTROLS .................................. 434 FIGURE 6-4: TC FILTERING EXAMPLE ......................................................................................... 454 FIGURE 6-5: TC TO VC MAPPING EXAMPLE ............................................................................... 455 FIGURE 6-6: AN EXAMPLE OF TRAFFIC FLOW ILLUSTRATING INGRESS AND EGRESS .................. 456 FIGURE 6-7: AN EXAMPLE OF DIFFERENTIATED TRAFFIC FLOW THROUGH A SWITCH ................ 457 FIGURE 6-8: SWITCH ARBITRATION STRUCTURE ......................................................................... 458 FIGURE 6-9: VC ID AND PRIORITY ORDER – AN EXAMPLE ......................................................... 459 FIGURE 6-10: MULTI-FUNCTION ARBITRATION MODEL .............................................................. 462 FIGURE 6-11: ROOT COMPLEX REPRESENTED AS A SINGLE COMPONENT ................................... 496 FIGURE 6-12: ROOT COMPLEX REPRESENTED AS MULTIPLE COMPONENTS ................................ 497 FIGURE 6-13: EXAMPLE SYSTEM TOPOLOGY WITH ARI DEVICES ............................................... 510
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FIGURE 6-14: SEGMENTATION OF THE MULTICAST ADDRESS RANGE ......................................... 512 FIGURE 6-15: LATENCY FIELDS FORMAT FOR LTR MESSAGES ................................................... 530 FIGURE 6-16: CLKREQ# AND CLOCK POWER MANAGEMENT ................................................... 534 FIGURE 6-17: USE OF LTR AND CLOCK POWER MANAGEMENT .................................................. 535 FIGURE 6-18: CODES AND EQUIVALENT WAKE# PATTERNS ...................................................... 537 FIGURE 6-19: EXAMPLE PLATFORM TOPOLOGY SHOWING A LINK WHERE OBFF IS CARRIED BY
MESSAGES ........................................................................................................................... 538 FIGURE 6-20. PASID TLP PREFIX: ....................................................................................... 541 FIGURE 6-21: SAMPLE SYSTEM BLOCK DIAGRAM ....................................................................... 545 FIGURE 6-22: LN PROTOCOL BASIC OPERATION ......................................................................... 546 FIGURE 6-23: EXAMPLE SYSTEM TOPOLOGIES USING PTM ......................................................... 552 FIGURE 6-24: PRECISION TIME MEASUREMENT LINK PROTOCOL ................................................ 553 FIGURE 6-25: PRECISION TIME MEASUREMENT EXAMPLE ........................................................... 555 FIGURE 6-26: PTM REQUESTER OPERATION ............................................................................... 558 FIGURE 6-27: PTM TIMESTAMP CAPTURE EXAMPLE ................................................................... 561 FIGURE 7-1: PCI EXPRESS ROOT COMPLEX DEVICE MAPPING ................................................... 566 FIGURE 7-2: PCI EXPRESS SWITCH DEVICE MAPPING ................................................................ 566 FIGURE 7-3: PCI EXPRESS CONFIGURATION SPACE LAYOUT ...................................................... 567 FIGURE 7-4: COMMON CONFIGURATION SPACE HEADER ............................................................ 578 FIGURE 7-5: TYPE 0 CONFIGURATION SPACE HEADER ................................................................ 585 FIGURE 7-6: TYPE 1 CONFIGURATION SPACE HEADER ................................................................ 587 FIGURE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER ..................................................... 591 FIGURE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER .............................................. 592 FIGURE 7-9: VECTOR CONTROL FOR MSI-X TABLE ENTRIES ..................................................... 593 FIGURE 7-10: PCI EXPRESS CAPABILITY STRUCTURE ................................................................. 595 FIGURE 7-11: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................ 595 FIGURE 7-12: PCI EXPRESS CAPABILITIES REGISTER ................................................................. 596 FIGURE 7-13: DEVICE CAPABILITIES REGISTER .......................................................................... 598 FIGURE 7-14: DEVICE CONTROL REGISTER ................................................................................. 603 FIGURE 7-15: DEVICE STATUS REGISTER .................................................................................... 610 FIGURE 7-16: LINK CAPABILITIES REGISTER ............................................................................... 612 FIGURE 7-17: LINK CONTROL REGISTER ..................................................................................... 617 FIGURE 7-18: LINK STATUS REGISTER ........................................................................................ 626 FIGURE 7-19: SLOT CAPABILITIES REGISTER .............................................................................. 629 FIGURE 7-20: SLOT CONTROL REGISTER ..................................................................................... 631 FIGURE 7-21: SLOT STATUS REGISTER ....................................................................................... 635 FIGURE 7-22: ROOT CONTROL REGISTER .................................................................................... 637 FIGURE 7-23: ROOT CAPABILITIES REGISTER.............................................................................. 638 FIGURE 7-24: ROOT STATUS REGISTER ....................................................................................... 639 FIGURE 7-25: DEVICE CAPABILITIES 2 REGISTER ........................................................................ 640 FIGURE 7-26: DEVICE CONTROL 2 REGISTER .............................................................................. 646 FIGURE 7-27: LINK CAPABILITIES 2 REGISTER ............................................................................ 650 FIGURE 7-28: LINK CONTROL 2 REGISTER .................................................................................. 653 FIGURE 7-29: LINK STATUS 2 REGISTER ..................................................................................... 658 FIGURE 7-30: PCI EXPRESS EXTENDED CONFIGURATION SPACE LAYOUT .................................. 663 FIGURE 7-31: PCI EXPRESS EXTENDED CAPABILITY HEADER .................................................... 664
20
FIGURE 7-32: PCI EXPRESS ADVANCED ERROR REPORTING EXTENDED CAPABILITY STRUCTURE ............................................................................................................................................. 666
FIGURE 7-33: ADVANCED ERROR REPORTING EXTENDED CAPABILITY HEADER ........................ 667 FIGURE 7-34: UNCORRECTABLE ERROR STATUS REGISTER ........................................................ 668 FIGURE 7-35: UNCORRECTABLE ERROR MASK REGISTER ........................................................... 670 FIGURE 7-36: UNCORRECTABLE ERROR SEVERITY REGISTER ..................................................... 672 FIGURE 7-37: CORRECTABLE ERROR STATUS REGISTER ............................................................. 674 FIGURE 7-38: CORRECTABLE ERROR MASK REGISTER ............................................................... 675 FIGURE 7-39: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER ................................ 676 FIGURE 7-40: HEADER LOG REGISTER ........................................................................................ 678 FIGURE 7-41: ROOT ERROR COMMAND REGISTER ...................................................................... 678 FIGURE 7-42: ROOT ERROR STATUS REGISTER ........................................................................... 680 FIGURE 7-43: ERROR SOURCE IDENTIFICATION REGISTER .......................................................... 682 FIGURE 7-44: TLP PREFIX LOG REGISTER .................................................................................. 683 FIGURE 7-45: PCI EXPRESS VIRTUAL CHANNEL CAPABILITY STRUCTURE ................................. 684 FIGURE 7-46: VIRTUAL CHANNEL EXTENDED CAPABILITY HEADER .......................................... 685 FIGURE 7-47: PORT VC CAPABILITY REGISTER 1 ....................................................................... 686 FIGURE 7-48: PORT VC CAPABILITY REGISTER 2 ....................................................................... 687 FIGURE 7-49: PORT VC CONTROL REGISTER .............................................................................. 688 FIGURE 7-50: PORT VC STATUS REGISTER ................................................................................. 689 FIGURE 7-51: VC RESOURCE CAPABILITY REGISTER .................................................................. 690 FIGURE 7-52: VC RESOURCE CONTROL REGISTER ...................................................................... 692 FIGURE 7-53: VC RESOURCE STATUS REGISTER ......................................................................... 694 FIGURE 7-54: EXAMPLE VC ARBITRATION TABLE WITH 32 PHASES ........................................... 696 FIGURE 7-55: EXAMPLE PORT ARBITRATION TABLE WITH 128 PHASES AND 2-BIT TABLE ENTRIES
............................................................................................................................................. 697 FIGURE 7-56: PCI EXPRESS DEVICE SERIAL NUMBER CAPABILITY STRUCTURE ......................... 698 FIGURE 7-57: DEVICE SERIAL NUMBER EXTENDED CAPABILITY HEADER .................................. 699 FIGURE 7-58: SERIAL NUMBER REGISTER ................................................................................... 700 FIGURE 7-59: PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ......................... 701 FIGURE 7-60: ROOT COMPLEX LINK DECLARATION EXTENDED CAPABILITY HEADER ............... 702 FIGURE 7-61: ELEMENT SELF DESCRIPTION REGISTER ............................................................... 703 FIGURE 7-62: LINK ENTRY .......................................................................................................... 704 FIGURE 7-63: LINK DESCRIPTION REGISTER ............................................................................... 704 FIGURE 7-64: LINK ADDRESS FOR LINK TYPE 0 .......................................................................... 706 FIGURE 7-65: LINK ADDRESS FOR LINK TYPE 1 .......................................................................... 707 FIGURE 7-66: ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY ...................................... 708 FIGURE 7-67: ROOT INTERNAL LINK CONTROL EXTENDED CAPABILITY HEADER ...................... 708 FIGURE 7-68: ROOT COMPLEX LINK CAPABILITIES REGISTER .................................................... 709 FIGURE 7-69: ROOT COMPLEX LINK CONTROL REGISTER .......................................................... 713 FIGURE 7-70: ROOT COMPLEX LINK STAT

PCI Express® Base Specification Revision 4.0 Version 0.3

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Transcript of PCI Express® Base Specification Revision 4.0 Version 0.3