PCB Designer’s SI Guide

PCB Designer’s SI Guide

A basic guide for SI and crosstalk for a PCB designer

Preface What the heck is SI? Why and what should I Simulate? What is the strategy for SI Analysis? Is crosstalk happens when you talk in the mobile? What do you mean by transmission line? Topology??? Are you kidding? Delay?? How about a schedule change? This is a collection of articles, which are found in web and other sources trying to answer your questions. Hope it will be helpful

PCB Designer’s SI Guide Venkata

Table of Content

Basics of SI___________________________________________________________________5 1.1 When Speed is important? _____________________________________________5

1.1.1 Acceptable Voltage and timing values ________________________________5 1.2 Signal Integrity ______________________________________________________5

1.2.1 Waveform Voltage Accuracy_______________________________________5 1.2.2 Timing_________________________________________________________5

1.3 Speed of currently used logic families ____________________________________5 1.3.1 Transition Electrical Length (TEL) __________________________________6 1.3.2 Critical length___________________________________________________6 1.3.3 What is Transmission Line? ________________________________________6 1.3.4 What is moving in a Transmission line?_______________________________6 1.3.5 Power Plane Definition____________________________________________6 1.3.6 The concept of Ground ____________________________________________7

1.4 STRIPLINE circuit with Electromagnetic field _____________________________7 1.5 RLC Transmission Line Model _________________________________________8

1.5.1 What is Impedance? ______________________________________________8 1.5.2 A Practical impedance equation for microstrip _________________________8 1.5.3 What is relative dielectric constant Er? _______________________________9

2 Interconnections for High Speed Digital Circuits _______________________________10 2.1.1 Summary______________________________________________________10

2.2 Examples of dynamic interfacing problems _______________________________10 2.3 IC Technology and Signal Integrity_____________________________________12 2.4 Speed and distance __________________________________________________14 2.5 Digital signals: Static interfacing _______________________________________15 2.6 Digital signals: Dynamic interfacing ____________________________________16 2.7 Review questions ___________________________________________________18

3 Interconnection Models____________________________________________________20 3.1 Summary__________________________________________________________20 3.2 Reference model for interconnection analysis _____________________________20 3.3 Receiver model_____________________________________________________21 3.4 RC interconnection model ____________________________________________23 3.5 Parameters of the interconnection ______________________________________25 3.6 Refined models _____________________________________________________26 3.7 Review question ____________________________________________________28

4 Transmission Line Models _________________________________________________31 4.1 Summary__________________________________________________________31 4.2 Transmission line models _____________________________________________31 4.3 Loss- less transmission lines ___________________________________________32 4.4 Critical Length _____________________________________________________34 4.5 Reference transmission line model______________________________________35 4.6 Line driving _______________________________________________________36 4.7 Propagation and reflected waves _______________________________________37 4.8 A sample system____________________________________________________39 4.9 Review questions ___________________________________________________42


5 Analysis techniques _______________________________________________________45 5.1 Summary__________________________________________________________45 5.2 Transmission time and skew___________________________________________45 5.3 Effects of termination resistance _______________________________________46 5.4 Lattice diagram _____________________________________________________48 5.5 Examples of Real Lines ______________________________________________49 5.6 Simulation code ____________________________________________________51 5.7 Examples of results__________________________________________________54 5.8 Review questions ___________________________________________________55

6 Design guide for interconnection ____________________________________________57 6.1 Summary__________________________________________________________57 6.2 Incident wave switching ______________________________________________57 6.3 Effects of capacitive loading __________________________________________58 6.4 Termination circuits _________________________________________________59

6.4.1 Passive termination______________________________________________60 6.4.2 Low power termination___________________________________________61 6.4.3 Active low power termination circuit. _______________________________61

6.5 Driving point-to-point lines ___________________________________________62 6.6 Driving bused lines __________________________________________________64 6.7 Design guidelines ___________________________________________________67 6.8 Review questions ___________________________________________________67

7 Signal Integrity in Digital Circuits ___________________________________________70 7.1 Crosstalk __________________________________________________________70

7.1.1 Summary______________________________________________________70 7.2 Examples of signal integrity problems ___________________________________70 7.3 Simplified Model for Crosstalk Analysis _________________________________71 7.4 Forward and backward crosstalk _______________________________________74 7.5 Examples__________________________________________________________76 7.6 Near-end and Far-end crosstalk ________________________________________80 7.7 Review questions ___________________________________________________81

8 Design Guide to Handle Crosstalk ___________________________________________85 8.1 Summary__________________________________________________________85 8.2 Effects of Crosstalk__________________________________________________85 8.3 Passive countermeasures _____________________________________________86 8.4 Active Control of Crosstalk ___________________________________________92 8.5 Review questions ___________________________________________________94

9 Ground Bounce and Switching Noise_________________________________________97 9.1 Summary__________________________________________________________97 9.2 The totem pole Current Spike__________________________________________97 9.3 Current flow in the output capacitance__________________________________100 9.4 Total Ground Bounce _______________________________________________100 9.5 Review questions __________________________________________________105

10 Design Guide for Ground & Power Distribution _____________________________107 10.1 Summary_________________________________________________________107


10.2 Decoupling Capacitors ______________________________________________107 10.3 Placement of bypass Capacitors _______________________________________113 10.4 Ground and power distribution________________________________________114 10.5 Clock distribution __________________________________________________115 10.6 Review Questions __________________________________________________118

11 Laboratory Experience _________________________________________________120 11.1 Summary_________________________________________________________120 11.2 Aim of the experience_______________________________________________120 11.3 Generator Parameters _______________________________________________122 11.4 Cable Parameters __________________________________________________123 11.5 Mismatch at driver and at termination __________________________________124 11.6 Capacitive Load ___________________________________________________125 11.7 7. Time-domain reflectometer ________________________________________127 11.8 Driving the line with logic devices_____________________________________128

12 SI Analysis Strategy____________________________________________________133 12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133

12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES______________________133 12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134

12.3 SOLUTION SPACE ANALYSIS _____________________________________135 12.3.1 STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135 12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135 12.3.3 STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136 12.3.4 STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136 12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136 12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137 12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137 12.3.8 STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137 12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138 12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139

12.4 CONCLUSION____________________________________________________139

13 Glossary _____________________________________________________________141


Basics of SI 1.1 When Speed is important? Speed is important when; the edge rate (rise or fall time) of a clock is fast enough that the signal can change from one logic state to the other in the same or less time than it takes the signal to travel the length of the wire or net. 1.1.1 Acceptable Voltage and timing values Any voltage level within the values of the Vin Maximum to Vin Minimum is a valid logic signal. Excursions outside these limits will cause logic malfunction. SI engineering involves; developing design rules that insures all logic signals fall within the envelope for any allowed combination of components, temperature and power supply voltage. 1.2 Signal Integrity SI has 2 components that are interlinked; voltage accuracy of the waveform and timing of arrival of switching edges at the input. 1.2.1 Waveform Voltage Accuracy It is affected by impedance matches, ground bounce and coupling etc. 1.2.2 Timing Is affected by propagation delay variations in ICs, travel time on wires, and variation in edge rates of ICs. 1.3 Speed of currently used logic families Logic type Typical edge speed

(nSEC) Transition electrical length in FR-4 (inches)

Critical length in inches

STANDARD TTL 5.0 29.0 14.5 ASTTL 1.9 10.9 5.45 FTTL 1.2 6.9 3.45 10K ECL 2.5 14.4 7.2 BTL 1.0 5.8 3.9 CMOS/DS 1.5 9.0 4.5 LVDS 0.3 1.73 0.86 100K ECL 0.5 2.88 1.44 GA AS 106 0.3 1.73 0.86 GTL+(PENTPRO) 0.3 1.73 0.86 Overshoot and undershoot problems will start to occur at less than 1/3 of the Transition Electrical Length (TEL) and may require series termination of transmission lines, as well as impedance control.


1.3.1 Transition Electrical Length (TEL) The length of transmission line represented by one rise or fall time. To obtain TEL, multiply rise or fall time by velocity of travel of electromagnetic energy in the transmission line. E.G. Rise time 1.5 nSEC, velocity 5.8 inches per nano second. So TEL = 1.5 X 5.8 = 8.7” Velocity of travel of electromagnetic energy in transmission line = 5.8 inches/nSEC 1.3.2 Critical length The length that two lines must run in parallel in order for backward cross talk to reach a maximum or to saturate. This is approximately ½ of TEL. 1.3.3 What is Transmission Line?

• A transmission line is any pair of conductors that are used to move electromagnetic energy from one place to another.

• In PCBs, this is typically a trace and one or more power planes • Power lines are transmission lines • Waveguides is a transmission lines • TV Twin lead is a transmission line • Co-axial cable is a transmission line • Twisted pairs are transmission line.

All of the transmission line has characteristic impedance. 1.3.4 What is moving in a Transmission line?

• Rapidly changing electromagnetic field at or near the speed of light • Typical EM Waves • Radar waves, Light Waves, AM/FM Radio Wave, Pager Signals, EMI/RFI Energy, TV

Waves EM waves do not depend on electrons for transmission, all move through vacuum at the speed of light. All are EM energy moving from place to place. 1.3.5 Power Plane Definition

• At transmission line speeds, all power planes in a PCB are ground planes, irrespective of their DC names

• Any power plane can serve as the “ground” plane for any “fast” signal • It is not necessary to route critical signals such as clocks over the plane called “DC’ ground • Why is this so? By design, we short power planes together at ac frequencies. This shorting is

done using bypass capacitors of the PCB itself. If the power planes are not shorted at high frequencies (meaning low power system impedance) there will be large amounts of noise on the power supply rails (a common source of EMI in PCBs with small inter-plane capacitance)


1.3.6 The concept of Ground The word Ground is used to describe a very wide variety of things in electronics. Examples are chassis of unit, the plane half of transmission line, the reference terminal of an analog system By defining ground us: the point in an electronic system from which voltage measurements are made. It is a reference point only. It has no meaning or function Some grounds used in electronic circuits

• Chassis ground • • Logic Ground – this is the point where all measurements are made, no need to connect to

chassis

• Analog ground – this is commonly used to represent a point in a system that analog circuits use to measure or compare analog signals. It can and must be connected to LOGIC GROUND at some point

1.4 STRIPLINE circuit with Electromagnetic field

Magnetic lines of force (solid lines) encircle the signal conductor; electric lines of force (dotted lines) connect the signal conductor to the reference plane


1.5 RLC Transmission Line Model

This model assumes ground is plane of negligible inductance and resistance. The following equations permit one to calculate the reactance of capacitors and inductors as a function of frequency. The equation for calculating the amount of capacitive reactance in an ac circuit is given by:

XC = 1 / (2πfC)

where:

XC = capacitive reactance in ohms f = frequency in hertz C = capacitance in farads

The equation for calculating the amount of inductive reactance in an ac circuit is given by:

XL = 2πfL

Where:

XL = inductive reactance ohms (Ω) f = frequency in hertz (Hz) L = inductance in henries (H)

1.5.1 What is Impedance?

• Impedance is the resistance to the flow of energy in a transmission line • At low frequencies, it is primarily DC resistance of the bulk copper and is relatively small in

PCB traces • At high frequencies it is primarily reactive and substantially higher than the DC or low

frequency value • Reactance is both capacitive and inductive

1.5.2 A Practical impedance equation for microstrip


79 5.98ln

0.81.41or

HZ

W Te = ++

Zo = Trace impedance in OHMS Er = Relative Dielectric constant H = Height of trace above plane T = Trace Thickness Valid for 5<w<15 mils 1.5.3 What is relative dielectric constant Er?

• Relative dielectric constant, Er, is a measure of the affect an insulator has on capacitance of a pair of conductors as compared to same conductor pair in a vacuum.

• The dielectric constant in vacuum is 1.

An equation for calculating Er using velocity measure with a TDR (time domain reflection)

r

ce

v= Where c = speed of light; v = measure propagation velocity


2 Interconnections for High Speed Digital Circuits

2.1.1 Summary

The first lesson answers the following questions:

• Which kinds of systems are addressed? • What does "dynamic interfacing" mean? • Which kinds of signals are analyzed here? • Which are the relevant static parameters of digital logic circuits?

2.2 Examples of dynamic interfacing problems

1) Spikes and temporary faults appear at the output of a combinatorial circuit. The reason is that the change of logic state is sensed with different delays by a logic circuit connected to the same signal. This may cause transient combinations of logic states, which were not taken into account in the design process.

2) Figure 1.1 shows two microprocessors driven by the same clock signal. That means they should run synchronously, without problems related with marginal timing, such as metastability. In the real circuit, for some combinations of temperature and supply voltage, the system exhibits random errors for microprocessor 2. Swapping the devices has no effect; therefore the problem is related with the socket, not with the device.

Figure 1.1 Clock distributions to a couple of microprocessors.

The random errors are caused by synchronization problems (metastability) in the information exchange between the two microprocessors. The solution is a redesign of the clock distribution circuit as in Figure 1.2, taking into account transmission line effects. This can guarantee the timing margins for the synchronous circuits of the two microprocessors.


Figure 1.2 Improved clock distribution.

3) A full-rack length (49 cm) backplane is equipped with boards using 74F245 transceivers towards the bus, as in Figure 1.3. Backplane signals on the scope exhibit high signal distortion (Figure 1.4). Moreover, the bus interfaces have rather high power consumption.

Figure 1.3 Loaded backplane bus.


Figure 1.4 Waveforms on a high-speed digital interconnection.

Understanding the problem enables the designer to select the proper logic family for the drivers, thus achieving better waveforms, and reducing the power consumption. 2.3 IC Technology and Signal Integrity Microelectronic technology allows us to put several million devices (transistors) on a single die, but similar advances did not occur in interconnection capability. Namely, the number of devices in a single IC scales with the square of the (chip size)/(device size) ratio (S/l), while standard interconnection, being placed on the die boundary, scales linearly towards the same parameter. The two parameters are plotted in Figure 1.5. Therefore, in the design of complex high-performance systems, we have to face an interconnection bottleneck.


Figure 1.5 Different rate of improvement for IC complexity and interconnection capability.

This communication bottleneck is addressed by increasing the speed (bit rate) on external interconnections, and by increasing the number of pins. But higher speed means higher dv/dt on I/O pins. This requires high currents to charge/discharge parasitic capacitors, and the effect is multiplied by the increase in the number of I/O pins. Higher currents mean more noise towards other circuits and systems, and careful design of interfaces is required to sustain the nominal speed of digital circuits in real systems. Surface mount technology (Figure 1.6) and new packaging techniques which reduce the size of devices and systems, and reduce parasitics by moving interconnection points from the boundary to any die position (eg BGA and flip-chip) help to deal with these problems. Also Low Voltage (LV) logic families, which reduce the DV between logic states help to limit EMI (and power consumption), at the expense of reducing noise margin and therefore increasing their susceptibility (sensitivity to external interference).

Figure 1.6 Surface mount packages (divisions on the top are 1 mm. each)


2.4 Speed and distance To evaluate the actual speed of information transfer, we must consider that in actual systems each conductor (wire, track) has resistance, capacitance, and inductance. Therefore signal transmission delays (and hence the speed of operation) depend not only on logic gates, but also on interconnections. The information is carried by electric signals, which are related to electromagnetic waves, moving at high but limited speed. As the time scale of system operation (defined by the clock period) becomes of the same order of magnitude as the time required by electrical signals to move across a system, conductors cannot be considered equipotential, and we must model wires and tracks as transmission lines. Table A gives the approximate distance travelled by electrical signals on a PCB during one clock period (Electrical length of the clock), for some common clock rates.

Clock Rate

Clock Period

Electrical Length Device

1 MHz 1 ms 200 m Old microprocessors

10 MHz 100 ns 20 m Current low performance microcontrollers

100 MHz 10 ns 2 m Current medium performance

microprocessors 500 MHz 2 ns 0.4 m high performance

microprocessors and DSPs

Table A: Approximate distance traveled by electrical signals on a PCB during one clock period

What must be actually taken into account is not the clock period, but the edge slope. The change from one logic state to the other requires a finite time (roughly corresponding to the rise time or the fall time of the waveform). In first approximation, the spectrum of a digital signal covers from DC to a frequency F = 1/2tr. Current high-speed circuits, with rise/fall time below 1 ns, have significant components at frequencies above 500 MHz. The frequency content depends on edge steepness, not on repetition rate. If the signal has to travel over some distance, devices tied to the same node (that is connected by a wire, or a PCB track) may sense different logic states. This effect is completely hidden in the conventional "logic diagrams", which assume that all logic circuits tied to a node sense the same state at the same time. The rise/fall time of current logic devices is about 1 ns; that means only wires shorter that 20 cm can be considered a single "node". This data shows how for most modern high-speed logic families the interconnection delay and the transmission line effects interact with pure logic behavior of gates, and can cause false signaling. These effects put upper bounds on the speed of logic systems; even if the pure logic could run at infinite clock rate, the wiring introduces limits, as discussed in the following lessons.


2.5 Digital signals: Static interfacing The digital signals actually consist of analogue voltages (and sometimes currents), which represent the logic state of logic variables (usually binary). Voltage and currents are defined as in Figure 1.7

Figure 1.7 Two interconnected digital devices.

The mapping between logic states and analogue voltages is defined by the static electrical parameters.

Logic State

Output Electrical Parameters

Input Electrical Parameters

LOW VOL , IOL VIL , IIL HIGH VOH , IOH VIH , IIH

Table B: Logic States and Electrical parameters

The static compatibility conditions (visualized in Figure 1.8)

VIL > VOL and VIH < VOH

Guarantee that electrical levels are correctly recognized as logic states.

Figure 1.8 Electrical compatibility chart.


Since each input sinks/sources a current, and the current handling capability of outputs is limited, the static interfacing conditions include another relation:

IOX > IIX

(the total current at driver output must be lower that the IOH or IOL specified by the manufacturer). This condition puts an upper limit on the number of inputs that can be connected to the same output. Even if most current digital circuits use CMOS devices, with input currents practically 0 (and therefore no limit in a purely static situation), CMOS inputs are always dynamic loads (capacitance), and increasing their number leads to speed reduction, as discussed in the following lessons. 2.6 Digital signals: Dynamic interfacing The behavior of a digital signal in the time domain is defined by a set of timing parameters. Rise time tR and fall time tF: time required by the signal to slew from 10% to 90% of total swing.

Figure 1.9 Definition of rise and fall times.

Propagation delays, tPLH and tPHL: respectively for LOW to HIGH and HIGH to LOW state changes. Figure 1.10a shows the input-output relationship for an inverter. The actual signals on a scope are in Figure 1.10b.

Figure 1.10a Definition of propagation delays.


Figure 1.10b Real digital signals.

Correct operation of flip-flops and registers require compliance with minimum set-up time (tSU) and hold time (tH). When these limits are fulfilled, the output state changes with a propagation delay tP after the clock active edge.

Figure 1.11 Timing parameters for a D-FF. Three-state buffers introduce enable and disable delays: tEN and tDIS.


Figure 1.12 Timing parameters for a 3-state buffer.

In summary, the main timing parameters are:

• tPLH, tPHL, tr, tf (for any logic circuit)

• tSU, tH, tP (for flip-flop)

• tEN, tDIS (for 3-state outputs)

Signal waveforms are modified by amplitude noise and time jitter, which changes the voltage levels and the timing margins, and may cause errors in the information transfer. In the following we shall analyze how digital systems can be designed in such a way as to minimize these effects, while running at the greatest possible speed. 2.7 Review questions 1) Dynamic interfacing addresses: · static compatibility of logic circuits, · power consumption of logic circuits, · *time-domain behavior of logic signals and circuits, · correctness of Boolean operations performed by logic gates. Static compatibility and power consumption are mainly related to DC parameters; Boolean operators determine the internal structure of logic circuits, not their interfaces. 2) Assuming a signal propagation speed of 0,6 c (c is the free-space propagation speed of the light), the "electrical length" of one clock period at 50 MHz is · 36 mm, · 1 m, · -* 3.6 m, · 6 m. 0.6 c = 0.6 x 300 000 km/s = 180 000 km/s For a 50 MHz clock the period is 20 ns; the distance traveled in 20 ns is 180x106 m/s x 20x10-9 s = 3.6 m. 3) The "propagation time" (tPHL) is defined as: · the time required by the voltage representing a logic state to change from VOL to VOH · *the delay between input and output state change for a High-to-Low transition · the time required by the voltage representing a logic state to change from VOL to 50% of VOH · the time required by the voltage representing a logic state to slew from 10% to 90% of VOH - VOL . Propagation times represent the delay between input and output of a logic device. The index (HL or LH) indicates the direction of the state change. 4) The "rise time" (tR ) is defined as: · the time required by the voltage representing a logic state to change from VOL to VOH, · the time required by the voltage representing a logic state to change from VOL to 50% of VOH, · *the time required by the voltage representing a logic state to slew from 10% to 90% of VOH - VOL, · the input-to-output delay of the receiver. This is a definition - just learn it ! 5) To explain the "set-up time" (tSU) you could say: · *the input D must be stable for at least tSU before the clock active edge; · the input D must be stable for at least tSU after the clock active edge; · the output Q will change with a delay of at least tSU after the active clock edge; · the minimum duration of the clock pulse is tSU. · the time required by the clock to slew from 10% to 90% of VOH - VOL is at least tSU . Flip-flops require time margins around the active clock edge to avoid


metastability. The input data must not change during these time margins. The pre-edge time is the setup; post-clock margin is the hold time. 6) The "disable" (tDIS) is defined as: · the time required by a three-state driver to exit from the high-impedance state, · *the time required by a three-state driver to enter the high-impedance state, · the input-output delay in a three-state driver to exit from the high-impedance state, · the time required by the voltage at the output of a three-state driver to slew from 10% to 90% of VOH - VOL . Due to internal parasitic and delays, a three-state driver requires some time to switch between active and non-active states. These are the enable and disable times. 7) With microelectronic technology evolution, the interconnection capability (that is the product between and ) · increases faster than local processing power, · *increases slower than local processing power, · increases at the same rate as local processing power, · decreases. Processing power depends on the number of active devices (transistors), which increases with the square of the (feature size)/(chip size) ratio. Interconnection capability (for standard packages) depends on how many active devices can be placed on the sides of the chip, which increases linearly with (feature size)/(chip size).


3 Interconnection Models 3.1 Summary

We shall start the analysis from simple linear models for driver/receivers and interconnections; this allows us to define the parameters which describe the behavior of systems made by several interconnected logic devices.

This lesson answers the following questions:

• What is a suitable reference model for interconnection analysis? • Which first-approximation models can we use for drivers and

receivers? • Which parameters can be defined for an interconnection? • What are "lumped parameters" and "distributed parameters"

models?

3.2 Reference model for interconnection analysis

The reference model for interconnection analysis consists of a driver, interconnection and receiver chain as in Figure 2.1.

Figure 2.1 Reference model for interconnection analysis.

Before entering the driver and after the output of the receiver we have logic states (0, 1). Between the driver output and the receiver input we describe the system in terms of electrical quantities such as voltage and current, or devices such as resistors, capacitors, etc. For the driver-interconnection-receiver systems we can define several models, with increasing accuracy.

• Linear models for driver and receiver, • RC, LC, LRC models for interconnections, • Transmission line models for interconnections,


• Nonlinear models for drivers and receivers.

The reference signal for the interconnection analysis is a logic state change, modeled as a voltage step generator inside the driver.

The electrical behavior of logic gates is specified by the static electrical parameters; these parameters define the static compatibility conditions previously defined.

3.3 Receiver model

The nominal transfer function of an inverting receiver is shown in Figure. 2.2. Examples of real transfer function are in Figure 2.3. The input voltage is interpreted as LOW or HIGH state depending on its level with respect to a threshold VTH , which can have any value in the range V IL- VIH .

Figure 2.2 "Ideal" transfer function of a logic inverter.


Figure 2.3 Examples of real transfer function of logic inverter.

Figure 2.4 Changes of the electrical parameters in different devices cause a shift of the transfer function.

The red and blue transfer characteristics in Figure 2.4 represent inverting buffers with different thresholds (both within specifications, that is in the range VIL- VIH). When the input voltage VIN is in the VIL- VIH range, it is not possible to state if it is above or below VTH for all logic circuits of that family. In this example when the input voltage VIN is within the VIL - VIH range, the "red" and "blue" inverters A and B (with different threshold voltages) map the same input signal to different output states. Static interfacing conditions are violated, and a Data Split may occur. Data split happens because of faulty or poor design, or because external noise modifies the voltage level on the interconnection.


Figure 2.5 The same input can be interpreted as different logic states.

On data split the digital circuits tied to the same node sense different logic states; the system is forced to a state not foreseen in the design phase (logic synthesis). In turn, it causes output errors or, for sequential circuits, unpredictable evolution or deadlocks. The indetermination of VTH is one of the reasons for the presence of skew (time indetermination) on interconnections. From this analysis we found that something wrong may happen when the input voltage VIN lies in the VIL - VIH interval. A first rule for digital interface design can be derived from this consideration: The input voltage VIN should lie in the VIL - VIH interval for the shortest possible time. This goal can be achieved by acting on two parameters:

• The amplitude of the V IL - VIH interval, which must be as small as possible. This amplitude depends on the tolerance of VTH, that is on the logic family, Some devices, specifically designed as interfaces, have tight tolerance on VTH, which corresponds to a narrow V IL - VIH interval.

• The slew rate of signals: faster transitions (short tR and tF) means that VIN stays in the V IL - VIH range for a shorter time. On the other hand, it means also higher current, more EMI towards other systems, and higher power consumption.

3.4 RC interconnection model

We shall use the reference model shown in Figure 2. 6. SA and SC are logic variables (0/1 or LOW/HIGH), while inside the driver/receiver and on the interconnection we analyze electrical variables (V, I, R,..). The driver is modeled by a Thevenin equivalent circuit: a logic state change at SA becomes a voltage step on VA, the receiver is modeled as a capacitor (this corresponds to C-MOS devices), and R-C circuits will be used for the interconnection.


Figure 2.6 Driver and receiver models for interconnection analysis.

A first approximation model for the interconnection is shown in Figure 2.7; it is modeled as a single node; the capacitor CI corresponds to the parasitic input capacitance of the wire and of the receiver (which is actually a good approximation for CMOS inputs). The circuit is a first order low-pass cell and the step response at the receiver input is an exponential.

Figure 2.7 Direct connection of nodes B and C.

At t = 0 VA applies the voltage step, and the capacitor CI can be considered a short-circuit, therefore the nodes B and C are at ground potential.

t = 0 VC = 0, VB = 0

When the transient is settled (t -> ), the capacitor becomes an open circuit, and the voltage at nodes B and C corresponds to VA.

t --> VC = VB = VA

The complete expression for VB and VC is (Figure 2.8):

VB = VC = VA (1 - e ) with = R C


Figure 2.8 Waveforms in the direct connection model.

3.5 Parameters of the interconnection

From this simple circuit we can define a first parameter to characterise an interconnection: the delay from state change at the driver and state change at the receiver, called transmission time tTX (Figure 2.9). This delay depends on the parameters of the driver (RO, output levels VUH/VUL), and of the receiver (C I, threshold voltage VTH), and corresponds to the value of t for VB = VTH.

tTX. = ln (VA / (VA - VTH))

Figure 2.9 Definition of the transmission time.

Since these parameters depend on parasitic, or may change among devices, the transmission time tTX will in turn change. The difference between maximum and minimum transmission time, which corresponds to the maximum variation of tTX is called Skew time tK:


tK = tTXmax - tTXmin A visualisation of the skew is in Figure 2.10.

Figure 2.10 Definition of the skew.

3.6 Refined models

To improve the accuracy we can add a series resistance RS to model interconnection wire resistance, as in Figure 2.11.

Figure 2.11 Series-resistance interconnection model.

The circuit is still a first order low-pass cell, but the threshold VTH is now crossed at different times in nodes B and C (Figure 2.12). This time difference is another type of skew: even assuming that all parameters are fixed and known, the transmission time depends on the position of the receiver (node B or C).


Figure 2.12 Waveforms for the series resistance interconnection model.

To further increase the accuracy from these basic RC models we can add new circuit elements that represent a more detailed interconnection structure (Figure 2.13):

a series inductance L, to take into account the wire/track inductance: RS -L-C model;

a parallel conductance GP towards ground, to model dielectric losses: GP-RS-L-C model;

Figure 2.13 More detailed models for the interconnection.

Resistance, capacitance and inductance are actually distributed along the whole length of the conductor; to improve the model accuracy the system can be divided into several short pieces (cells), with a R-L-C equivalent circuit for each of them. All these models are based on conventional circuit


elements, which represent R-L-C associated with a piece of interconnection: these are lumped-parameter models (Figure 2.14).

Figure 2.14 Multiple-cell interconnection model.

3.7 Review question

1) The "transmission time" tTX is defined as:

• the time required by the voltage representing a logic state to change from H to L (or vice-versa).

• *the delay from a state change at the driver and the sensing of that state change by the receiver.

• the time required by the electric signal to travel from the driver to the receiver.

• the input-to-output delay of the receiver.

The logic state changes become voltage steps at the output of logic circuits. They are sensed by other logic inputs when the voltage crosses the logic threshold. Due to output resistance of drivers and parasitic capacitance of interconnections and receivers, the vo ltage step becomes an exponential, and reaches the logic threshold after a delay called transmission time.

2) Using a model with series resistance, parallel conductance (R and C), the logic threshold is crossed

• *first at the driver output (near end), then at receiver input (far end). • first at the receiver input, then at the driver output. • at the same time at the driver and at the receiver.

The voltage at the near end (driver side) rises faster than the voltage at the far end (receiver).

3) The skew time is:

• the delay from the state change at driver input and voltage change at driver output.


• the delay from the voltage change at receiver input and state change at receiver output.

• the delay from a state change at the driver and the sensing of that state change by the receiver.

• the difference between transmission time in various system conditions and/or positions in the interconnection.

Receivers sense logic state changes after the transmission time, that is with a delay related with parasitic parameters, value of the threshold, position on the interconnection. The total variation of the transmission time is called skew.

4) Which of the following elements is not considered in the analysis of an interconnection (and does not affect the behaviour of the interconnection):

• the output circuit (driver). • the input circuit (receiver). • *the logic operations performed by interconnected devices. • the static electrical parameters.

The transmission time and the skew depend on the electrical parameters of the driver and of the receiver. The logic operation is performed inside the device, and does not affect the parameters of the interconnection.

5) If VIN stays in the V IL - VIH range:

• the driver can be damaged, • the receiver can be damaged, • a data split may occur, • the receiver output is blocked at VAL /2.

The receiver threshold is somewhere in the V IL - VIH range; if the input voltage is in the same range, various receivers can take different decisions (High or Low) for the same input voltage. This causes inconsistent system state and data split.

6) For a RC interconnection model the transmission time tTX is:

• *tTX = RC ln (VA / (VA - VTH)), • tTX = RC, • tTX = RC (VA / (VA - VTH)), • tTX = RC ln VTH.

The transmission time tTX can be computed by solving the equation:

VB = VTH = VA (1 - e ) with = R C


For t = tTX , VB = VTH ; substituting in the above equation:

VTH = VA (1 - e )

VTH - VA = - VA e

- ln((VTH - VA )/ VA ) = tTX / RC


4 Transmission Line Models 4.1 Summary

In the previous lessons we modeled interconnections with lumped elements, such as resistors and capacitors, and defined the basic parameters, which define interconnection performance: the transmission time and the skew. Here we shall move to distributed-parameter models, which are a better representation of interconnections for high-speed logical devices.


• What are "lumped parameters" and "distributed parameters" models?

• What is a loss-less transmission line? • Why and when should we use transmission line modes? • What is a reflected wave? • How can we compute reflection coefficients?

4.2 Transmission line models

In the previous lesson we defined cell-based lumped-parameter models (Figure 3.1).

Figure 3.1 Multiple-cell models.

Each cell models a piece of wire (or PCB track); as the length of this piece diminishes and the number of cells increases, the model approximation improves. For an infinite number of very small cells, the sequence turns into a distributed parameter model or transmission line (Figure 3.2).


Figure 3.2 Transmission line as a sequence of small elementary cells.

The transmission line is a distributed parameter model for the interconnection. The parameters of the transmission line are the R, L, C, G values for unit length (here labeled R', G', L', C', which in turn depends on the physical parameters (dimensions, materials,).

4.3 Loss-less transmission lines

When the series resistance RS and the parallel conductance GP are 0, the cells include only reactive elements (Figure 3.3), and no power is dissipated on the line. In these conditions Z0 is real and we talk of loss-less transmission line. Loss-less transmission lines are a very good approximation for PCB tracks, coaxial cable and copper wires. In the following we shall always use loss-less lines.

Figure 3.3 Loss-free cell, which can be translated into a loss-less transmission line.

For an analysis of transmission lines as interconnection, we shall define two parameters:

• the propagation speed U, • the characteristic impedance Z0.

They depend on inductance and capacitance per unit length (1 meter) L' and C'.


The characteristic impedance Z0 corresponds to the v/i ratio at any point of the line. When the physical parameters (size, materials) are constant, the same applies to L', C', and therefore to Z0.

For a transmission line of length l we can define a propagation time tP (time required by electromagnetic waves to travel over the length l)

The characteristic impedance Z0 and the propagation speed U for some commonly used interconnection media are within the following ranges:

U: 0.6 - 0.8 c (corresponds to 18-24 cm/ns)

Z0: Coaxial cables (Figure 3.4) 50 - 100

Flat cables (signal/ground pairs, Figure 3.5) 100-300

PCB tracks (with ground plane, Figure 3.6) 20 - 200

Figure 3.4 Example of transmission lines: coaxial cables


Figure 3.5 Example of transmission lines: flat cables.

Figure 3.6 Example of transmission lines: tracks and ground plane of a Printed Circuit Board (PCB)

Wider tracks have higher capacitance and lower inductance, that is lower characteristic impedance Z0 and lower propagation speed U. The inverse occurs with narrow tracks or when the gap between track and ground is decreased (that is when the board thickness is reduced).

As the unit inductance L' increases (more narrow track) the characteristic impedance Z0 increases and the propagation speed U decreases.

When many devices are connected to a track, the unit capacitance C' is increased by the device parasitic (input and output capacitance). Also in this case the characteristic impedance Z0 and the propagation speed U decrease.

4.4 Critical Length

If the propagation time over an interconnection is far less than rise and fall time of signals, the conductor can be considered equipotential; in this case


lumped-parameters RC models defined in lesson 2 can be used. When the propagation time is of the same order of magnitude as the transition time of logic circuits the interconnections must be modeled as transmission line.

For each logic family a critical length (related to transition times) can be defined: connections longer than this critical length must be modeled as transmission lines.

The table shows the values of critical connection length for various logic families.

Maximum connection length for lumped-parameter analysis for the various Logic Families

TTL 60 cm ALS 25 cm AS 6,5 cm HC 45 cm ABT 15 cm

4.5 Reference transmission line model

The reference model for interconnection analysis consists of a driver-line-termination system, as in Figure 3.7. The line has no loss. The driver sends a step signal on the left end of the line (near end); at the other end (far end) the line is terminated on a resistance RT. Other logic circuits can be connected at any position along the line.

Figure 3.7 Reference model for transmission line analysis.

The open-circuit voltage of the line driver is a voltage step with amplitude VA. RO is the internal output resistance of the driver.

The line is defined by two parameters:

• the characteristic impedance Z0


• the propagation time , where l is the physical length of the line and U is the propagation speed.

VB is the voltage at node B (driver output, left side of the transmission line, or near end) VC is the voltage at node C, corresponding to the right side of the line or far end. The termination resistance is connected to this node. The line termination can be a specific component or the input of a receiver.

4.6 Line driving

Let us first consider a driver connected to a line of infinite length (Figure 3.8).

Figure 3.8 Driving an infinite line.

When the logic state at driver input changes (eg 0 to 1), a voltage step (VOL to VOH, simplified as 0 to VA) appears at the driver output. The driver is loaded by the transmission line - that is by a dynamic impedance Z0. The actual step at node B is given by the partition of VA across RO and Z0 (Figure 3.9)

Figure 3.9 Equivalent circuit for line driving.


This is called first step or incident wave, and corresponds to the amplitude of the incident wave traveling on the line from the driver (left side) towards the termination (right end).

As long as there is no discontinuity on the transmission line, the wave continues to travel on the line towards the right side. If we connect at the far end a resistance RT = Z0 the incident wave is absorbed by the termination, and the whole line goes to a steady state with VC = VB. In these conditions the line is matched.

On any discontinuity of the characteristic impedance Z0 (change in track width, or insulator thickness or material, lumped loads,...), part of the energy traveling along the line goes through the discontinuity and the remaining part is reflected backward, generating a reflected wave (Figure 3.10).

Figure 3.10 Discontinuities in a transmission line.

The two ends of the line usually represent the most significant discontinuity; a typical situation for instance could be:

• Open line at the far end, • Low resistance termination at driver.

4.7 Propagation and reflected waves

On the line, voltage and current propagate at speed U in both directions. Signals going towards the right end (incident or progressive wave) are indicated by v1, i1 ; signals going towards the left side (reflected or regressive wave) are v2, i2. All these signals depend on time and position, that is :

v = v(t,x); i = i(t,x);


and the v/i ratio for each wave corresponds to the characteristic impedance Z0;

v1/i1 = Z0 ; v2/i2 = -Z0

The total voltage and current at time t in the position x are the sum of incident and reflected terms:

v(t,x) = v1(t - x/U) + v2(t + x/U), i(t,x) = i1(t - x/U) - i2(t + x/U)

At the far end (termination RT) Kirchoff and Ohm laws apply:

iT = i1 + i2; vT = v1 + v2; vT/iT = RT

while along the line we have: i1 = v1 / Z0; i2 = - v2/ Z0

and therefore we get : iT = i1 + i2 = (v1 - v2)/ Z0 vT = v1 + v2 = iT RT = (v1 - v2) RT/ Z0 (v1 + v2) Z0 = (v1 - v2) RT v2 = v1(RT - Z0)/(RT + Z0)

If we define a reflection coefficient as:

the backward (reflected) wave v2 can be written as:

These relations apply also when the characteristic impedance changes (variation in track size or distance from ground, lumped loads, etc). To comply with line equations on both sides part of the incident wave is reflected towards the near end, and the remaining part continues on the


line with the new characteristic impedance. Therefore, a reflected wave builds up at any discontinuity, including the near end (at the driver), if RO is not equal to Z0

4.8 A sample system

We can now analyze a driver-interconnection-receiver system. The interconnection is a PCB track, which can be considered loss-less transmission line. The only discontinuities are at both ends:

• · A termination resistance RT at the far end (at the receiver input) • · The driver with equivalent output resistance RO at the near end

At t = 0 the output of the driver sees the line as impedance Z0: the voltage at node B is the partition of VA among R0 and Z0 (Figure 3.11). This is the first step (incident wave) with amplitude:

Figure 3.11 Driver-line equivalent circuit.

This signal corresponds to the first incident wave V', which moves forward on the line at speed U.

At t = tp the step reaches the end of the line (node C). The signal at the far end C comes from a generator VL with equivalent impedance Z0, the transmission line. Therefore for the incident wave v/i = Z0.

On the termination resistance RT , v/i = RT. If RT is different from Z0, a reflected wave V" arises in C and propagates backwards from the termination towards the driver.


Figure 3.12Line-termination equivalent circuit.

The amplitude of this reflected wave is

At t = 2 tp the reflected wave V" comes back to the driver output (node B). Since the driver output resistance RO is different from Z0, a new reflected wave V"' is generated.

diagram with diagram, and travels left-to-right (from the near end to the far end).

The complete sequence is in Figure 3.13.

Figure 3.13Sequence of reflections at both ends of the line.

The voltage in any position is the sum of a ll incident and reflected waves. The waveforms in B and C are a sequence of steps with amplitude related with RO, Z0, RT. The steps occur at t = 2 K tP at the near end (B), and at (2k + 1) tP at the far end (C).


Two examples of VB and VC for different combinations of RT and RO are in Figure 3.14 (screen capture from a simulator). A sample scope display of the waveforms at nodes B and C (with open circuit for RT and RO >> Z0 ) is in Figure 3.15.

Figure 3.14Two examples of waveforms at near end (VB) and far end (VC).

Figure 3.15 Near end (top trace) and far end waveforms.


4.9 Review questions

1) A distributed model for interconnection contains

• a single lumped-element cell • at least 5 lumped-element cells • at least 100 lumped-element cells • *an infinite number of cells

Distributed models are built by increasing the number of cells in lumped parameter models. As the number of cells increases - for a given line length - the value of parameters (R, L, C) decreases.

2) The speed of electromagnetic waves in coaxial cables and PCB tracks is about (c = free-space speed of light)

• 2 c • *0.7 c • c • 1 c

This can be seen as a result of measurements or calculations from physical parameters.

3) For thinner tracks, the characteristic impedance

• *increases • decreases • does not change

The track and the ground plane make a capacitor; when track width decreases, the size of the capacitor decreases. The characteristic

impedance increases hwen C decreases.

4) For wider tracks, the characteristic impedance

• increases • *decreases • does not change


The track and the ground plane make a capacitor; when track width increases, the size of the capacitor increases. The characteristic

impedance decreases when C increases.

5) For thinner insulator towards ground, the characteristic impedance

• increases • *decreases • does not change

The track and the ground plane make a capacitor; when the separation between plates decreases, the value of the capacitor increases. The

characteristic impedance decreases when C increases.

6) For ticker insulator towards ground, the characteristic impedance

• *increases • decreases • does not change

The track and the ground plane make a capacitor; when the separation between plates increases, the value of the capacitor decreases. The

characteristic impedance increases when C decreases.

7) A 10 cm interconnection in a logic system using HC circuits

• *can be considered a single node • must be handled as transmission line

The rise/fall time in the HC logic family is a few ns. The distance travelled by the electric wave in this time is 40-60 cm, higher than the interconnection length.

8) The amplitude of the first step, for VA = 5 V, RO = Z0 is:

• 1 V • 2 V, • *2.5 V • 5 V


9) The reflection coefficient G is given by:

• = (RT - Z0)/(Z0 - RT), • = (RT - Z0)/(RT + Z0), • = (Z0 - RT)/(RT + Z0), • = (RT + Z0)/(RT - Z0).

This is the result of network analysis, computing the reflected wave as excess voltage required to comply with Ohm's equation on the line and on the termination.

10) For RT = 100 W and Z0 = 50 W the value of the reflection coefficient is:

• = 1 • = -1 • * = 0.6 • = -0.6

Can be computed from = (RT - Z0)/(RT + Z0),


5 Analysis techniques 5.1 Summary

This lesson describes some techniques that can be used to analyze simple transmission-line interconnection systems. Results for some exemplary cases are presented. This lesson answers to the following questions:

• How can we analyze transmission lines with linear drivers and receivers?

• How can we analyze transmission lines with non-linear drivers and receivers?

• Which technique can be used to evaluate transmission time and skew with transmission line models?

• Can we use standard mathematical tools and electrical simulators to analyze transmission line systems?

5.2 Transmission time and skew

Transmission time and skew keep the definition given in lesson 2. Instead of following an exponential, now the voltage on the line changes as a sequence of steps, corresponding to the sequence of reflected waves (Figure 4.1).

Fig 4.1 Waveforms at the near end (top trace) and far end of a

transmission line driven by digital signals.


The transmission time tTX and the skew tK are still defined as for RC models, but now their value is expressed in multiples of the propagation time tP , that is as the number of steps required to reach and cross the threshold. Figure 4.2 shows the near-end and far-end waveforms for an interconnection with low-current driver and open-circuit termination (this is the most common case for digital circuits).

Fig 4.2 Comparison between lumped-element and distributed element models.

In the following sections we shall analyse some simple specific cases for the termination resistance, evaluating the transmission time and the skew.

5.3 Effects of termination resistance

For the first reflected wave, we can look at signals for three specific cases.

1. RT = Z0 = 0;

The line is matched: the v/i ratio is equal to Z0 both on the line and at termination; G = 0 and there is no reflected wave. In figure 4.3 the top trace represents the voltage at the near end (driver), and the bottom trace is voltage at termination. Since there is no reflection, we observe a single step, respectively at t = 0 (, node B, driver, top trace) and t = tP (node C, termination, bottom trace).


If VTH > VA / 2, in this configuration tTXmax = tP , tK = tP.

Fig 4.3 Waveforms at the near end (top trace) and far end of a transmission line with matched termination.

2. RT = oo = 1;

The termination is an open circuit: since = 1, the reflected wave has the same amplitude and same polarity as the incident wave (figure 4.4). At the near end (node B, top trace) we can see a first step (t = 0), and a second step (same amplitude) at t = 2 tP. On the termination (node C, bottom trace) the incident and reflected wave add, and we see a single step with double amplitude.

If VTH > VA / 2, in this configuration tTXmax = 2tP , tK = tP.

Fig 4.4 Waveforms at the near end (top trace) and far end of an open transmission line.


3. RT = 0 = -1;

The termination is a short circuit: = -1, the reflected wave has the same amplitude but opposite polarity of

the incident wave. (The total voltage at the termination C (a short circuit) is 0, therefore the sum of incident and reflected waves must be 0). At t = 2 tP the reflected wave comes back to the driver and cancels the voltage VB. The resulting waveform in node B is a 2 tP pulse (red line in figure 4.5).

Fig 4.5 Waveforms on a transmission line with a short-circuit at the far end.

5.4 Lattice diagram

To analyze the behavior of the driver-line-receiver system we can use the lattice diagram technique (figure 4.6).

The lattice diagram represents on the horizontal axis (x) the segment of line under analysis, and on the vertical axis the time (t), increasing towards the bottom. The signal on the line is represented by a point, which moves in the (x,t) plane on straight lines with a slope depending on the propagation speed U = x/t. When the signal hits a discontinuity (such as line ends in this example), a reflected wave with an amplitude depending on the corresponding is sent backwards.


Fig 4.6 Structure of a lattice diagram.

The diagram represents the signal trajectory in the (x,t) plane, that is the (x,t) pairs that satisfy the wave equation. The amplitude of each reflected wave is given by the incident wave multiplied by the reflection coefficient. The total signal amplitude can be obtained by summing the amplitude of the reflected waves sequentially generated at each end. The v(P,t) waveforms corresponds to a vertical section of the diagram in the corresponding position (point P in this example). The various contributions sum as they arrive at that point (that is when the lattice crosses the vertical line). 5.5 Examples of Real Lines The following drawings represent lattice diagrams for some sample cases. The upper-right window shows the waveforms at the near end and at the far end.

Fig 4.7: RT = T = 1;RG = Z 0 G = 0;


Fig 4.8: RT = T = 1; RG > Z0 G = 0.5;

Both reflection coefficients are positive: the waveforms are a sequence of steps with the same polarity.

Fig 4.9: RT = 0 T = -1; RG > Z0 G = 0.85;


Fig 4.10: RT =0 T = -1; RG = Z0 G = 0;

5.6 Simulation code The simulator provided in the following analyses the behavior of loss-less transmission lines using the wave equations and computing actual waveforms using the lattice diagram technique.

The program generates three drawings, showing respectively the signals at near end, far end, and an intermediate point, and a 3D view of voltage on the line versus time and position.

The simulator is written in Matlab language (by MathWorks company: www.mathworks.com). To run this code you need the Matlab 5 environment. You may copy the source code, and modify the line or termination parameters.

% This code generates time/position views of step waveforms on a transmission line

% usage of variables: % t time % x position % y amplitude

% numeric parameters can be modified directly in the source code % to simulate different operating conditions;

clear


Zo = 100; % line imp Rs = 220; % source imp Rt = 1150; % term imp

tp = 4; % propagation delay over L L = 8; % line length

tmax = 45; % max observed time

F = 0; T = 0; t =0; G = 1; % step amplitude

As = Zo/(Rs+Zo); % Partition at driver output Gt = (Rt-Zo)/(Rt+Zo); % Gamma at termination Gs = (Rs-Zo)/(Rs+Zo); % Gamma at source

% first propagation

for t = 1:tp+1 for x = 1:L U(t,x) = F + G*As*((x/L)<(t/tp)); end end G = U(t,x) - F; F = U(t,x); bounce = 1;

% reflections

while t < tmax

for t = (bounce*tp):((bounce+1)*tp+1) for x = L:-1:1

U(t,x) = F + G*Gt*(((L-x)/L)<((t-bounce*tp)/tp)); end end G = U(t,x) - F; F = U(t,x); bounce = bounce+1;

for t = (bounce*tp):((bounce+1)*tp+1) for x = 1:L U(t,x) = F + G*Gs*((x/L)<((t-bounce*tp)/tp)); end end


G = U(t,x) - F; F = U(t,x); bounce = bounce+1;

end T = t;

% drawing results

x=1:L; t=1:T; [X,Y]=meshgrid(x,t);

mesh (X,Y,U) title (['View from termination: Gt = ',num2str(Gt), ' Gs =',num2str(Gs)]) xlabel ('distance'), ylabel ('time'), zlabel ('amplitude') view ([40, 30]) % view from termination %print -dwinc

figure mesh (X,Y,U) title (['View from source: Gt = ',num2str(Gt), ' Gs =',num2str(Gs)]) xlabel ('distance'), ylabel ('time'), zlabel ('amplitude') view ([-50, 30]) % view from source %print -dwinc

figure plot (t, U(t,1), 'w', t, U(t,L/3), 'r', t, U(t,L), 'g') %print -dwinc

Two examples of results from the simulator are give in figure 4.11 and 4.12.

Figure 4.11 shows the time evolution of the voltage on the line at different positions for an interconnection with positive reflection coefficients at source and at termination. All steps are positive, and the voltage at any point of the line is a monotonic staircase.

Fig 4.12 shows the time evolution of the voltage on the line at different positions for an interconnection with positive reflection coefficient at termination and negative reflection coefficient at source. This situation corresponds to a high current driver connected to an open line (termination resistance much higher than characteristic impedance). Now


steps invert direction on any bounce at the driver side. The waveform can oscillate, and cause multiple threshold crossing.

5.7 Examples of results

Fig 4.11 V(x,t) with positive reflection coefficient at source and at

termination.


Fig. 4.12 V(x,t) with negative reflection coefficient at source and positive reflection coefficient at termination.


1) When VTH > VA / 2, the maximum transmission time for a line matched at source and at termination is:

• tTXmax = 0 , • tTXmax = tP , • tTXmax = 2tP , • *the system does not work.

With matched source the first step is VA / 2; due to matching at the far end (termination) this is also the final voltage on the line. The voltage on the line never crosses the threshold.

2) When VTH < VA / 2, the maximum transmission time for a line matched at source and at termination is:

• tTXmax = 0 , • *tTXmax = tP , • tTXmax = 2tP ,


• the system does not work.

With matching at source and at termination the first edge (incident wave) reaches the far end in = tP, and there is no further reflection. All points on the line are reached within this time.

3) In which configuration can the line voltage have multiple threshold crossing ? (RO is the output resistance of the driver; Z0 the line impedance, RT the termination resistance)

• RO >> Z0, RT = Z0, • RO > Z0, RT = , • RO << Z0, RT = Z0, • *RO << Z0, RT = .

Multiple threshold crossing occurs when line voltage oscillates; this requires the composition of waves with opposite polarity, which are generated by a negative reflection coefficient at source.


6 Design guide for interconnection 6.1 Summary

The previous lesson presented how transmission line effects influence the waveform of digital signals. Here we shall review how the designer can manage these effects, in order to guarantee the correctness of information transfer.


• What are the effects of capacitive loads on bus lines? • What does "IWS driver" mean? • Which termination circuits are used in real systems? • What are "parallel" and "series" terminations? • What is the difference between point-to-point and bused lines?

6.2 Incident wave switching

Incident wave switching (IWS) occurs when the receiver can sense the logic state change on the first step impressed to the line. To guarantee this condition, the first step must be higher than the threshold VTH, and this means Z0 >> RO. This can be obtained by lowering the output resistance RO (that is using high-current drivers), and by keeping the characteristic impedance Z 0 as high as possible.

Example 1

The design specifications require to get IWS on an interconnection with:

• Threshold voltage VTH = 2.5 V, • Characteristic impedance of the interconnection Z0 = 70 , • Open circuit output voltage from the driver in the High state: VA = 4 V

The designer can derive either the specification for the driver equivalent output resistance RO, or the minimum value for driver output current IOH.

The amplitude of the first incident wave (first step) can be evaluated from the open circuit output voltage, partitioned among the drive output resistance and the line impedance:


fig 5.1

VB = VA * Z0 / (Z0 + RO), which solved in RO gives: RO = Z0 * (VA / VB - 1) RO <= 42

An alternate specification is the output current IOH; the voltage VB can be written as:

VB = Z0* IOH

To achieve IWS VB must be higher than the threshold voltage VTH, that is:

IOH = VB / Z0 IOH >= 35,7 mA

6.3 Effects of capacitive loading

The characteristic impedance Z0 depends on the unit capacitance and inductance C' and L':

When new receivers or transceivers are connected to the line (eg in backplane buses, as in figure 5.2), their input parasitic capacitance adds to the intrinsic line capacitance.

Fig 5.2 Model for a multi-tap interconnection.


The unit capacitance increases and therefore the characteristic impedance Z0 decreases. If the added unit capacitance is C", the characteristic impedance changes from

to

that is it is reduced by a factor

Example 2

A line with characteristic impedance Z0= 70 has unloaded unit capacitance C' = 50 pF/m (no-load). We connect to the line 20 loads, 30 pF each (equivalent capacitance on a transceiver I/O pin) equally spaced over 50 cm.

What is the new value Z0" of the line characteristic impedance?

The distributed loads account for an additional unit capacitance

C" = (30 pF x 20 loads ) / 0.5 m = 1200 pF/m.

The reduction factor is ; therefore Z0" = 70/5 = 14 .

The minimum value for driver output current IOH to achieve IWS (other parameters as in previous example) is now:

VB = Z0" * IOH IOH = VB / Z0 " IOH >= 178 mA

Such current is far higher than IOH of commercial logic devices.

6.4 Termination circuits

The current flowing in the termination resistance RT must come from (or go into) the driver. In the previous examples the termination resistance RT was always connected to ground. To drive a line with termination connected to ground at values higher than VTH, the driver must have high IOH. No current is required in the Low State.


If the termination resistance is tied to VCC (or to any voltage close to VOH), no current flows in the high state and the current is about VOL / RT for the low state. In this case the driver must have high IOL.

For matched lines (RT = Z0) the current may rise to rather high values. For instance, with a termination RT = 70 and VCC = 5 V the output current IOL

= = 70 mA. This current flows into the driver, and adds to receiver input currents.

Due to asymmetry in the output stage, IOL is usually higher than IOH, and therefore termination resistances are usually connected towards VOH rather than to ground. In the case of Open Collector drivers, the termination resistance acts also as pull-up resistance.

Several circuits can be used for terminations; some of them reduce the output current required from the drivers:

6.4.1 Passive termination

This termination is a simple pull-up towards VCC or a termination voltage VT (fig 5.3).

Fig 5.3 Single-resistance termination.

The voltage VT can come from a voltage divider or from a voltage regulator (fig 5.4).

Fig 5.4 Termination to a voltage other than VAL.


If VT > VOH , the regulator must always supply a current. If VOL < VT < VOH, the regulator must have current sink and source capability. Usual 3-term regulators (eg the 780x series) are not suitable in this last case; special regulators are available from the manufacturers.

6.4.2 Low power termination

The termination resistance is connected to signal ground though a capacitor, as in figure 5.5. On a voltage step, the capacitor acts as a short circuit, and the line is terminated by RT . For steady line no current flows in the capacitor, and there is no static power consumption.

Fig 5.5 Passive low-power termination.

6.4.3 Active low power termination circuit.

The non-inverting buffer with positive feedback acts as a bistable circuit which follows the state of the line (fig 5.6). On a state change, current flows in RT only as long as the output has not changed state. For a steady line no voltage difference appears on RT, and no current flows.

Fig 5.6 Active low-power termination.

For any of these circuits, diodes connected to ground or to the power supply clamps spikes caused by reflected waves or by reactive devices (fig 5.7).


Fig 5.7 Clamping the far end to block noise spikes.

6.5 Driving point-to-point lines

This section describes the signals in transmission lines driven from one end. The first case discussed is a line open at the far end ( T = 1) and matched at the driver (RO = Z0).

The first step in B (t = 0) has amplitude VA/2 (partition of VA on RO and Z0). At t = tP the first step reaches the far end (C), and is incremented by the reflected wave (with the same amplitude, since T = 1). The total step is twice the first step in B. At 2 tP the reflected wave comes back to the near end (B) and adds to the first step.

The system is now in its final state; there is no further reflection because the driver side of the line is matched. The waveforms are in figure 5.8 (where 1 tP corresponds to 2.5 horizontal divisions).

Fig 5.8 Near end (top trace ) and far end waveforms for an open

line with matched driver.

We will now analyse the same circuit as in the previous example (line open at the far end: T = 1, with the driver no longer matched (RO < Z0,


G < 0). Such mismatching occurs whenever we use high current drivers to get a high first step, because of their low equivalent output resistance.

Since G < 0, the signal reflected at the driver has opposite polarity with respect to the original step. The steps on the line can be either positive or negative, with sign inversion every 2 tP, (the time distance between reflections at driver).

At the far end C, where incident and reflected wave sum with the same polarity, the actual waveform can oscillate. These oscillations may bring the voltage to cross several times the logic threshold VTH, thus causing additional logic state changes.

Fig 5.9 Near end (top trace) and far end waveforms for an open line with high-current, low-resistance driver.

To avoid unwanted logic state changes caused by high current drivers we could match the line at the far end. This parallel termination is a load, and increases static power consumption.

Another possibility to block oscillations is to match the line at the driver side, with a resistance RG connected between the line and the driver output, as in figure 5.10. If RG + RO = Z0 , the total equivalent resistance at the driver side is RO' = Z0, and the backward wave (travelling from C to B) is fully absorbed at the driver.

Fig 5.10 Series termination.


At the driver side we can observe a double step (incident wave at t=0, reflected wave at t = 2 tP; on the open end we get a single step with double size (incident plus reflected wave) at t = tP.(Figure 5.11).

This technique is called series termination, and is widely used to drive address and control lines of small memory banks. It uses less power then parallel termination at the far end, but can be used only for point-to-point interconnections, driven from one end.

Fig 5.11 Open line, low resistance driver with series termination.

6.6 Driving bused lines

A driver connected to an intermediate point E of a uniform line with characteristic impedance Z0 is loaded by an impedance Z0/2 (Fig 5.12). To get incident wave switching, the driver output impedance must be very low (that is, the driver must be able to source or sink a high current). In the node E we have three parallel branches, respectively with impedance Z0, Z0, and RO. The equivalent impedance in E is always less that Z0, and the corresponding reflection coefficient < 0. The polarity of reflected waves is inverted and the voltage on the line can oscillate as in the previous example.

Since another branch of the line is connected at driver output, source termination in the node E is not possible (Z0 in parallel to any other impedance is always less than Z0). To absorb the reflections it is necessary to terminate the line at both ends. This is the typical case of multipoint buses (for instance backplane buses, where several boards can be connected at many positions).


Fig 5.12 Line driving from an intermediate point.

In multi-point buses, many devices (active driver, receiver, disabled drivers, and passive loads) are tied to each line. The capacitive load lowers the propagation speed and the characteristic impedance of the line (a 100 line can go below 20 due to additional capacitance; the propagation speed scales the same factor). Driving low impedance lines requires high-current devices, and high current means more heat to dissipate and more noise towards other circuits (that is a EMC problem). Therefore it is mandatory design practice to limit the capacitive load on each line.

The board must use a single transceiver towards the bus (figure 5.13, left). The transceiver isolates all on-board circuits and reduces the capacitive loading on bus lines. Direct connection of on-board devices to bus lines (figure 5.13, right) must be avoided, since it increases the capacitive load and lowers the characteristic impedance.


Fig 5.13 Interfacing a daughter- board with a backplane bus.

L and C parasitic parameters are proportional to track length; to keep them to minimum values, the transceiver must be placed as close as possible to the board connector. For the same reason the smallest acceptable package should be used; SMD devices are preferred towards PTH (figure 5.14), because of smaller size and shorter pin connections which keeps low parasitic capacitance and inductance.

Pin Though Hole (PTH) devices Surface Mount Devices(SMD) Fig 5.14 Comparison among different packages.


6.7 Design guidelines

High-speed logic systems must use multiple layer Printed Circuit Boards (PCBs), with alternated signal layer and ground/supply layers, to provide a controlled environment for signal propagation. Example of signal track layers and ground plane are in figure 5.15.

Fig 5.15 Tracks and ground plane in a PCB.

In summary, to get high transfer speed and reliability in a multipoint bus connection we must:

• limit capacitive loading by inserting isolation buffers on each board;

• place drivers and receivers as close as possible to the bus connector;

• choose small packages, with low parasitics; • use multilayer PCB, to get a well defined transmission

line environment.


1) The correct value of a series termination resistance RS is: (RO is the output resistance of the driver; Z0 the line impedance, RT the parallel termination resistance)

• RS = Z0 + RO • RS = RO - RT • RS = Z0 - RT • *RS = Z0 - RO

The sum of driver output resistance and external series termination must equal the line characteristic impedance.


2) To avoid reflections with mid-point driving bused lines, one has to:

leave line ends open,

put series termination on all drivers,

*place matched parallel termination at both ends,

place matched parallel termination at one end only.

Since three branches (two transmission lines and the driver output) converge at the driving node, it is not possible to match the line at the driver side. The only possibility is to avoid reflections at the far ends, by matched terminations.

3) In a mid-point driven 100 ohm bused line, the amplitude of the first step, for VA = 5 V, RO = 50 , is:

• 1 V, • 1.25 V, • *2.5 V, • 5 V.

The driver sees a Z0 / 2 load (Z0 // Z0 ). Use of the equation: VB = VA * Z0 / (Z0 + RO) gives:

VB = 5V * 50 / (50 + 50) :

4) A 20cm PCB track with unit capacitance 30 pF/m is loaded with 10 loads with equivalent capacitance 10 pF, evenly spaced. The unloaded line impedance is 150 . The approximated loaded line impedance is:

• 200 , • 100 , • 10 , • *35 .

The loaded line impedance can be calculated as: ; since the

unloaded impedance is the impedance reduction factor is

.


The added unit capacitance is C" = ((10 x 10 pF) / 20cm ) x 100cm) = 500 pF/m.

Loaded line impedance Z" = 150/4.2 = 35.68 .


7 Signal Integrity in Digital Circuits

7.1 Crosstalk 7.1.1 Summary

Conductors running side-by-side (e.g. bus tracks) exhibit capacitive and inductive coupling. Due to these couplings, a signal driven on one line can induce noise on the other ones; this behaviour is called crosstalk.

The first lesson answers the following questions:

• What does "signal integrity" mean? • What are typical signal integrity problems? • What are the effects of mutual coupling among PCB conductors? • How can mutual coupling cause false signalling?

7.2 Examples of signal integrity problems

1) In a bundle of wires only some of them are active (that is carry logic transitions), but signals appear also on non-active conductors. This is a crosstalk problem, and can be handled by proper selection of driving devices and wiring layout.

Figure 1.1 Crosstalk from capacitive and inductive coupling.

2) A pulse is applied to one input of a buffer; the other inputs of the same package are fixed at High or Low levels. The voltage at the outputs corresponding to steady inputs change state when other devices in the same package switch. This can be caused by ground bounce noise - a common-path crosstalk problem - and can be avoided by proper layout and decoupling of the power supply.


Figure 1.2 Crosstalk caused by ground bounce.

7.3 Simplified Model for Crosstalk Analysis

The reference model for a first approximation analysis of crosstalk consists of two wires (or PCB tracks) running close to each other, as in figure 1.3.

Figure 1.3 Two coupled tracks.

For this analysis the wires are modeled as two transmission lines with characteristic impedance Z0 and both capacitive (CM) and inductive (LM) coupling. To avoid multiple reflections, both lines have matched terminations RT = Z0. (figure 1.4).


Figure 1.4 Transmission line model for Crosstalk analysis.

The driven line (or active line, always drawn in the upper part of the diagram) carries a signal moving at speed U. This signal is a voltage step with rise time tr and slope dv/dt = DV/tRr. (Figure 1.5).

Figure 1.5 Disturbing signal.

The effects of capacitive coupling can be evaluated with the model shown in figure 1.6. The equivalent circuit includes a voltage generator VM, the coupling capacitance CM, and the impedance Z0/2, which models the resting (or passive) line.


Figure 1.6 Model for capacitive Crosstalk

If the voltage change VSC on the passive line is small, the whole step VS appears through the capacitor CM. A current ICM = CM dv/dt flows from the capacitor to the load Z0/2. This rectangular current pulse generates a voltage pulse with the same duration tr. and amplitude VSC = ICM Z0/2. In summary:

This pulse propagates on the passive line towards the two ends of the passive line, thus making the Backward Capacitive (BC) and Forward Capacitive (FC) terms of crosstalk (figure 1.7).

Figure 1.7 Forward and backward propagation of the capacitive term

The inductive coupling causes on the passive line a voltage proportional to the concatenated magnetic flow change, and therefore again to dv/dt. The induced voltage is VSL = LM di/dt .

Figure 1.8 Model for inductive crosstalk


Also this voltage propagates on the passive line towards the two ends with opposite polarity in the two directions: Backward Inductive (BL) and Forward Inductive (FL) terms of crosstalk (figure 1.8). In this case, since the induced disturbance can be modelled by a voltage generator serially connected along the passive line, the backward and forward pulses have opposite polarity.

Figure 1.9 Forward and backward propagation of the inductive term

7.4 Forward and backward crosstalk

In summary, the disturbing signal propagating on the active line puts on the passive line four noise signals or crosstalk terms, all with amplitude proportional to dv/dt and duration tr:

1. Crosstalk caused by coupling through CM , which propagates towards the termination (right side): Forward Capacitive crosstalk FC;

2. Crosstalk caused by coupling through CM , which propagates towards the driver (left side): Backward Capacitive crosstalk BC;

3. Crosstalk caused by coupling through LM , which propagates towards the termination (right side): Forward Inductive crosstalk FL.

4. Crosstalk caused by coupling through LM , which propagates towards the driver (left side): Backward Inductive crosstalk BL.

The total crosstalk moving towards the right end (far end, termination), in the same direction of the disturbing signal is the forward crosstalk FT = FC + FL . Forward crosstalk is the sum of terms 1 and 3 above; since they have the same polarity, if dv/dt > 0 (for the disturbing signal), the forward crosstalk is always positive.


The total crosstalk moving towards the left end (near end, driver), in the opposite direction of the disturbing signal is the backward crosstalk BT = BC + BL. Backward crosstalk is the sum of terms 2 and 4 above; since they have opposite polarity the actual polarity of backward crosstalk depends on the prevalence of capacitive (2) or inductive (4) term.

The above mentioned disturbances are generated on each elementary section of line: the actual voltage v(x,t) at any point of the line is the sum of all these contributions. The disturbing pulse moves towards the far end with speed U, and the forward term moves in the same direction at the same speed. At any point along the line all the forward terms previously generated arrive at the same time, and sum up to make a single pulse of width tr and increasing amplitude as it moves along the line towards the far end. The forward term at different points along the line is visualized in figure 1.10. These are the signals, which can be observed on a scope connected to the resting line, when an edge travels along the disturbing line.

Figure 1.10 Forward term of crosstalk

Backward terms sum in the time domain and make a pulse with fixed amplitude and width related to position along the line.

When the disturbing edge reaches the far end at t = tP, it is absorbed by the matched termination, and the corresponding noise generators turn off. The forward term ends immediately; the various points along the line


return to the resting voltage as the "turn off" propagates backwards towards the driver.

Figure 1.11 Backward term of crosstalk

7.5 Examples What is Crosstalk? Crosstalk is the interaction between signals on two different electrical nets. The one creating Crosstalk is called an aggressor, and the one receiving it is called a victim. Often, a net is both an aggressor and a victim. An electrical current in a loop generates a magnetic field. If this magnetic field is changing, it can either radiate energy by launching radio frequency waves, or it can couple to adjacent loops ("Inductive cross-talk").


The voltage on a line creates an electric field. If this electric field is changing, it radiates radio waves, or it can couple capacitively to adjacent lines ("Electrostatic cross-talk").

When does a line or loop radiate radio frequency waves? Basically, if the line or loop has signal energy at a frequency high enough that the line or loop represents at least a tenth of a wavelength, there will be a measurable amount of electromagnetic radiation ("Radio waves").

When does a line or loop radiate radio frequency waves? • Basically, if the line or loop has signal energy at a frequency high

enough that the line or loop represents at least a tenth of a wavelength, there will be a measurable amount of electromagnetic radiation ("Radio waves").

• λ(60MHz) = 5 meters • ? 600MHz)= 0.5 meters


Difference between SI and EMC • Signal Integrity (SI), how a system affects itself. Signal integrity is the ability of a signal to

generate correct responses in a circuit. A signal with good signal integrity has digital levels at required voltage levels at required times.

• Electromagnetic Compatibility (EMC), interactions with the environment. It results from the antenna properties of a transmission line (such as a cable, route or package pin).

The following drawings are taken from an algorithmic simulator, which separates the waveforms of forward and backward crosstalk components for different capacitive and inductive couplings. This split is not possible in real systems, where the voltage at any point of the line is the sum of forward and backward waves. The three diagrams are snapshots of the voltage on the disturbing line (upper diagram), and of forward and backward terms on the resting line (respectively second and third diagram from the top). Note that these diagrams represent v(x) at a given t; they are not v(t) diagrams taken at given points on the line, like the scope diagrams in figure 1.10 and 1.11. The waveforma are idealised (rectangular pulses); in real systems edges are rounded, and rise/fall times of crosstalk signals are not zero.

The first diagram (Fig 1.12) shows the crosstalk voltages at t = tP/3, for a given combination of dV/dt (rise time tr of the disturbing edge), CM , and LM (the values of these parameters shown in the box at the bottom right corner are only for comparison of different situations).

Figure 1.12 Crosstalk noise at t = tP/3.

Figure 1.13 shows the same waveforms for the same system at a later time t = 2 tP/3 . The forward term amplitude increases (due to summation


of contributions along the line), but the duration is still t r, while the backward term keeps the same amplitude but longer duration.

Figure 1.13 Crosstalk noise at t = 2 tP/3

In the third diagram (Fig. 1.14), the ratio among capacitive and inductive coupling is inverted: the capacitive term overcomes the inductive one, and the polarity of the resulting forward term is reversed.

Figure 1.14. Crosstalk noise at t = tP/3, with higher capacitive coupling.

The effects of edge slope are shown in figure 1.15. All parameters are the same in both cases, the only difference being the slope of the disturbing signal rising edge. Since crosstalk amplitude is proportional to the slew rate, the steep edge causes a higher noise. The disturbance lasts for the duration of the edge, and is close to 0 when the active line does not change state.


Figure 1.15 Crosstalk pulses for steep and slow edges

7.6 Near-end and Far-end crosstalk

The actual crosstalk signals in a real system are the sum of all contributions (inductive, capacitive, forward and backward terms). Due to different propagation directions, the waveforms depend on the observation point: a scope connected to different points shows different wave shapes. Summarising the previous analysis:

At the near end all terms start for t = 0; the backward term ends when the disturbing pulse reaches the far end, and the induced noise generator is turned of (at t = tP). This information (or the negative edge caused by turning off the disturbing pulse at the far end) needs another tP to reach the near end, therefore the total duration of crosstalk noise at the near end is 2 tP (track A in figure 1.16).

The disturbing pulse (and induced noise) reaches the far end at t = 2 tP (nothing can be seen before). The forward term (narrow pulse with width tr) is the sum of all contributions along the line; the backward term ends almost immediately, as the disturbing pulse reaches the far end at the same time at t = 2 tP. Therefore the far-end crosstalk is a narrow pulse, occurring at t = 2 tP , with sign and amplitude related with the actual LM and CM values (track C in figure 1.15). At the intermediate position (track B in figure 1.16) we can observe the forward term (narrow pulse, variable height), followed by the backward term (rather flat pulse, width depending on the position).


Figure 1.16 Measurement of total crosstalk.


1) A processing system suffers intermittent failures; the error rate changes (but never goes to 0) when the power supply voltage changes by a few %, some ICs are replaced, or interface boards are moved to other slots. The correct countermeasure is:

• rewrite the program in another language, • analyse the OS interfaces, • *revise the electrical design, focusing on dynamic interfacing and

signal integrity aspects, • put a voltage regulator on the power supply.

These symptoms reveal random errors, which cannot depend on the SW (repeating the operations with the same data should give identical results), nor on the power supply. Too narrow electrical interfacing margins make the system sensitive to noise and disturbance, which cause small changes in signal levels and power supply voltage.

2) The term which best describes the problem addressed by signal integrity is


• static compatibility of logic circuits • power consumption of logic circuits • *dynamic behaviour of logic signals and circuits • correctness of Boolean operations performed by logic gates

Static compatibility is also a condition to fulfil, but the correctness of dynamic behaviour requires also static compatibility.

3) The amplitude of crosstalk noise is

• *proportional to the slew rate (dV/dT) of the disturbing signal • inversely proportional to the slew rate (dV/dT) of the disturbing

signal • not affected by the slew rate of the disturbing signal • proportional to the duration of the disturbing signal

The crosstalk is directly proportional to mutual coupling (capacitive and inductive) and on slew rate of signals. Steep edge, with fast slew rate push more noise through capacitive and inductive coupling.

4) The backward crosstalk noise term at the near end has:

• fixed amplitude, duration tr, • fixed amplitude, duration proportional to line length, • amplitude proportional to line length, fixed duration, • amplitude and duration proportional to line length,

The backward term can be seen as the sum of all contributions along the line, originated when the disturbing pulse travels towards the far end. When the pulse reaches the far end (for a matched line), it is absorbed by the termination. The backward pulse duration is therefore twice the propagation time, which in turn depends on line length.

5) The forward crosstalk noise at the far end has:

• fixed amplitude, duration tr , • fixed amplitude, duration proportional to line length, • *amplitude proportional to line length, fixed duration, • amplitude and duration proportional to line length.

The forward term can be seen as the sum of all contributions along the line, originated when the disturbing pulse travels towards the far end. Since these elementary contributions travel towards the far end at the same speed as the disturbing pulse, their amplitude increases as the signal moves toward the far end. The final peak value is therefore proportional to the length of the line.


6) At the near end we can observe a crosstalk noise pulse with duration

• tr, • 2 tr, • tP, • *2 tP,

The total width of the near end crosstalk pulse depends on the time required by the disturbing signal edge to travel along the line (tP), plus the time required by the negative edge (the crosstalk noise turn-off) to come back to the near end (another tP).

7) At the far end we can observe a crosstalk noise pulse with duration

• *tr, • 2 tr, • tP, • 2 tP,

The far end crosstalk pulse is the sum of all elementary contributions along the line, which move towards the far end at the same speed as the disturbing signal. They sum in the amplitude domain, and the pulse width corresponds to the width of each elementary contribution (t r).

8) If the characteristic impedance Z0 of the disturbed line increases, the capacitive term of crosstalk:

• does not change, • *increases, • decreases.

The amount of capacitive crosstalk depends on the partition among the mutual capacitance CM and the line characteristic impedance Z0. As Z0 goes up the attenuation decreases, and the noise transferred through capacitive coupling to the resting line increases.

9) if we connect a scope at the middle point of the disturbed line we will observe:

• a pulse with duration tP followed by a spike of duration tr, • a pulse with duration 2tP followed by a spike of duration tr, • *a spike of duration tr, followed by a pulse with duration tP, • a spike of duration 2tr, followed by a pulse with duration 2tP.


The signal at any point is the sum of the forward term (a spike of duration tr) and the backward term (a pulse with duration twice the fly time from that point to the far end, that is tP for the line middle point).

10) If the length of a couple of lines is doubled (and all other parameters per unit length remain unaffected):

• the amplitude of near-end crosstalk doubles, • *the amplitude of far-end crosstalk doubles, • the width of far-end crosstalk doubles, • the amplitude and the width of near-end crosstalk doubles.

The far end crosstalk pulse is the sum of all elementary contributions along the line, which move towards the far end at the same speed of the disturbing signal. Therefore the amplitude of far end crosstalk is proportional to the line length.


8 Design Guide to Handle Crosstalk

8.1 Summary

The physical laws that causes crosstalk cannot be modified, but proper design can keep under control both the amount of crosstalk (passive countermeasures), and its effects (active countermeasures). This lesson presents the design technique for electronic systems which allows us to reduce the errors originated by crosstalk.

The following questions can be answered in more detail by this lesson:

• What are the actual effects of crosstalk? • How can the designer keep these effects under control? • What does "active countermeasures" mean, and how can it be put

to work? • What are the "passive countermeasures" at the circuit and system

levels?

8.2 Effects of Crosstalk

The previous lesson described how mutual coupling can induce noise pulses on conductors which should stay in a fixed logic state. These pulses have amplitude and width related to the characteristics of the disturbance signals and the electrical parameters of the system. For instance, the capacitive term can be evaluated as:

and the inductive term:

If these voltages and currents cross the logic threshold of logic devices, they may be interpreted as false logic states. The goal of the designer is to avoid errors caused by these spurious logic states, and can be achieved through a series of countermeasures:


Passive countermeasures limit the amount of crosstalk noise, by controlling the parameters of the signals and of the physical system.

Active countermeasures limit the effects of noise towards logic circuits (the spurious pulses, even if present, are not translated into a false logic state). These techniques exploit some characteristics of noise signals, such as the limited duration or energy. The top level active countermeasures include error correction techniques, which can mask errors at the electrical level, and are not addressed here.

8.3 Passive countermeasures

Both the capacitive and the inductive terms are proportional to the disturbing signal slew rate

, or, for a simplified triangular wave . To reduce the slew rate we can reduce DV or increase tr .

Reducing DV means using low-voltage logic devices (which provide benefits also for power consumption and external EMI). Unfortunately a simple voltage scaling also affects the logic threshold; if we reduce the voltage difference among the HIGH and LOW logic states, the noise margin is proportionally reduced, and lower noise pulses can still cause false signalling. To keep the noise margin we must use devices with tight control of threshold; these are discussed in the active countermeasure section.

Increasing tr means using low-speed logic circuits (the slowest logic family which allows to fulfilment of timing specifications). The slow transition among logic states may cause other problems (eg. long totem-pole current pulses - see lesson 3). A first fundamental design rule is:

Use the slowest logic family compatible with speed requirements of the system.

Controlled slope drivers have been designed for best performance in driving long lines. These devices keep dv/dt under control even in fast switching circuits. The output stage consists of several transistors which are turned on in sequence. The total equivalent resistance is low, but the current is kept to a limited value (at the expense of an increase in the switching time).


Figure 2.1 Controlled slope waveform.

The other key parameters are the capacitive and inductive coupling.

All printed circuit boards (PCBs) and cables exhibit capacitive coupling among tracks or conductors. A proper use of screens and ground conductors may substantially reduce these parasitic capacitances.

Mutual capacitance in printed circuit boards depends on the distance between tracks and from adjacent grounds. Ground tracks and ground planes add capacitance between signal tracks and grounds, but reduce mutual track-to-track capacitance.

• internal ground layer: cuts capacitive coupling between tracks on external sides (Figure 2.3);

• alternating signal-ground tracks: cuts capacitive coupling between adjacent tracks (Figure 2.4);

• ground-signal-ground sandwich: the characteristic impedance is precisely defined, and couplings are minimized (Figure 2.5).

Figure 2.2 Standard PCB

Figure 2.3 Reducing capacitive coupling with a ground plane.


Figure 2.4 Reducing capacitive coupling with interleaved ground track.

Figure 2.5 Multilayer PCB with ground and power planes.

The qualitative effects are summarised in the following table:

PCB track without ground plane Zo 200

ohm Crosstalk 50%

PCB track with one ground plane Zo 80 ohm Crosstalk 25%

PCB track with ground plane on both sides Zo 100

ohm Crosstalk 11%

A second fundamental rule, for PCB and interconnection systems (cables) designers is:

Reduce capacitive coupling by separating wire/tracks and by using screens (ground layers, ground tracks);

Inductive coupling is more difficult to visualise than mutual capacitance: there is no real "magnetic screen", but the designer can manage to avoid transformer-like structures, which exhibit high mutual inductance.

In digital systems signal and ground return make loops, as in figure 2.6.


Figure 2.6 Signal-ground loop.

Ground currents follow the lowest impedance path, that is the minimum resistance for DC or low frequency, and minimum inductance path for high frequency components. The inductance is proportional to the concatenated magnetic flow of a wire loop, which depends on the loop area. Therefore to keep inductance low we must minimise loop area by providing a return path as close as possible to the signal conductor.

When the PCB has a continuous ground plane, the return current follows a minimum impedance path with minimum loop area, that is as close as possible to the signal conductor, as in figure 2.7a.

In the ground plane of a multilayer PCB, holes are used to create conducting vias among different layers. A group of adjacent holes makes a slot. Holes and slots break the ground plane and force currents to form more wide loops (for this aspect slots are worse than holes). Return paths looping around a slot is shown in figure 2.7b.

Figure 2.7 Photo of the ground plane in a multilayer PCB. The yellow line corresponds to the signal track (on another layer).


1. The green return path can travel on the ground plane without forming loops

2. The return path must loop around a slot.

On connectors and flat cables, special care must be taken in positioning ground pins and wires. If the return current flows far from the corresponding signal the path makes wide loops.

Figure 2.8 A wide loop can be made thinner by moving the GND pin near the signal pin.

If the loops made by signals and ground returns have significant shared area, they make a transformer (with single-turn windings in air), with high mutual inductive coupling. If the loops have no common area, the inductive coupling is minimised (figure 2.9).


Figure 2.9 Two nested loops can be decoupled using independent GND pins for each signal.

Flat cables, with several conductors running at close spacing for some distance, may have strong inductive coupling. Independent ground returns on pins close to signals, minimises the inductive coupling, while using the same pin for return currents from several signals creates nested loops with high mutual inductance, as shown in figure 2.10.

Figure 2.10 Signal (Si) - Ground loops in a flat cable. The number of GND connections is the same in both cases, but b) exhibits far less inductive

coupling.

A similar problem occurs with arrays of termination resistors: devices with a common VT pin shared by many termination resistances have mutual coupling higher than independent-resistors arrays.


Figure 2.11

a) termination array with common VT pin: high inductive coupling,

b) independent resistors termination array: low inductive coupling.

A third fundamental design rule for designers is therefore:

Reduce loop areas by providing return paths as close as possible to signal paths,

and

Reduce inductive coupling by avoiding nested loops.

8.4 Active Control of Crosstalk

Controlling the slope of signal edges is a passive countermeasure, which reduces the amount of generated noise. The same technique can be used to blocks short spikes. A dV/dt limiter (a logic buffer with controlled slope) in the signal path can filter short noise pulses.

Figure 2.12 Effect of a slew rate limiter


Both the inductive and the capacitive terms of crosstalk have a duration shorter than 2 tP ; if the logic circuits are not sensitive to logic state changes with duration shorter than 2 tP , crosstalk pulse - even if present - is blocked before entering the logic devices. This time-filtering function is accomplished by integrating receivers.

The block diagram of an Integrating Receiver is in figure 2.12:

Figure 2.12 Block diagram and signals for an integrating receiver.

The input signal V1 goes to an integrator, and only when the output of the integrator crosses the threshold VTH the output state changes the state. Pulses shorter then a time threshold TTH cannot move the integrator output through the threshold, and are completely ignored. The structure has an intrinsic delay of at least TTH (to decide if a state lasts longer that TTH, it must be observed at least for this time). If TTH = 2 TP,all spurious pulses originated by crosstalk are filtered out.

Another technique to reject crosstalk pulses is to increase noise margins. For the same VOH and VOL that means to reduce the V IH - VIL interval, which requires tight control of the actual threshold value. Some logic families, such as ETL (Enhanced Transceiver Logic) are specifically designed with precisely controlled threshold, as in figure 2.13.


Figure 2.13 Comparison between standard logic and Enhanced Transceiver Logic.


1) Signals with limited slew rate allow

• reduced inductive crosstalk only, • reduced capacitive crosstalk only, • *reduced capacitive AND inducti ve crosstalk, • no effect on crosstalk.

Both inductive and capacitive crosstalk are proportional to the disturbing signal slew rate.

2) Which of the following countermeasures has NO EFFECT on capacitive crosstalk

• use of ground planes, • guard tracks between signal tracks, connected to ground at one

end, • *use of separate grounds for each signal, • avoiding nested signal-ground loops.

Using separate grounds reduces the nested current loops. This reduces mutual inductive coupling, but has no effect on capacitive coupling.

3) Which of the following countermeasures has NO EFFECT on inductive crosstalk

• use of ground planes,


• *guard tracks between signal tracks, connected to ground at one end,

• use of separate grounds for each signal, • avoiding nested signal-ground loops.

Guard tracks act as an electrostatic screen, and reduce mutual capacitance. They could also reduce inductive coupling if used as individual return paths for signal currents.

4) Which is the most effective passive countermeasure to reduce capacitive crosstalk

• PCB with internal ground layer • alternating signal-ground tracks • ground-signal-ground sandwich • *alternating signal-ground tracks, and ground-signal-ground layer

sandwich.

The ground tracks interleaved between signal tracks and the ground layers above and below the track are a good approximation of a complete screen around the signal conductor.

5) Which logic family is the best choice to limit the crosstalk?

• the fastest commercially available within cost budget limits, • *the slowest compatible with timing specifications, • the latest one, independently of speed and cost, • the family which uses less static power.

Using slow logic families keeps the dV/dt of signal edges; the noise towards other parts of the systems is proportional to disturbing signal slew rate. However, the circuit speed must comply with timing requirements (system-operation is a requirement as mandatory as low crosstalk!)

6) Integrating receivers

• block capacitive crosstalk only, • block inductive crosstalk only, • *filter any pulse shorter than a predefined time, • block any pulse longer than a predefined time.

The integrating receiver is a time-domain filter, which allows logic state changes to go through only if they last longer than the time threshold of the receiver. Short pulses are ignored, independently of their origin.


7) Which of the following layouts is more effective in reducing inductive coupling in a flat cable (G = Ground wire, S = Signal wire):

• *S G S G S G S G, • S G G S S G G S, • G G S S S S G G, • S S S S G G G G.

Alternating signal and ground wires minimises the common area of the loops, thus reducing mutual inductive coupling.

8) Slots in ground planes

• *increase mutual inductive coupling, • decrease mutual inductive coupling, • increase mutual capacitive coupling, • decrease mutual capacitive coupling.

Inductive coupling comes from nested signal-return current loops. A continuous ground plane allows return current to circulate as close as possible to the signal track, thus minimising the loop area. A slot in the ground plane may force the current to run on a path longer and away from the signal, thus increasing connection inductance and coupling with other circuits.

9) A sequence of two integrating receivers with time thresholds TF (each)

• Block pulses shorter than TF , • Block pulses shorter than 2TF , • Block pulses longer than TF , • Do not block any pulse.

Signals longer than the time threshold are delayed by an integrating receiver, not modified in any other manner. Therefore the combined effect of a sequence of integrating receivers is filtering with the shortest time threshold, and delaying the sum of individual delays


9 Ground Bounce and Switching Noise

9.1 Summary

The previous lessons concerned spurious signalling originating from capacitive and inductive coupling among interconnecting wires or parts of the interconnection, such as connectors and termination resistances. There are also other sources of noise within the system: when ground and supply paths are shared among different devices, the voltage drop caused by the ground currents of a device may affect the behaviour of other devices. This is the common path crosstalk, which causes simultaneous switching noise and ground bounce, described in this lesson.


• How can common paths cause crosstalk? • What are the causes of ground bounce? • What is the relation between simultaneous switching and ground-

bounce? • Why is ground-bounce a type of crosstalk?

9.2 The totem pole Current Spike

The output stage of logic circuits is made with two active devices (transistors), which act as switches with complementary commands. In a first approximation, the equivalent circuit of a logic output is a SPDT (Single Pole Double Throw) switch, as shown in figure 3.1. (the diagrams show CMOS devices, but similar considerations apply also to bipolar logic circuits).

Figure 3.1 - Simplified model of a logic output.


With such a circuit no current can flow from the power supply VDD to GND - this is the reason for the 0 steady state power consumption of CMOS circuits. A more accurate analysis must take into account the analogue behaviour of the transistors: they toggle among the ON and the OFF states in a soft manner, and go into intermediate states during the logic transitions. When both transistors are in light conduction a current IS flows directly from VDD to GND, as shown in figure 3.2.

Fig 3.2 - Current flow during logic transition (Totem Pole current spike).

The duration of the current pulse depends on the speed of the input transition; if it is too slow (eg if the input is indefinitely kept near VTH), the current flow may damage the device due to overheating. Since only totem-pole outputs exhibit this behaviour (Open Collectors have only one active device towards GND), this current is called Totem Pole Current Spike.

The power and ground connections of Integrated Circuits have some inductance (mainly caused by the package: bonding wires and lead frame. Some examples are in the following table:

Package Inductance on each pin

DIP 14 10 nH DIP 68 100 nH PLCC 10 nH Wire bond 1 nH

Flip chip 0,1nH

Wire bond and Flip-chip have far lower parasitic inductance due to shorter connections.


The current spike at state change is far higher than DC current in steady state, and it causes voltage drops due to the impedance of the ground and power connections. The shift in the ground voltage is:

OR

where tri is the rise time of the current. A similar drop occurs on the power supply lead (inductance LS). The actual supply voltage at the device pin is VALE = VAL - VS - VG.

Figure 3.3 Voltage drops caused by the totem-pole current spike.

These voltages become noise on all other nodes (outputs and inputs) in the same package, and modify both the actual input voltage (thus causing possible false transitions), and the outputs which should stay in a steady state.

This effect can be seen as crosstalk (fake signals from state transitions on nearby signals), caused by common paths, rather than by mutual inductive and capacitive coupling as seen in lesson 1.

The shift in ground potential due to switching noise affects all nodes of the device, and may cause false signalling. It is referred to as ground bounce.


9.3 Current flow in the output capacitance

To change the voltage level VOUT at the output node, the output stage of the logic gate must charge or discharge the capacitance CO associated with that node. This again means a current flow through the output stage from VDD (L-H transitions, figure 3.3) or towards GND (L-H transitions, figure 3.4 ).

Figure 3.4 Charging the output capacitor in a L-H transition

Figure 3.5 Discharging the output capacitor in a H-L transition.

The following values can be used for a first rough evaluation of the actual total capacitance:

Logic inputs: 2 -10 pF Logic outputs: 20-50 pF

Since a significant part of this capacitance comes from the package, smaller packages have lower capacitance.

9.4 Total Ground Bounce

The current flowing in the output of a driver comes through the power and ground pins. The totem pole spike and the output capacitance charge current occur at any output node, and the total current depends on the number of simultaneously switching outputs. When many drivers are included in the same package, the currents for each output must flow through the device power and ground pin. With severe capacitive loading


(such as in buses, where many input or disabled 3-S outputs are connected to each line) the current spike at state change can go to rather high levels.

Numerical example 1:

A logic output drives 10 loads, with equivalent input capacitance of 30 pF each (typical value of equivalent output capacitance for a disabled 3-S output)

The total capacitance is CT = 300 pF

VOL = 0.5 V and V OL = 4.5 V (typical values for CMOS logic)

The voltage change among logic states is 4V; assuming a rise time tf of 4 ns, the current can be evaluated from the relation:

; ;

(current for a single driver, assuming constant slew rate voltage at the output)

The current spike caused by charge and discharge of the output capacitance may cause voltage drops due to the impedance of the ground and power connections, which can be evaluated as

OR

In the previous example, under the assumption of triangular voltage and rectangular current, the current slew rate should be infinite. Therefore we need a better model, as shown in figure 3.6.


Figure 3.6 Linear model (a) and real waveforms (b).

We can analyze the ground bounce for a HIGH-LOW transition, using these simplified models for current and voltage waveforms.

The (equivalent) load capacitor CL is charged at VH and, during the state transition, is discharged to VL. We assume an "ideal" driver, with RO = 0, but will take into account the inductance LG of the interconnection from the drain of the output transistor (lower node of the switch in our model) to the system ground reference. CL is directly connected to the reference ground. The output step from VH to VL is a rounded trapezoidal waveform. The current in the capacitor is the derivative of the voltage:

This current flows in the inductance LG, and causes a voltage drop

which appears directly on the ground pin of the driver, as in figure 3.7.


Figure 3.7 Ground bounce caused by discharge of the output capacitor.

The voltage drop on the ground lead appears directly at the outputs in the LOW state, since these are connected to ground through the driver output transistor. The HIGH outputs are connected to the power supply VCC, and get only second order effects (due to the current spike through the totem-pole output and parasitic coupling).

Figure 3.8 Effects of ground bounce on steady outputs.

The same model can be applied for LOW-HIGH transitions, taking into account parasitic inductance of supply interconnections. Now the voltage drop appears directly at the outputs in the HIGH state, connected to VCC; LOW outputs get only second o rder effects (figure 3.9).


Figure 3.9 Effects of H-L and L-H transitions.

The induced noise is proportional to the current spike, and this in turn is higher when several outputs change state at the same time. This disturbance is therefore called simultaneous switching noise.

Numerical example 2

An integrated circuit contains 8 drivers, in a DIP 20 package. Each driver works in the conditions of example 1 (a current peak of 300 mA when the output changes logic state). The total peak current is

8 x 0.3 = 2.4 A

Assuming a triangular current waveform with total duration 4 ns (the voltage rise time), and peak value 4,8 A (doubled, to keep the same area, which corresponds to the same total charge moved in/out the capacitor), the slew rate of the current is:

With 10 nH inductance for the ground pin (optimistic assumption, since the 20 pin DIL is slightly larger than the 14-pin), the amplitude of the ground bounce is


Since the input signals VI are referred to system ground, the same voltage drop VG appear at the input of drivers, and changes V I to V'I = V I - VG. Therefore the drop on ground lead caused by output current spikes may also induce false logic states a t the inputs.

On inverting buffers with input at the HIGH state, this effect may bring about self-oscillations. As shown in figure 3.10, at t = T1 the actual input voltage V'I = V I - VG crosses the threshold VTH, and that changes the output state, starting the sustained oscillations (not shown in figure 3.10).

Figure 3.11 Start of oscillations in an inverter with capacitive load


1) Simultaneous switching noise caused by low-to-high state change affects

• mostly the outputs at low logic state, • *mostly the outputs at high logic state, • only the outputs at low logic state, • the outputs at low and at high logic state in equal ways.

In L > H transitions the output capacitance is charged from the power supply. The current flowing in the supply pin may shift the actual supply voltage of the device, thus changing the HIGH output level.

2) Simultaneous switching noise caused by high-to-low state change affects

• *mostly the outputs at low logic state, • mostly the outputs at high logic state,


• only the outputs at high logic state, • the outputs at low and at high logic state in equal ways.

In H > L transitions the output capacitance is discharged towards GND. The current flowing in the ground pin may shift the actual ground of the device, thus changing the LOW output level.

3) Increasing the capacitive load

• *increases the ground bounce mostly in H>L output transitions, • increases the ground bounce only in L>H output transitions, • increases the ground bounce both in H>L and in L>H output

transitions, • does not modify the ground bounce.

Increasing the output capacitance increases the amount of charges to be removed to shift the output voltage from VOH to VOL . These charges make the current flowing in the ground pin, which may shift the actual ground of the device, thus causing the ground bounce.

4) Increasing the resistance of common ground connections may cause ground bounce because o f

• totem pole current spike, • charge current in L>H output transitions, • *discharge current in H>L output transitions, • steady-state currents in the IC.

In H > L transitions the output capacitance is discharged towards GND. The discharge current flows in the ground pin, and causes a shift of the actual ground of the device.

5) 16 outputs with a capacitive load of 100 pF each switch together from 5V to 0V ; the fall time is 5 ns; the ground connection has a 1 ohm equivalent resistance. The expected ground bounce is:

• 0.8 V, • *1.6 V, • 3.2 V, • 4.8 V.

The slew rate dv/dt is 1V/ns; the current can be evaluated as I = C /(dv/dt). The total capacitance is 100 pF x 16 = 1,6 nF. Since V = R x I: Ground bounce V = 1 ohm x (1.6 nF / (1 V/ns)) = 1.6 V


10 Design Guide for Ground & Power Distribution

10.1 Summary

Currents must flow in digital circuits to power the active devices and charge/discharge parasitic capacitance; these same currents flow in ground and supply conductors and may cause false signalling because of ground bounce and simultaneous switching noise. This lesson presents the techniques used to distribute ground and supply to ICs in such a way as to minimise this kind of noise. Reducing the disturbance of an electronic system towards itself reduces also the Electro Magnetic Interference (EMI) radiated to the external world.


• How can the designer predict the amount of ground bounce? • Which logic family must be chosen to minimise switching noise? • What is the influence of board layout on switching noise? • How can bypass capacitors reduce ground bounce and switching

noise? • Which are the best techniques to distribute ground and power

supplies in high-speed digital circuits? • How should we distribute clock signals?

10.2 Decoupling Capacitors

To reduce the effects of ground bounce and simultaneous switching the designer should take several steps, some similar to the ones which reduce crosstalk:

• use slow logic circuits; • minimise capacitive loads; • reduce impedance of ground and supply connections; • insert bypass capacitors between supply and ground.

The peak output current depends on capacitive load, that is on the number of inputs connected to the driver. In the case of bus lines, a transceiver insulates the bus line from internal board loads, thus reducing ground bounce in bus drivers.


The model to show the effect of bypass capacitors is in figure 4.1. Two devices receive ground and power supply from partially common conductors. When the output stage of the driver requires some current, it must come from the power supply through the power and ground connection, which have some equivalent resistance and inductance (only the inductance is shown in the equivalent circuit). These currents cause voltage drops, the ground bounce and the switching noise.

The voltage drop on the wire inductance caused by current of device 1 also affects the device 2.

Figure 4.1. Current path with no bypass capacitor.

The bypass capacitor acts as local storage for electrical charges to be used for current pulses caused by the Totem Pole output switch and charge/discharge of parasitic output capacitance. With a bypass capacitor the current flow and voltage drops are modified as in figure 4.2. The voltage drop caused by the current of device 1 does not affect the supply voltage of device 2 (V2). In this scheme however, these drops still affect the power supply of device 1.

Figure 4.2. Current path with a bypass capacitor


A better positioning is shown in figure 4.3: connecting the capacitor directly to the ground and supply pin of the device minimises all voltage drops causes by current flowing in ground or supply conductors (as long as we do not consider the inductance of the capacitor itself - see later).

Figure 4.3 Bypass capacitor directly on device supply pin: the voltage V2 is not affected by currents of device 1.

The bypass capacitor can be placed also in other positions, provided that the current required by device 1 could be supplied without causing voltage drops on the ground/supply connections of device 2. Figure 4.4 is an example of incorrect positioning.

Figure 4.4 Incorrect placements of the bypass capacitor: V2 is affected by drops on L2 and L5.

Even with bypass capacitors, the impedance of ground and power supply conductors must be kept as low as possible. Reducing this impedance reduces the voltage drop for a given current. To reduce inductance,


resistance, and impedance use wide tracks or continuous ground/supply planes.

The impedance of all conductors in the ground-supply path must be low, and this includes the bypass capacitor itself. The impedance of a capacitor should decrease with frequency, but real components have series inductive and resistive components, caused by leads and dielectric losses (figure 4.5).

Figure 4.5 A real capacitor.

The impedance diagram for the real capacitor (figure 4.6) has a capacitive zone (left - for low frequency the inductance can be considered a short circuit), and an inductive zone (right - for high frequency the capacitor can be considered a short circuit), where impedance goes up with the frequency. Between these two, we can define a resonant frequency, where the impedance is reduced to a minimum value (only resistive loss).

Figure 4.6 Impedance of ideal (blue) and real capacitor (red).


The parasitic inductance depends mainly on the package; capacitors o f different values but with the same package have different impedances in the capacitive zone, but almost identical behaviour in the inductive zone. Capacitors with the same nominal value but a different package or different type have identical behaviour in the capacitive zone, and different impedance for high frequency, as shown in figure 4.7a and 4.7b.

Figure 4.7 a) Different capacitance value in the same package

b) The same capacitor in different packages (with different equivalent inductance).

The best bypass capacitors to be placed close to switching devices are multilayer ceramic, shown in figure 4.8 (leaded packages) and 4.9 (surface mount).

Figure 4.8 Multilayer ceramic bypass capacitors in leaded packages (each division on the top is 1 mm)


Figure 4.9 Multilayer ceramic bypass capacitors in surface mount package (compare the size; here too each division on the top is 1 mm).

A first rough rule for effective bypass is to use one multilayer ceramic 10-100 nF, placed close to the IC (about one capacitor every 10 drivers). Capacitor leads add inductance, and must be kept as short as possible; surface mount devices, with direct connection to supply and ground conductors are better than Pin Through Hole (PTH) devices.

The minimum value for a bypass capacitor can be evaluated from the circuit in figure 4.10.

Figure 4.10 Charge sharing from load to bypass capacitance.

The charges from the bypass flow to the load capacitors at the output of drivers. For a DV change on a capacitor CL the amount of charge required is Q = DV CL . This same amount of charge causes on the supply voltage a change DVS = Q CB, and therefore:

DV CL = DVS CB,

CB = DV CL / DVS


For instance, if 16 outputs with 30 pF capacitive load switch together from 0 V to 5 V, and if the desired change in supply voltage is 0.1 V:

CB = 5V (16 x 30 pF) / 0.1 V = 24 nF

Higher values can be used, as long as this does not increase the parasitic inductance. Consider that large capacitors (eg aluminum electrolytic) have good behavior at low frequency, but the wide case causes large inductive components. To achieve low impedance over a wide range of frequency we must put in parallel capacitors of different values and types. Small ones will be placed as close as possible to the switching devices, to supply the charges through low-inductance wires (typically one capacitor per small package). Large ones are placed on arrays of packages, or at board level.

Figure 4.11 Impedance of several parallel capacitors.

10.3 Placement of bypass Capacitors

Bypass capacitors store charges close to the places where they are needed (the driver IC supply and ground pins), and provide the peak current through low-impedance paths.

The printed circuit boards must be designed with a short distance between power and ground. This is achieved by using power and ground planes, which can be electrically approximated with distributed capacitance. A bypass capacitor as close as possible to the power and GND pins of the device helps to provide a low-impedance path for the transient currents.


Numerical example

Consider a device driving a line from L to H having an impedance (Z @ 100 W) and a supply voltage (Vcc = 5 V). The current needed to shift the line voltage is 50 mA. For eight outputs switching the total current is I = 50 × 8 = 400 mA. This current is provided by the power line (or plane) in a period which can be estimated as 3 times the rise time of the output (for instance approximately 3 ns for ABT). The bypass capacitor must supply the charge in that same period of time to avoid Vcc drop, therefore supply connection inductance becomes an important issue. The inductance is directly proportional to the distance between the lines as well as the length of the lines. By reducing the loops, we can minimise the inductance and allow the capacitor to do its function more efficiently, and hence keep the noise off the power line (or plane).

10.4 Ground and power distribution The most effective technique to keep low inductance in ground and power distribution is to use continuous planes; this is not possible for single layer or double-layer PCB, where ground/power distribution must compete with signal tracks. Suitable distribution schemes are in the following figures. For each scheme the blue arrow (middle diagram) shows the ground-supply loop, that is the path of currents during the Totem Pole switching, and the orange arrow (right diagram) shows the path of the return current for the signal track shown (black line).

The finger layout in figure 4.12 uses only one layer, but forces the supply current and the signal return current to flow in wide-area loops.

Figure 4.12

Rearranging the fingers as in figure 4.13 cuts the supply current loop area, but keeps a wide signal-return loop (and uses two different layers).


Figure 4.13 Dual-comb distribution with reduced loops.

The grid scheme in figure 4.14 requires bypass capacitors on each device to reduce loop area both for supply and return currents (at each crossing a bypass capa citor provides a path for fast-changing currents).

Figure 4.14 Grid distribution scheme and current flow through bypass capacitors

10.5 Clock distribution Distribution of clock signals is a critical issue in high-speed logic systems. The clock synchronizes the operations, and state changes of logic signals are related with clock edge time position. To comply with timing specification of sequential logic circuits, the clock must reach each part of the system at the same time, that is with limited skew tK (the skew reduces the set-up and hold time margins).


Figure 4.15 Skew in clock distribution.

Multidrop connections (figure 4.16) introduce skew because of the different positions of receivers along the line.

Figure 4.16 Multidrop clock distribution.

The star connection, with series termination on each line at the driver side, as in figure 4.17, possibly allows the designer to insert equal delays between the driver and each clocked device. Each interconnection must have the same parameters and length; this equalises the transmission delays. Several lines converge to the same point (the driver output), and it is difficult to get line impedance matching.


Figure 4.17 Star distribution from a single driver.

An even better solution is to drive each line with a separate buffer, as in figure 4.18. Specific devices, with matched-delay buffers are available for this task. With RS = Z0 - RO the interconnection lines are matched at the near end, no reflection occurs on the driver, and each signal is fully settled within 2 tP.

Figure 4.18 Star distribution with multiple drivers.

For better matching of propagation times, line length can be equalised by proper PCB layout; the track follows a winding path, to put a consistent electrical length in a narrow space as in figure 4.19.


Figure 4.19 Equalisation of delays on PCB tracks.

10.6 Review Questions

1) To reduce ground bounce

• use high current drivers • *reduce capacitive loading of outputs • use terminated transmission lines • raise the impedance of ground connections

The ground bounce is caused by the current spike required to (dis)charge the output capacitance. This current increases as the total capacitance at the output of the driver is increased. The termination of transmission lines does not affect the ground bounce, and all other answers bring an increase of the bounce.

2) An acceptable value for local bypass capacitors is

• 10 pF • 100 pF • *100 nF • 10 mF

The bypass capacitor must supply the charges required by the totem-pole current spike, and provide charge or discharge to output capacitance. The actual value can change depending on the parameters of the IC and of the interconnection, but a value of 100 nF is correct in most cases. Too small capacitors (less than 1 nF) cannot store enough charges, and too large ones have larger size with higher parasitic inductance.

3) The bypass capacitor must be placed

• as close to the power supply as possible • as close as possible to devices which need high static current • *as close as possible to devices with high dynamic current

consumption • anywhere in the system

The electric charge stored in the bypass capacitor reaches the output stage of the driver through the ground and supply connections. The voltage drop is proportional to the resistance and inductance of these connections. Placing the capacitor as close as possible to the IC reduces resistance and inductance in the current paths.

4) The preferred device as a bypass capacitor for high-speed digital circuits is:


• aluminium electrolytic capacitor • multilayer ceramic, axial lead • multilayer ceramic, radial lead • *multilayer ceramic, surface mount

The bypass capacitor must have a capacitive behaviour in the frequency range corresponding to the harmonic content of driver current spikes. With 2 ns rise-fall times the significant power of the harmonics is around 50 MHz and above. The best capacitors are SMD, due to very short and low-impedance connections towards the supply and ground plane.

5) A smaller package helps to reduce ground bounce because it:

• has better heat dissipation, • *has less inductance on GND conductors • has less capacitance among adjacent pins • has thinner wires towards ground.

Smaller packages have shorter VDD and GND connections - and therefore less parasitic inductance - from the silicon die to the IC pin.

6) If a capacitor is modelled as a LRC serial circuit, the minimum value of impedance is for a frequency F:

• F = • *F = • F = • F =

The impedance of an inductance L is ZL = jwL, and the impedance of a capacitor C is ZC = 1/jwC. The total impedance is:

Z = jwL + 1/jwC = (-w2 LC + 1)/ jwC

For w2 = 1/LC , Z = 0.

7) For frequency above resonance, a capacitor behaves as

• Pure inductance • Series R and L • Pure resistance • Parallel LC

With a R L C series model, above the resonant frequency the capacitive impedance is far less than inductive and resistive terms. The capacitor can be modeled as a R-L serial circuit.


11 Laboratory Experience 11.1 Summary

This lesson describes how the transmission line behaviour can be verified with some simple laboratory experiments.

The lesson answers to the following questions:

• How can we get experimental evidence of transmission line behaviour?

• Which electronic instruments should be used to analyse signal integrity?

The experience described in the following is part of the course "Electronics of Telecommunications" held at the Politecnico di Torino.

11.2 Aim of the experience The aim of this laboratory experience is to check the behaviour of a transmission line in various operating conditions, and to become familiar with transmission line behaviour. The comparison of the dynamic behaviour of different logic families is also described. We will observe on the oscilloscope the waveforms at both ends of a transmission line driven by a square wave generator (the square wave corresponds to a sequence of voltage steps of alternate polarity). As transmission line we shall use a rather long coaxial cable (10 to 20 meters) to achieve propagation times long enough to allow the use of standard low cost instruments to verify the propagation effects (signal generator and scope).

The experience is repeated in different driving and load conditions:

• line matched at both ends; • line with open far end; • line with unmatched driver.

The sequence of experiments is:

A) Measurement of pulse generator parameters; B) Measure of cable parameters; C) Effects of mismatch at driver and termination ends; D) Effects of capacitive load; E) Time-domain reflectometry; F) Driving a line from logic circuits.


Laboratory equipment required for the experience

• signal generator, 50 W output impedance, transition times < 20 ns; • oscilloscope, 2-channels, 100 MHz minimum bandwidth; • 10 to 20 m of RG58 coaxial cable; • 50 W terminations; • adapters to mount components at cable ends; • resistors and capacitors: 22 W, 100 W, 220 W, 1 nF, • Logic devices of various families (LS, HC, AC, BCT, ...);

For all measurements set the signal generator for square wave, at about 2 V peak, 200 kHz rate.

Connect the signal generator to one end of the cable, and the scope to both ends of the cable using high impedance probes. Use adapters at both ends to mount the required R and C components.

The lattice diagram analysis technique is described in lesson 3 of "Interconnections for high-speed digital circuits".

The experimental setup for all proposed measurements is shown in figure 5.1. A 50 W coaxial cable (type RG 58) is used as the transmission line, and is driven by a pulse generator. The waveforms at source and termination ends are monitored on a scope. Incident and reflected waves can thus be verified in several different operating conditions.

Figure 5.1 Measurement setup


The cable length determines the transmission time tP, and therefore the time scale of all measurements, and in turn the requirements of instrumentation (especially the scope). Using 10 m of cable, all measurements can be performed with a 100 MHz scope, available in most general purpose electronic laboratories. Components at both ends of the cable can be connected using clips mounted on BNC connectors, as shown in figure 5.2.

Figure 5.2 The cable and the test fixtures used for the measurements

11.3 Generator Parameters

1) Verify the no load (open circuit) output amplitude VB from the signal generator (Figure 5.3 a).

2) Connect the signal generator to a known load RL (e.g. 100 W), and measure the new VB; compute the output impedance RO of the signal generator (Figure 5.3 b). The expected result is about 50 W.


Figure 5.3 Measurement of the signal generator output impedance.

11.4 Cable Parameters

1. Connect the signal generator to an open line (the coaxial cable); check the waveform at near and far ends (Figure 5.4), and compare with results from lattice diagrams.

Figure 5.4

The top trace shows signal at source end: the two steps correspond to the incident and to the reflected wave (after 2 tP). Since the source is matched to line impedance, there is no further reflection.

From the waveform at the near end and from the cable length compute the wave propagation speed U.

Expected result for RG58 cable: about 0.7 c.

3) connect a termination; verify the absence of reflected waves.


Figure 5.5 Measurement of propagation speed in the cable.

11.5 Mismatch at driver and at termination

1. Connect a series termination resistance RS (220 W) between the generator and the line.

2. Leave the line open at the far end (GT = 1). 3. From the waveform at near and far ends, compute the reflection

coefficient GG (near end). 4. Compare with results from lattice diagrams. 5. Verify the waveforms at near and far ends. Since both reflection

coefficients are > 0, all steps have the same direction and decreasing amplitude, making an exponential envelope.

6. Compare with results from lattice diagrams.

Figure 5.6 Measurement setup for RO > Z0, line open at far end

Figure 5.7 Waveforms for RO > Z0, line open at far end.

Repeat for a generator resistance lower than characteristic impedance (put a 22 W resistance in parallel to the generator output). Since now the reflection coefficient at source is negative, steps have alternated direction, causing oscillations at the far end.


Figure 5.8 Measurement setup for RO < Z0, line open at far end.

Figure 5.9 Waveforms for RO < Z0, line open at far end.

11.6 Capacitive Load

1) Connect a 1 nF capacitor (CT) at the far end of the line. 2) Verify the waveforms at near and far ends.

For a first approximation analysis, the far end capacitor can be considered a short circuit when the step arrives at the termination (GT = -1), and an open circuit (GT = 1) after the transient. Therefore at t = tP (for the far end) and t = 2 tP (for the near end) the waveform corresponds to a short circuit at the far end. For t >> time constant RC the waveform corresponds to an open line.


Figure 5.10 Measurement setup for transmission line with capacitive load

Figure 5.11 Waveforms in a transmission line with capacitive load.


11.7 7. Time-domain reflectometer The experimental setup used before consists of a step (or pulse) generator and an oscilloscope, and is actually a Time Domain Reflectometer or TDR. The TDR is also built as a complete free-standing instrument and can be used to analyse the state of a transmission line from one side only. The waveforms at the near and far end of an open transmission line with matched impedance at the driver are in figure 5.12. The cable length can be measured from the width of the intermediate step at the near end, which corresponds to 2tP (100 ns in this experiment). The far-end waveform shows a single step, because the incident and the reflected wave appear at this point at the same time.

Figure 5.12 Near end (top trace) and far end waveforms for an open line with matched driver.

If we add another segment of coaxial cable to the far end, the total propagation time is increased (wider intermediate step in the top waveform), and the point C becomes an intermediate point in a longer line. The bottom waveform shows separate incident and reflected waves.

Figure 5.13 Another segment of transmission line is attached at the far end.

The total cable length is still measured by the width of the intermediate step at the near end (about 150 ns in this experiment). The length of the additional cable can be measured from the width of the intermediate step at the point C (previous far end, 50 ns in this experiment). The waveform in C (bottom trace) shows an intermediate step, because the incident and the reflected wave now appear at this point at different times.


Figure 5.14 Near end (top trace) and intermediate point waveforms for an open line with matched driver.

11.8 Driving the line with logic devices Using LS-family circuits, the equivalent output impedance is slightly higher than the cable impedance, and the rising edge exhibits multiple steps (as in the previous experiment C). The different height of the first step shows that output impedance is different for the H-L (red) and L-H (blue) transitions (lower for L-H). This asymmetric behaviour is typical of bipolar logic families (TTL and similar ones), which have IOL > IOH.


Figure 5.15 Open line driven by a 74LS device.

With HC-family drivers the output impedance is close to 50 W and there is almost no reflection at the driver (Figure 5.16, as in previous experiment B). Rising and falling transitions are symmetrical.


Figure 5.16 Open line driven by a 74HC device

For AC-family devices the output impedance is lower than characteristic impedance, and this causes negative reflections with oscillations (Figure 5.17, second part of experiment C).


Figure 5.17 Open line driven by a 74AC device

Clamp diodes at the termination can limit the oscillations. Since logic devices have clamp diodes at the inputs, connecting a receiver at the end of the line changes the waveforms as in figure 5.18. This is a correct Incident Wave Switching (IWS) working condition.


Figure 5.18 Line with clamp diodes at the far end driven by a 74AC device.


12 SI Analysis Strategy Signal Integrity (SI) analysis concentrates on the analog analysis of the switching behavior of fast digital signals. This analysis has become common over the past few years because more system designs are experiencing the ringing, crosstalk and ground bounce problems associated with high-speed signal switching. By using signal integrity analysis to predict and correct SI issues up-front in the design process, the chance of first pass success is greatly increased. The earliest PCB-level SI tools were designed to be run after placement and routing were complete, but before the design was fabricated. SI analysis identified signals with high-speed problems, and those nets were then rerouted to eliminate the problems found. This technique was really only effective with boards with a small number of highspeed nets, and enough free space on the board to accommodate rerouting signals where problems were predicted by analysis. The original “post-route” methodology evolved to accommodate routing only critical nets first, then performing SI analysis on the partially routed board to determine if the performance of those nets was satisfactory. Once the critical nets performed acceptably, the rest of the board could be routed and then post-route SI analysis run as usual. These methodologies were adequate for PCBs with small numbers of critical nets, but are still not adequate for today’s more demanding system designs. Modern systems are dominated by buses with speeds of 50 MT/s and up, having hundreds of critical nets. When a system becomes this heavily populated with high-speed nets, the traditional approach of “route-analyze-fix” becomes impossible. For these designs, a more systematic method for defining SI requirements and ensuring their compliance is required. 12.1.1 A modern high-speed design methodology must involve the at least the following:

1. SI analysis (simulation) software 2. Defined requirements for high-speed signal behavior (e.g. flight time, overshoot) 3. Physical design (placement and routing) tools

12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES Given that SI issues must be addressed early in the system design cycle, there are two fundamental strategies that can be employed:

1. Define each signal’s SI requirements (e.g. flight time, overshoot) and then use these requirements to assess the quality of the placement and routing processes

2. Using each signal’s SI requirements, derive a placement and routing strategy for each group of signals, and then use that strategy to drive the placement and routing processes.

Although the two strategies appear similar at first, they are really quite different. The first strategy is just an extension of the old route-analyze-fix approach. Defining the electrical requirements up-front makes it possible to run simulation automatically after routing and determine if a net needs to be rerouted — allowing the router to continue iterating until the predicted net performance is acceptable. Once the performance for a given net is predicted as acceptable, the net is “locked down” and further edits to that net are disabled.

The primary problem with this approach is that locking down high-speed nets will block routing channels, making the rest of the board harder to complete, and possibly requiring extra layers in the board to complete the design. Any edits to a high-speed net require that SI analysis be rerun to ensure the SI performance has not been affected


— a potentially time-consuming process. Since each high-speed net is routed independently (and probably, differently) SI analysis must be rerun often as the high-speed nets in the design are updated. The second design strategy involves performing considerable SI analysis up-front to “characterize” different placement and routing strategies to define a robust placement and routing strategy. Once the strategy (called a “solution space”) has been defined, any placement and routing solution that remains within the stated guidelines can be expected to have acceptable SI performance, because the design’s range of operating conditions have already been exhaustively characterized.

The process of characterizing a placement and routing strategy is called solution space analysis. This analysis takes a potential routing strategy and then analyzes it under all the possible combinations of design, manufacturing and environmental conditions that can occur. If the design performs acceptably under these conditions, it can be considered a “robust” solution. 12.2.1 There are two fundamental types of conditions that need to be considered for solution

space analysis: o Real-world, or manufacturing/environmental conditions o Design variances

Real world conditions are those elements that vary from system to system whether the designer wants them to vary or not. These variances are the result of normal manufacturing variances and differences in operating conditions. As an example, a PC specified for 600 MHz operation is expected to perform with any 600 MHz processor that is plugged (thus, it must work with “fast” and “slow” 600 MHz devices). Similarly, the computer will probably be expected to function with silicon temperatures from about 50 F to 150 F — even though the silicon’s performance degrades as the system warms up. If the traces on the board are impedance-controlled, the system will still be expected to vary if trace impedance varies by +/- 10%, which is typical for impedance controlled designs.

Figure 1. Solution Space Concept

“Design variances” are the allowable variances in layout that will allow the system to work properly, given the variances in manufacturing and environmental conditions. Design variances are therefore design rules that are ultimately passed to the layout designer. For example, design rules might be specified as a pin schedule and a set of allowable min/max values for different segment lengths. As long as the layout conforms to the specified design rules, the pre-layout characterization ensures the design will run “at-speed” reliably.


This exhaustive pre-layout analysis of manufacturing & design variances is the same process performed by semiconductor vendors that publish “routing guidelines” for designs based on their components. Semiconductor vendors commonly analyze millions of conditions of combinations (“cases”) to ensure that their design rules are robust enough to be followed without the need for detailed SI analysis. Vendors who have historically performed these analyses have done so using complex combinations of in-house and commercial tools. This level of automation is now available to designers in commercial tools. 12.3 SOLUTION SPACE ANALYSIS The steps involved in performing solution space analysis are:

1. Define an initial topology (placement/routing strategy) for a class of high-speed nets 2. Define the different manufacturing tolerances to be analyzed, and their min/max values 3. Define the starting point for the design variances to be analyzed 4. Set up and run a number of simulation cases 5. Examine the simulation results, identify which cases “failed” and why 6. Adapt the topology and design rules as appropriate 7. Repeat steps 4-6 until the topology “converges” on a set of values that “pass” for all cases analyzed 8. Derive design rules for the target CAD system 9. Use the resulting rules to drive the placement/routing processes

12.3.1 STEP 1 — DEFINING THE INITIAL TOPOLOGY Solution space analysis starts by defining pin scheduling, termination (if any) and nominal circuit parameters for a representative high-speed net. If the net is part of a high-speed bus, then all the bits of the bus will typically have the same electrical/physical constraints, such that finding a routing solution for one bit of the bus constitutes finding a solution for the whole bus. If there are any pre-existing constraints for device placement, they should be taken into account at this stage. For example, if the processor cannot be less than 3” away from its corresponding chipset, it makes no sense to explore potential routing strategies with processor — chipset connections less than 3” in length. By taking known placement constraints into account up front, electrically valid (but physically invalid) solutions can be eliminated early. 12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES

The next step is to determine which manufacturing tolerances will have a significant effect on the behavior of the circuit. For instance, the typical +/- 10% variance in characteristic impedance of an impedance-controlled board may have a substantial effect on SI, while the +/- 1% variation in the impedance of a precision terminator may not. Because solution space analysis looks at all combinations of variables, it makes sense to analyze only those variances that are “significant,” in which “significant” is a design–specific factor. Sensitivity analysis can be performed at this stage to help prioritize the effect of the different manufacturing variances on circuit behavior. This helps identify which variables can be excluded, or left until a final, detailed validation is to be performed. Other optimizations can also help reduce simulation run time and improve accuracy –for example, if multiple segments of the same net are routed on the same signal layer, the impedance of the different segments will “track” (scale together). Modeling this tracking behavior has the benefit of reducing the number of different cases that need to be analyzed, and eliminating unnecessary pessimism in the results. Once the variables to be analyzed and their values are determined, the min/max data is entered as part of the circuit model.


12.3.3 STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES

Recall that the design variances will ultimately become the “design rules” used for PCB layout. These rules can be specified as physical rules (net length, spacing), as well as electrical rules (segment delay, overshoot, crosstalk) – or as a combination of both. Once determined, the different design variables and their min/max values are entered as part of the circuit model.

Some design rules may involve a relationship between different parts of the net. For instance, if two net segments are required to always total to a certain length, the delay of one length should be expressed as a function of the length of the other segment. This is a similar form of optimization to the one discussed in step 2, in that this reduces the simulation run time and improves the accura cy of the results. 12.3.4 STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES Once the circuit and its variables/relationships are set up, the process of defining all the different cases (combinations of variables) and analyzing them should be fairly automatic. This will be dependent on the CAD software user for analysis. Traditional solution space analysis processes have relied on collections of commercial tools and custom “scripts” to perform this process. In the Cadence 13.6 release, Signal Explorer Expert performs this process automatically. The number of cases to be analyzed grows rapidly as additional variables are introduced, and can rapidly expand to require millions of simulation runs. To keep run times down and simulations practical, some method of randomly running “subsets” of the full simulation job is required. This serves two purposes:

1. It keeps the number of simulation runs manageable for large, multi-variable runs. 2. It allows small subsets of a large analysis job to be run quickly to identify problems, saving the large runs for later

after the topology has converged. 12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND

WHY Solution space analyses are typically run as batch jobs that take anywhere from 5 minutes to many hours. They return simulation results for each case analyzed — usually in terms of electrical parameters like calculated flight time, overshoot, etc. The simulation results are compared against a design requirement to determine which cases passed and which failed. For instance, the timing budget might show that the flight time for a high-speed net must be greater than 300pS, and less than 3.2nS, while electrical constraints might require that overshoot be limited to less than 500mV.


Figure 2. Example of multi-case analysis and results display Sorting and filtering the simulation results makes it easy to identify which cases failed, and which combinations of conditions they represent. 12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE Once the passing/failing cases have been identified, the electrical designer examines the results and determines how to correct the topology. Sorting, filtering and plotting the data may make it easier to spot the “trends” that determine electrical success or failure. The designer may also want to isolate a specific case and rerun the detailed simulation to view the simulation waveforms to aid in debugging. Based on the simulation data, the topology being designed and an understanding of the high-speed phenomena affecting the circuit, the designer makes an adjustment to the topology and reruns the process. 12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES

THAT PASS FOR ALL CASES ANALYZED The solution space process is iterative, thus, the layout-analyze-fix loop has been moved all the way forward in the design cycle. This process continues until the topology converges into a set of design variances that allow the design to function correctly under all combinations of real-world conditions. Keep in mind that not all topologies will converge. Failure to converge may indicate that a placement/routing strategy is simply not viable, and that different placement/routing/termination rules should be investigated. 12.3.8 STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM After a solution space analysis is defined, the electrical designer determines the applicable design rules for layout. The “real world” variances used in solution space analysis are not passed to layout, because the analysis accounted for the actual variances in the manufactured design (e.g. trace impedance) even when the designer tried to keep the value fixed. The design rules passed to layout are determined by the design variances (e.g. min/max segment length) used in solution space analysis.


Figure 3. Example of circuit topology and associated rules 12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE

THE PLACEMENT/ROUTING PROCESSES This step has traditionally been a large “disconnect” in high-speed PCB design, because the design rules are only passed verbally or on paper, but not as a part of the fundamental PCB database itself

How the design rules can be passed to layout will be highly CAD system dependent. Ideally, all the rules for a given set of nets can be collected into a generic “template” that defines the routing strategy for the entire group of nets. Pin scheduling, min/max segment lengths (either electrical or physical), length matching restrictions and any other electrical/physical requirements are encoded a s part of the template. The template is then imprinted against a group of nets in the PCB database, imposing the associated design rules on each net in the group. This template strategy proves especially useful for managing large buses, in that a single template can be used to quickly specify all the design rules across the entire bus.

If the design rules can be expressed as rules supported by the CAD tool, then the native design-rule-check (DRC) capabilities of the native CAD system can be used to ensure the physical design is compliant with the defined design rules. This represents a considerable — though not necessarily obvious — improvement over the traditional technique of running post-layout SI analysis to uncover high-speed signal problems. For example, if the design rule for a given segment specifies an electrical length of not more than 500 pS, and the segment was manually routed to be 750 pS in length, then should be no need to run a full SI analysis to uncover what is really a simple length violation – since the DRC capabilities of almost all CAD tools support simple length checks.

Thus, the native DRC capabilities of the CAD system can be used to pinpoint basic design rule violations so they can be quickly resolved. In an ideal situation, a rules-based autorouter would simply route the design to specifications.

In practice however, design is performed as a combination of auto/cleanup routing and interactive routing. DRCs are created early in the process and cleaned up as the design progresses. DRCs offer the quickest and most efficient way to highlight and resolve problems. By leveraging the CAD tool’s DRC system, most errors are found early, leaving only the more difficult (and unexpected) design issues for SI analysis.


This strategy of using solution space analysis up front to define rules and then driving them into the layout system opens up possibilities for new design tools. For example, a spreadsheet display can be used to show the different constraints contained in the database, and provide a real-time display of how the design compares against those constraints as the design is placed and routed. During placement, the spreadsheet can provide feedback of the different tradeoffs involved in component placement as each component is moved.

Figure 4. Spreadsheet analysis of design constraints based on placement In an ideal world, design rules would be defined completely before placement and routing began. In the real world, design rules are usually not completely defined before physical design begins, and almost always change as the design and routing process progresses. If the CAD system allows new design rule templates to be applied against the existing design without disturbing the placement/routing, CAD designers can quickly assess the impact of changes in design rules against existing work, identifying which signals will need to be rerouted, and the degree to which those nets violate the updated design rules.

An additional advantage of this technique is that SI analysis need not be rerun every time the routing of a critical net is updated. Because the design rules were determined from up-front comprehensive analysis of worst-case conditions, any net routing that conforms to the design rules in the database can be expected to function correctly. 12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS Post-layout SI analysis still has its place in a solution space design flow, because unexpected problems can still occur. The emphasis shifts considerably, because the post-layout analysis is intended to serve as a “signoff” analysis, instead of being used as the primary vehicle for identifying SI issues. The problems uncovered during post-layout analysis, if any, tend to be isolated and correctable on a case-by-case basis. 12.4 CONCLUSION This article has reviewed the traditional techniques for identifying SI problems in high-speed designs, and outlined the “solution space” approach for defining and driving high-speed placement and routing strategies. This technique uses comprehensive up-front SI analysis to define robust


design rules, and then leverages the CAD system’s native design rule checks to ensure that the design is placed and routed according to the design rules. While the solution space approach has been used by semiconductor vendors for years, it has re lied heavily on custom methodologies and scripting designed around specific design scenarios. The capability to provide this type of analysis to the average user has only recently become available in commercial SI tools. high-speed design issues invariably require changing the PCB design process. Because the issues of signal timing, signal integrity, power delivery/decoupling and EMI are interrelated, the PCB electrical and physical design processes must become interrelated as well. The solution space approach takes advantage of the different groups of engineers that exist in most organizations and their respective strengths. Up-front and post-route SI analysis can be performed by electrical designers, who derive electrical design rules based on SI analysis and an understanding of the preexisting placement requirements of a design. By imprinting the resulting design rules into the PCB database and leveraging the CAD tool’s DRC capabilities, layout designers have the best chance of routing the design to the ru les, and can choose from a selection of interactive and automatic routing strategies.


13 Glossary Word Definition

AC Coupling

Method of interfacing drivers and receivers through a series capacitor. Often used when the differential swing between drivers and receivers is compatible, but common mode voltages of driver and receiver are not. Requires that a minimum data frequency be established based on the RC time constant, necessitating a run length limit.

Attenuation Reduction in amplitude of a signal.

BER See Bit Error Rate

BERT See Bit Error Rate Test or Bit Error Rate Tester

Bit Error Rate

A measurement of the number of errors detected at a receiver in a given length of time, sometimes specified as a percentage of received bits; sometimes specified in exponential form (10E-8 to indicate 1 bit error in 10E-8 bits).

Bit Error Rate Test or Bit Error Rate Tester

An instrument used to determine the Bit Error Rate (BER) of a device or system under test. It is generally made up of a test pattern generator, receiver, and analyzer.

BIST Built-In Self Test

CDR See Clock Data Recovery.

Channel Bonding Feature of multi-channel high-speed transceivers. Allows multiple channels to be sued together, offering a greater aggregate bandwidth.

Chirp

Bit sequence, which is transmitted by a high-speed transceiver when it is not in use. The chirp is usually a repeating pattern of IDLE characters. The purpose of the chirp is to keep clock recovery circuits aligned and active while the link is not transmitting data.

Clock/Data Recovery Feature of most high-speed serial transceivers. At the receiver, a clock is generated based on the timing of data transitions. In this way, a clock signal is derived from the data.

CML See Current Mode Logic.

Comma K-character

Common Mode The DC component of a signal. In differential channels, it is the average voltage of the differential pair.

Crosstalk Undesirable signal coupling from noisy aggressor nets to victim nets. May be eliminated by increasing the spacing between the nets or reducing signal amplitude of the aggressor net.

Current Mode Logic A differential I/O standard used in high-speed serial channels. Voltage swing is typically from 450 mV to 1200 mV.

DC Balanced A channel is said to be DC Balanced if it has an equal number of 1’s and 0’s transmitted across it. Encoding schemes like 8B10B are designed to ensure this.

DC Coupling Method of interfacing drivers and receivers without the use of series capacitors. A direct connection (through PCB trace) from driver to receiver.

Deterministic Jitter The component of jitter attributable to the data pattern in the channel. Different digital patterns have different spectral contents. These differing spectral contents give rise to varying amounts of signal jitter.

Differential Signaling A signaling scheme, which uses two complementary signals to transmit data.


Differential signaling offers faster data rates at reduced signal swing, with higher signal to noise ratio.

Dispersion

"Smearing" of a signal or waveform as a result of transmission through a non-ideal transmission line. Through a non-ideal medium, signals travel at different velocities according to their frequency. Dispersion of the signal is the result. All cables and PCB transmission lines are non-ideal.

DSL Digital Subscriber Line

Equalization Amplification or attenuation of certain frequency components of a signal. Used to counteract the effects of a non-ideal transmission medium.

Eye Diagram

An eye diagram of a signal overlays the signal’s waveform over many cycles. Each cycle’s waveform is aligned to a common timing reference, typically a clock. An eye diagram provides a visual indication of the voltage and timing uncertainty associated with the signal. It can be generated by synchronizing an oscilloscope to a timing reference.

The vertical thickness of the line bunches in an eye diagram indicate the magnitude of AC voltage noise, whereas the horizontal thickness of the bunches where they cross over is an indication of the AC timing noise or jitter. Fixed DC voltage and timing offsets are indicated by the position of the eye on the screen.

Eye Mask

The size of the eye opening in the center of an eye diagram indicates the amount of voltage and timing margin available to sample this signal. Thus, for a particular electrical interface, a fixed reticule or window could be placed over the eye diagram showing how the actual signal compares to minimum criteria window, know as the eye mask. If a margin rectangle with width equal to the required timing margin and height equal to the required voltage margin fits into the opening, then the signal has adequate margins. Voltage margin can often be traded of for timing margin.

Falltime The time it takes for a waveform to transition from the high logic state to the low logic state. Falltime is usually measured from 90% of the total signal swing to 10% of the signal swing.

Idle Pattern

A data sequence transmitted by a high-speed transceiver as a placeholder or for link maintenance. The particular sequence of an IDLE pattern is determined by the communication protocol, and is usually a control character like K28.5.

Impedance (Characteristic Impedance)

Electrical characteristic of a transmission line, derived from the capacitance and inductance per unit length.

Inter-Symbol Interference A form of data corruption or noise due to the effect that data has on data-dependent channel characteristics.

ISI See Inter-Symbol Interference.

Jitter

The jitter of a periodic signal is the delay between the expected transition of the signal and the actual transition. Jitter is a zero mean random variable. When worst-case analysis is undertaken the maximum value of this random variable is used.

Jitter Tolerance

Jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input that causes a predefined, acceptable loss at the output. For example jitter applied to the input of an OC-N equipment interface that causes an equivalent 1dB optical power penalty.

Jitter Transfer Jitter transfer is defined as the ratio of jitter on the output of a device to the jitter applied on the input of the device, versus frequency. Jitter transfer is


important in applications where the system is utilized in a loop-timed mode, where the recovered clock is used as the source of the transmit clock.

LAN Local Area Network

LDT Lightning Data Transport

Loopback Path in a high-speed transceiver, which connects the output to the input, on either the PMA or PCS side, for testing purposes.

LVDS Low Voltage Differential Signaling. A differential IO standard commonly used for high-speed, low-swing signals.

MAN Metropolitan Area Network

Multilevel Signaling System where multiple logic levels are utilized instead of just two (high and low). This enables the tranmission of multiple bits in a single waveform.

Overshoot Phenomenon where a signal rises to a level greater than its steady-state voltage before settling to its steady-state voltage.

PCS Physical Coding Sublayer

Peak-to-Peak In the case of peak-to-peak voltage, a measure of a signal's total amplitude. In the case of peak-to-peak jitter, a measure of the extremes of excursion of the bit transition times.

PECL

Positive Emitter-Coupled Logic. A differential IO standard based on the ECL standard, but which operates with a positive supply voltage (ECL uses a negative supply voltage). PECL is used in clocking and high-speed data applications.

PLL Phase-Locked Loop

PMA Physical Media Attachment

PRBS Pseudo-Random Bit Sequence

Pre-Emphasis

Pre emphasis is magnitude boosting of high frequency spectral components before launching the signal (wave) onto the Transmission Line. Transmission Lines embedded in most standard PCB materials (FR4, Rogers 43xx, Nelco and Rogers) suffer varying degrees of dispersion and loss in the 1 gigahertz spectrum. This is mostly due to conductance losses (leakage from the copper trace to any other conducting structure) and Skin Effect. Dispersion is a phenomenon whereby spectral components travel at different velocities. The waveform looks smeared when it arrives at the receiver.

Both of these "characteristics" play into a diminished and poorly received signal. By boosting the high freq. spectral components, the magnitude of these components can be diminished as the wave travels through the Transmission Line, but since it starts out larger than the lower frequency components, the composite signal arrives at the receiver looking the way it was intended.

Pre Emphasis is done by simply increasing the maximum amplitude of the signal for one bit period. If the signal is 1 bit in duration, the amplitude is allowed to rise to a value which is some percentage greater in magnitude. At this point, if the signal is to stay at the same logic state, the driver sends a decreased magnitude signal, or nominal logic


level. Every time a transition occurrs, the greater magnitude level is used. For all times after this that the same level is to be transmitted, the nominal magnitude is used.

Random Jitter Jitter caused by Power Supply noise, temperature variations and crosstalk.

Ringing

Common name for the waveform that is seen when a transmission line ends at a high impedance discontinuity. The signal first overshoots, then dips down below the target value, and continues this with decreasing amplitude until it converges on the target voltage.

Risetime The time it takes for a signal to rise from 10% of its total logic swing to 90% of its total logic swing.

SAN Storage Area Network

SERDES Serializer/Deserializer, a common name for a high-speed transceiver, which performs the parallel-to-serial conversion as well as the serial to parallel conversion.

Single Ended Method of signaling which, unlike differential signaling, only transmits signals over one net.

Skin Effect/Loss Electrical loss in a non-ideal medium due to skin effect. Skin effect is the tendency for high-frequency signal components to travel close to the surface of the medium.

SNR Signal to Noise Ratio

SONET Synchronous Optical Network

Termination

Usually implemented with passive components, termination is used to interface drivers, receivers, and traces that have differing impedance values. Typically, device drivers and receivers do not match the impedance of the PCB trace that connects them. Termination resistors are employed to match the impedances of these components, maximizing signal transmission and reducing noise.

UI See Unit Interval

Unit Interval Unit of time corresponding to one bit period. A unit interval is the time it takes to send one bit.

WAN Wide Area Network

WDM Wavelength Division Multiplexing

PCB Designer’s SI Guide

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