PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... ·...

42
PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U X C O N T R O L ALU CTL INSTRUCTION FETCH INSTR DECODE REG FETCH EXECUTE/ ADDRESS CALC MEMORY ACCESS WRITE BACK A D D A D D A L U

Transcript of PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... ·...

Page 1: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

PC InstructionMemory

4

MUX

Registers

Sign Ext

MUX

Sh L 2

DataMemory

MUX

CONTROL

ALUCTL

INSTRUCTION FETCH

INSTR DECODE REG FETCH

EXECUTE/ADDRESS CALC

MEMORY ACCESS

WRITEBACK

ADD A

DD

ALU

Page 2: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Caches

Slides courtesy of Chris Nevison

With modifications by

Alyce Brady

and

Nathan Sprague

Page 3: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

PC InstructionMemory

4

MUX

Registers

Sign Ext

MUX

Sh L 2

DataMemory

MUX

CONTROL

ALUCTL

INSTRUCTION FETCH

INSTR DECODE REG FETCH

EXECUTE/ADDRESS CALC

MEMORY ACCESS

WRITEBACK

ADD A

DD

ALU

Page 4: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Memory◆ Main Memory (DRAM) much slower than

processors◆ Gap has widened over the past 20+ years,

continues to widen◆ Memory comes in different technologies:

fastest is also the most expensive

FastestMost expensiveSRAM: .5-5 ns$4000-$10000/GB

SlowestLeast expensiveMag. Disk: 5-20 million ns$0.50-$2.00/GB

Page 5: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Using Memory

◆ Temporal locality - likely to reuse data soon– WHY?

◆ Spatial locality - likely to access data close by – WHY?

Page 6: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Using Memory

◆ Temporal locality - likely to reuse data soon (loops)

◆ Spatial locality - likely to access data close by (sequential nature of program instructions, data access)

◆ Use small amounts of expensive memory, larger amounts of less expensive memory

◆ Memory hierarchy used to hide memory access latency

Page 7: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Memory Hierarchy

First LevelCache

Second LevelCache

MainMemory

Secondary Memory (Disk)

Page 8: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Using the Memory Hierarchy◆ Check if data is in fast memory (hit); if not

(miss), fetch a block from slower memory– “Block” may be a single word or several words

◆ Fetch time is miss penalty ◆ Hit rate is fraction of memory accesses that are

hits; miss rate = 1 - hit rate◆ If locality is high, hit rate gets closer to 1◆ Effect: memory is almost as fast as fastest level,

as big as biggest (slowest) memory

Page 9: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Cache Issues◆ How is cache organized and addressed?◆ When cache is written to, how is memory image

updated?◆ When cache is full and new items need to be put

in the cache -- what is removed and replaced?

Page 10: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Direct Mapped:

Any given memory address can only be found in one cache address (although many memory addresses will map to the same cache address)

Page 11: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Cache Example (Direct Mapped)

◆ 256 Byte Cache (64 4-byte words)◆ Each Cache “line” or “block” holds one word (4

bytes)◆ Byte in cache is addressed by lowest two bits of

address◆ Cache line is addressed by next six bits in address◆ Each Cache line has a “tag” matching the high 24

bits of the memory address

Page 12: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Addresstag 00 01 10 11line address

000000000001

000110000111

000010000011

000100000101

001110001111

001100001101

001010001011

001000001001

111110111111

Page 13: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Address

Address 1100 0000 1010 0000 0000 0110 0010 1000

tag 00 01 10 11line address000000000001

000110000111

000010000011

000100000101

001110001111

001100001101

001010001011

001000001001

111110111111

Page 14: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Address

Address 1100 0000 1010 0000 0000 0110 0010 1000

1100 0000 1010 0000 0000 0110

tag 00 01 10 11line address000000000001

000110000111

000010000011

000100000101

001110001111

001100001101

001010001011

001000001001

111110111111

Page 15: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Cache Access1. Find Cache line address (bits 2 - 7)

2. Compare tag to high 24 bits

– if matched, cache hit» find Byte address, read or write item

– if not matched, cache miss, go to memory» for a read: retrieve item and write to cache, then use» for a write: write to memory (or to cache, see below)

3. Direct mapped cache -- every address can only go to one cache line!

4. What happens when cache is written to?

Page 16: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Write Policy

◆ Write Through– Write to memory and to cache– Time to write to memory could delay instruction

» write buffer can hide this latency◆ Write Back (also called Copy Back)

– Write only to cache» mark cache line as “dirty”, using an additional bit

– When cache line is replaced, if dirty, then write back to memory

Page 17: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Addresstag 00 01 10 11

Lineaddress

000001

110111

010011

100101

valid

Desired Address88  = ...00010 110 00104 = ...00011 010 0088  = ...00010 110 00104 = ...00011 010 0064  = ...00010 000 0012  = ...00000 011 0064  = ...00010 000 0072  = ...00010 010 00

N N

N N

N N N N

Page 18: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Addresstag 00 01 10 11

Lineaddress

000001

110111

010011

100101

valid N N

Y N

N N

N N

0000 0000 0000 0000 0000 0010

Desired Address88  = ...00010 110 00  MISS ­ fetch104 = ...00011 010 0088  = ...00010 110 00104 = ...00011 010 0064  = ...00010 000 0012  = ...00000 011 0064  = ...00010 000 0072  = ...00010 010 00

Page 19: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Addresstag 00 01 10 11

Lineaddress

000001

110111

010011

100101

valid N N

Y N

Y N

N N

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0011

Desired Address88  = ...00010 110 00  MISS ­ fetch104 = ...00011 010 00  MISS ­ fetch88  = ...00010 110 00104 = ...00011 010 0064  = ...00010 000 0012  = ...00000 011 0064  = ...00010 000 0072  = ...00010 010 00

Page 20: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Addresstag 00 01 10 11

Lineaddress

000001

110111

010011

100101

valid N N

Y N

Y N

N N

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0011

Desired Address88  = ...00010 110 00  MISS ­ fetch104 = ...00011 010 00  MISS ­ fetch88  = ...00010 110 00  HIT!104 = ...00011 010 0064  = ...00010 000 0012  = ...00000 011 0064  = ...00010 000 0072  = ...00010 010 00

Page 21: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Addresstag 00 01 10 11

Lineaddress

000001

110111

010011

100101

valid N N

Y N

Y N

N N

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0011

Desired Address88  = ...00010 110 00  MISS ­ fetch104 = ...00011 010 00  MISS ­ fetch88  = ...00010 110 00  HIT!104 = ...00011 010 00  HIT!64  = ...00010 000 0012  = ...00000 011 0064  = ...00010 000 0072  = ...00010 010 00

Page 22: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Addresstag 00 01 10 11

Lineaddress

000001

110111

010011

100101

valid Y N

Y N

Y N

N N

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0011

Desired Address88  = ...00010 110 00  MISS ­ fetch104 = ...00011 010 00  MISS ­ fetch88  = ...00010 110 00  HIT!104 = ...00011 010 00  HIT!64  = ...00010 000 00  MISS ­ fetch12  = ...00000 011 0064  = ...00010 000 0072  = ...00010 010 00

Page 23: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Addresstag 00 01 10 11

Lineaddress

000001

110111

010011

100101

valid Y N

Y N

Y Y

N N

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0000

0000 0000 0000 0000 0000 0011

Desired Address88  = ...00010 110 00  MISS ­ fetch104 = ...00011 010 00  MISS ­ fetch88  = ...00010 110 00  HIT!104 = ...00011 010 00  HIT!64  = ...00010 000 00  MISS ­ fetch12  = ...00000 011 00  MISS – fetch64  = ...00010 000 0072  = ...00010 010 00

Page 24: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Addresstag 00 01 10 11

Lineaddress

000001

110111

010011

100101

valid Y N

Y N

Y Y

N N

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0100

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0000

Desired Address88  = ...00010 110 00  MISS ­ fetch104 = ...00011 010 00  MISS ­ fetch88  = ...00010 110 00  HIT!104 = ...00011 010 00  HIT!64  = ...00010 000 00  MISS ­ fetch12  = ...00000 011 00  MISS – fetch64  = ...00010 000 00  HIT!72  = ...00010 010 00

Page 25: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Byte Addresstag 00 01 10 11

Lineaddress

000001

110111

010011

100101

valid Y N

Y N

Y Y

N N

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0010

0000 0000 0000 0000 0000 0000

Desired Address88  = ...00010 110 00  MISS ­ fetch104 = ...00011 010 00  MISS ­ fetch88  = ...00010 110 00  HIT!104 = ...00011 010 00  HIT!64  = ...00010 000 00  MISS ­ fetch12  = ...00000 011 00  MISS – fetch64  = ...00010 000 00  HIT!72  = ...00010 010 00  MISS – fetch (wrong tag)

Page 26: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Accelerating Memory Access

◆ Wider bus◆ Wider memory access

Page 27: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Accelerating Memory Access

◆ How can Cache take advantage of faster memory access?

◆ Store more than one word at a time on each “line” in the cache– Any cache miss brings the whole line containing the

item into the cache◆ Takes advantage of spatial locality

– next item needed is likely to be at the next address

Page 28: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Cache with multi-wordline

◆ 256 Byte cache -- 64 4-byte words◆ Each block (line) contains four words (16 bytes)

– 2 bits to address byte in word– 2 bits to address word in line

◆ Cache contains sixteen four-word blocks– 4 bits to address cache block (line)

◆ Each cache line has tag field for upper 24 bits of address

Page 29: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Word Address

tag

00 01 10 11

line address 0000 0001

0110 0111

0010 0011

0100 0101

1110 1111

1100 1101

1010 1011

1000 1001

Byte Address00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

Address 1100 0000 1010 0000 0000 0110 0010 1000

Page 30: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Word Address

tag

00 01 10 11line address

0000 0001

0110 0111

0010 0011

0100 0101

1110 1111

1100 1101

1010 1011

1000 1001

Byte Address00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

Address 1100 0000 1010 0000 0000 0110 0010 10 00

MUXHitTo Control Data

Page 31: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

PC InstructionCache

4

MUX

Registers

Sign Ext

MUX

Sh L 2

DataCache

MUX

CONTROL

ALUCTL

INSTRUCTION FETCH

INSTR DECODE REG FETCH

EXECUTE/ADDRESS CALC

MEMORY ACCESS

WRITEBACK

ASDUDB A

DD

ALU

MemAddr

MemData

Hit

MemAddr

MemData

Hit

Page 32: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Instruction Cache Hit / Miss

◆ Hit or Miss: – Instruction is fetched from Cache and placed

in Pipeline buffer register– PC is latched into Memory Address Register

◆ Hit: – Control sees hit, execution continues– Mem Addr unused

Page 33: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Instruction Cache Hit / Miss◆ Miss

– Control sees miss, execution stalls– PC reset to PC - 4– Values fetched from registers are unused– Memory Read cycle started, using Mem Addr

◆ Memory Read completes– Value stored in cache, new tag written– Instruction execution restarts, cache hit

Page 34: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Speeding Up Cache◆ execution time = (execution cycles + stall cycles) × cycle time

stall cycles = # of instructions × miss ratio × miss penalty◆ We can improve performance by

– Reducing miss rate

– Reducing miss penalty

◆ More flexible placement of blocks– Miss rate

◆ Caching the Cache– Miss penalty

Page 35: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Associative Cache◆ Fully Associative

– Blocks can be stored in any cache line.– All tags must be checked on every access.

◆ Set Associative– Two or more (power of 2) lines for each address– More than one item with same cache line address can

be in cache– Tags for all lines in set must be checked, any match

means a hit, if none match, a miss

Page 36: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

line address

Two-way set associative cache

Word Address

tag

00 01 10 11

000

Byte Address00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

100

101

110

111

010

001

011

Page 37: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Hit

Address 1100 0000 1010 0000 0000 01100 010 10 00

Data

Word Address

tag

00 01 10 11

000

Byte Address00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

100

101

110

111

010

001

011

Valid

MUX

Page 38: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Replacement Policy◆ Necessary to select a line to replace when using

associative caches◆ Least Recently Used (LRU) is one possibility

Page 39: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Multi-level Cache◆ Put two (or more) levels of cache between CPU and

memory◆ Focus of top level cache is on keeping hit time low◆ Focus of lower level cache is on keeping miss penalty

low for top level cache - low miss rate is more important than hit time.

Page 40: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Cache Summary - types◆ Direct Mapped

– Each line in cache takes one address– Line size may accommodate several words

◆ Set Associative– Sets of lines serve the same address– Needs replacement policy for which line to

purge when set is full– More flexible, but more complex

Page 41: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Cache Summary◆ Cache Hit

– Item is found in the cache– CPU continues at full speed– Need to verify valid and tag match

◆ Cache Miss– Item must be retrieved from memory– Whole Cache line is retrieved– CPU stalls for memory access

Page 42: PC Instruction Registers Memory A L M U Data U X M ALU INSTRUCTION INSTR DECODE ... · 2018-05-29 · PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U

Cache Summary

◆ Write Policies– Write Through (always write to memory)– Write Back (uses “dirty” bit)

◆ Associative Cache Replacement Policy– LRU (Least Recently Used)– Random


A U R U M - 147.182.164.38

A U R U M - 147.182.164.38

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MWD Vibration Memory Module - APS Technology...SureShot Vibration Memory Module (VMM ) Headquarters u Wallingford u USA7 Laser Lane, Wallingford, CT 06492 USA Phone: 860.613.4450 u

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