Patil Hareesh Bhargava PavanMobile: +91-9980512890, E-mail: patil.phb@gmail.com

LinkedIn: http://in.linkedin.com/pub/patil-pavan/62/527/651/Career Objective:

To become a key technical resource for an organization , where I am able to explore my full potential, add to my learning curve, as well as contribute effectively and efficiently to achieve organizational goals.

Experience: Total work experience of 2.5 year till date in the field of VLSI. 30th Oct 2014 till date working as a “Project Fellow” in VLSI with CSIR-National

Aerospace Laboratories, Bangalore. Experience in development of FPGA IP core prototype process. Knowledge on PCI’e. Gained knowledge on DO-254. Gained hands on experience on Requirement Tracer from Mentor Graphics. April 2014 to Oct 2014 Worked as an “Engineer Support (Post Silicon Validation)” in

VLSI with Cypress Semiconductors India Pvt. LTD., Bangalore. Experienced in VHDL, Xilinx FPGA programming. Proficient in RTL design, simulation and synthesis using Xilinx ISE, XST tools. Worked on development project and providing technical assist for project. Experience in semiconductor testing. Experience in Lab VIEW based semiconductor testing.

Educational Qualification: Bachelor of Technology in Electronics and Communication Engineering at JNTU

University Anantapur in 2013 with 75%. Board of Intermediate (M.P.C) in 2009 with 84%. Board of Secondary Education (SSC) in 2007 with 78%.

Certification/Course: Ongoing Xilinx corporate training.

Technical Skills:

Languages : C | Lab VIEW HDL’s : VHDL | Verilog VLSI programming Tools:

Xilinx ISE / VIVADO | Questa simHardware

Xilinx FPGA evaluation boards (SP605/ ML605/ ZC706 / KC705/Zed Board) NI PXI | NI HSDIO | NI DAQ

Aerospace Protocol: ARINC 664Operating Systems

Windows | Linux UbuntuDO-254 Tools:

HDL Designer | Req Trace

Area of interest: RTL design.

FPGA Design. Development of new IP’s.

Project(s) and Roles at CSIR-NAL:

Avionics Full Duplex Switched Ethernet Protocol (ARINC 664)Description: Development of AFDX receiver protocol IP block in VHDL. Creating FSM’s for internal blocks of the AFDX receiver/transmitter. 4-bit CRC generation. Creating MDIO management IP block in VHDL.Role:

FPGA IP design and development. Understanding the specifications and features of the protocol. Writing VHDL code for development of AFDX IP. Design and development of MDIO. Development of Finite State Machines in VHDL programming. RTL coding in VHDL also creating test bench for the corresponding block. Simulation and Debugging of test cases using Xilinx ISim simulator. Creating design documents and memos. Debug with Chip Scope analyzer. Board level debug on different Xilinx FPGA families. System integration. Development of system level test benches. Creating ILA for on chip simulation using Chip Scope Analyzer.

Integration of Tri Mode Ethernet MAC (TEMAC)Description: Customization of Xilinx TEMAC IP core for generation of UDP packets.Role:

Understanding the TEMAC IP core features. RTL code for generation of UDP frames. Simulation and Debug of the TEMAC IP core.

Project(s) and Roles at Cypress Semiconductors India Pvt. Ltd.

Rainer: 16 bit- Mbit Nonvolatile Static Random Access Memory (NvSRAM)Description: NvSRAM is a type of non-volatile random access memory. It is similar in operation to static random access memory. But NVSRAM provides the asynchronous parallel and ONFI 1.0 interface options. Access time is as low as 20 ns. Infinite endurance. No batteries to require store data on power loss.Roles:

Interface with production test team to support correlation and yield enhancements. Support test engineers with prototype hardware including cable and harness assembly,

wiring and electrical and mechanical assembly, test and maintenance. Working closely with IC Design team to generate characterization test specifications. Hands-on test and characterization of blocks within Envelope Tracking IC’s. Generate reports analyzing, communicating and documenting test data relevant to the

product and component approval process. Responsible for transfer of Engineering and Production test packages (48TSOP,

44TSOP, 165BGA). Worked on Lab VIEW programming for automatic test with temptronics, source

meters etc.

Worked on 48 TSOP and 165BGA packages to test the memory devices and micro probing on the same packages.

IBIS model silicon correlation and char. Developed Lab VIEW program to test the memory devices and generating data for the

same. Worked on FPGA module for debug the program and test the memory devices on

different packages.

Internship at CYBERNETICS Services Pvt. Ltd. (April 2012- July 2012)Guide: Mr. P. Nagaraju, Sr. R&D

Platform-Windows | Tools& Languages: Lab VIEW

Dredger monitoring system Development of dredger monitoring system for a dredging machine to identify how

much depth we have covered so far.Hobbies: Reading books, playing chess, cricket, net surfing, making new friends.Personal Details:Date of Birth : 3rd, Nov 1991.Father : P.S.RamamurthySex : MaleAddress : #362, 1st floor, 2nd cross, 17th main road, Muneswara Block,

Bangalore- 560026Languages known : English, Kannada, Telugu, Hindi.

Declaration

I hereby declare that the above mentioned details are true to the best of my knowledge and belief.Date:Place: Bangalore Patil Hareesh Bhargava Pavan