Pass Transistors and Transmission Gates

Pass Transistors and Transmission Gates

João Canas Ferreira

University of PortoFaculty of Engineering

2015-04-07

Topics

1 Pass transistors

2 Transmission gates

João Canas Ferreira (FEUP) Pass Transistors and Transmission Gates 2015-04-07 2 / 20

Logic gates with pass transistorsà NMOS transistors can be used as voltage-controlled switches

Switch networkIn

puts A

B

B

B

F = AB

Source: [Rabaey03]

à Ensure that there is no contention on external nodesà Level of output signal must be “restored”à Characteristics:

I Fewer transistorsI No static power consumption

I . . . but pay attention to the output buffer


Output voltage levelà The voltage level for a “1” is degraded by a network of NMOS passtransistors.

VDD

In

x Out

0 0.5 1 1.5 20.0

1.0

2.0

3.0

Time [ns]

Vo

ltage

[V]

xOut

In

Source: [Rabaey03]

I VX = VDD − VT

I Output inverter may exhibit static power consumption.I It is useful to change the output inverter’s VM

I NMOS transistor suffers body effect (increased VT) de Vin − VT (linearregion)

I Connecting drains to gates of pass transistors increases the degradationof the output voltage level.


NMOS switch

VB = VDD − VT = VDD − (VT0 + γ(√|2ΦF |+ VSB −

√|2ΦF |) ≈ 1.8 V

A = 2.5 V

B

C = 2.5 V

CL

Source: [Rabaey03]

A = 2.5 V

C = 2.5 V

BM 2

M 1

M n

I VB does not reach 2.5 V, but just 2.5 V-VT.I The next gate exhibits static power consumption.I NMOS transistor is subject to the body effect, increasing the threshold

voltageI The switch resistance grows as VB approaches VA − VT (linear region).


Voltage transfer curvesà The voltage transfer curves of this type of circuits are very different fromthe VTCs of complex dual CMOS gates.

Source: [Rabaey03]


The CPTL logic family

I CPTL = complementary pass transistor logicI Complementary values are always availableI All gates use basic block topologyI One may need to use transistors with VT=0, to avoid the degradation caused by

connecting drains to gates.


Restoring the voltage level

M2

M1

Mn

M r

OutA

B

VDDVDDLevel Restorer

X

Contention in node X during thetransition H→L: discharge via Mn

is opposed by pull-up via Mr.

Source: [Rabaey03]

I Rail-to-rail swingI Level restorer increases the capacitance of node XI This is a ratioed circuit, and so involves solving the problem of finding

the dimension of Mr.


Sizing the level restorer (simulation)

0 100 200 300 400 5000.0

1.0

2.0

W/Lr =1.0/0.25 W/Lr =1.25/0.25

W/Lr =1.50/0.25

W/Lr =1.75/0.25

Vol

tage

[V]

Time [ps]

3.0

Source: [Rabaey03]

I There is an upper limit for the size of the level restorer.I Pull-down may be provided through a chain of several NMOS transistors.

vários transístores NMOS.I Mr increases the rising time and decreases the falling time.I Increased capacitance of node X makes the gate slower.


Using zero-threshold transistors

Source: [Rabaey03]

I Pass transistors with VT = 0 VI Leakage currents can be significant (for infrequent commutation).I Body effect is still present.


Topics

1 Pass transistors

2 Transmission gates


Transmission gate

A B

C

C

A B

C

C

BCL

C = 0 V

A = 2.5 V

C = 2.5 V

Source: [Rabaey03]

à The use of transmission gates has been declining. Why?


Transmission gate resistance

Vout

0 V

2.5 V

2.5 VRn

Rp

0 . 0 1 . 0 2 .00

1 0

2 0

3 0

Vout, V

Res

ista

nce

, oh

ms

Rn

Rp

Rn || Rp

Geq =1

Req≈ kn(VDD − VTN) + kp(VDD − |VTP|)


Transmission gate multiplexer

AM2

M1

B

S

S

S F

VDD

VDD

S S

GND

In1 In2S S


XOR logic gate

A

B

F

B

A

B

BM1

M2

M3/M4

saída Foutput F

I The dual implementation requires 12 transistors.I Analyze cases B=1 and B=0 separately..I The output node (F) always has a low-resistance path to a supply rail.


Delay of transmission gate chains

V1 Vi1

C

2.5 2.5

0 0

Vi Vi+1

CC

2.5

0

Vn1 Vn

CC

2.5

0

In

V1 Vi Vi+1

C

Vn1 Vn

CC

InReqReq Req Req

CC

(a)

(b)

C

Req Req

C C

Req

C C

Req Req

C C

Req

CIn

m

Source: [Rabaey03]


Delay optimizationDelay of RC chain

tp = 0.69n∑

k=0

C Reqk = 0.69 C Reqn(n + 1)

2

Delay of RC chain with intermediate buffersI n: total number of transmission gates

m: number of transmission gates per segment

tp = 0.69⌊

nm

C Reqm(m + 1)

2

⌋+( n

m− 1)

tbuf

= 0.69⌊C Req

n(m + 1)

2

⌋+( n

m− 1)

tbuf

Optimum number of transmission gates per segment

mopt = 1.7

√tbuf

C Req


Exemple: delay of a chain of transmission gates

Source: [Rabaey03]

à 16 transmission gates, 8 kΩ, 3.6 fF: 2.7 psJoão Canas Ferreira (FEUP) Pass Transistors and Transmission Gates 2015-04-07 18 / 20

Example: full adder

A

B

P

Ci

VDDA

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

Ci

Co

S

Ci

P

P

P

P

P

Sum Generation

Carry Generation

SetupSource: [Rabaey03]

I Similar delay for carry and sumsignals

I Uses 24 instead of 28 transistors

S = A ⊕ B ⊕ CS = AB C + ABC + A BC + ABCCo = AB + BC + ACG = AB D = A B P = A ⊕ BCo(G, P) = G + PCS(G, P) = P ⊕ C


References

à Some of the figures come from the book:

Rabaey03 J. M. Rabaey et al, Digital Integrated Circuits, 2nd

edition,Prentice Hall, 2003.http://bwrc.eecs.berkeley.edu/icbook/


http://bwrc.eecs.berkeley.edu/icbook/

Pass Transistors and Transmission Gates

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