Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor...

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Pass Transistor Logic

Transcript of Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor...

Page 1: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Pass Transistor Logic

Page 2: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Agenda

Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated Electronics Static CMOS Logic Circuits Pseudo nMOS Logic Circuits Pass Transistor Logic Circuits Dynamic Logic Circuits Case Studies

Page 3: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Pass Transistor Logic Circuits

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

Page 4: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

nMOS Pass Transistor – Logic ‘1’ Transfer

Page 5: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

nMOS Pass Transistor – Logic ‘0’ Transfer

Page 6: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.
Page 7: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

PASS TRANSISTORS IN SERIES

Page 8: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

PASS TRANSISTOR LOGIC CIRCUITS

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

Page 9: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

TRANSMISSION GATES

NMOS pass transistor passes a strong 0 and a weak 1. PMOS pass transistor passes a strong 1 and a weak 0. Combine the two to make a CMOS pass gate which will

pass a strong 0 and a strong 1.

Page 10: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

TRANSMISSION GATE

Page 11: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

PROBLEMS WITH TRANSMISSION GATES

No isolation between the input and output. Output progressively deteriorates as it passes through

various stages.

However designs get simplified.

Page 12: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

TRANSMISSION GATE - LAYOUT

Page 13: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

PASS TRANSISTOR LOGIC CIRCUITS

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

Page 14: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Multiplexor

Page 15: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Pass Transistor Logic Circuits

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

Page 16: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

XOR gate

Page 17: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

PASS TRANSISTOR LOGIC CIRCUITS

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

Page 18: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

D – Latch

Page 19: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

TIMING ISSUES

Page 20: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

D LATCH

Page 21: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

D - LATCH

Page 22: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

D LATCH – ALTERNATE CIRCUIT TOPOLOGY

Page 23: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

PASS TRANSISTOR LOGIC CIRCUITS

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

Page 24: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Static Flip Flop

0

1

D1

0

Q

ClkClk

Transparent when Clk=0

Transparent when Clk=1

At Clk= 0 1, Q = D. Else Q is held.

Page 25: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

D Flip Flop – Circuit Diagram

Page 26: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

D Flip Flop - Operation

Page 27: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

D Flip Flop - Waveforms

Page 28: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Pass Transistor Logic Circuits nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

Page 29: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Handling Clock Skew

Clk-in Clk

Clk'

Page 30: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Pass Transistor Logic Circuits

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

Page 31: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Pass Transistor Logic Families

Complementary Pass Transistor Logic Family Dual Pass Transistor Logic Family Swing Restored Pass Transistor Logic Family

Page 32: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Problems

Design 4 to 1 multiplexor using transmission-gates. Implement an XOR gate using minimum number of

transistors. Implement a full adder using transmission gates.

Page 33: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Solution - 1

C'0

C0

C1

C'1

Y

A0

A1

A2

A3

Page 34: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

Solution - 2

C'0

C0 C'1

A0

A1

A2

A3

C1 Y

Page 35: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.

XOR Gate

A B

AB


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