PARBIT Partial Bitfile Configuration Tool
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PARBIT Tool 1 PARBIT Partial Bitfile Configuration Tool Edson L. Horta ([email protected]) Washington University, Applied Research Lab August 15, 2001 Supported by: NSF ANI-0096052; Xilinx Inc. and CNPq (Brazil)
description
PARBIT Partial Bitfile Configuration Tool. Edson L. Horta (horta @arl.wustl.edu ) Washington University, Applied Research Lab August 1 5 , 2001 Supported by: NSF ANI-0096052 ; Xilinx Inc. and CNPq (Brazil). Motivation. FPX. RECATS. Single chip ATM Switch VIRTEX FPGA - PowerPoint PPT Presentation
Transcript of PARBIT Partial Bitfile Configuration Tool
PARBIT Tool 1
PARBITPartial Bitfile Configuration Tool
Edson L. Horta
Washington University, Applied Research Lab
August 15, 2001
Supported by: NSF ANI-0096052;Xilinx Inc. and CNPq (Brazil)
PARBIT Tool 2
Single chip ATM SwitchVIRTEX FPGAPartial Reconfigurablewww.lsi.usp.br/~recats
VIRTEX FPGAPartial ReconfigurableDynamic Hardware Pluginhttp://www.arl.wustl.edu/arl/projects/fpx
Motivation
RECATS
Mutual Need: tool to generate partial configuration files for
VIRTEX FPGA
FPX
PARBIT
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VIRTEX Architecture
• Resources– CLBs– IOBs– Block SelectRAMs– Clocks
• Configuration– bitstream: configuration bitfile– configuration columns
• Center• CLB• IOB• Block SelectRAM Interconnect• Block SelectRAM Content
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VIRTEX Architecture
• Configuration ColumnsLe
ft IO
B Co
lum
n
Bloc
k Se
lect
RAM
Inte
rcon
nect
Bloc
k Se
lect
RAM
Con
tent
2IOBs
2GCLKs
2IOBs
2IOBs
2IOBs
2IOBs
2IOBs
2IOBs
2GCLKs
CLB
Colu
mn
CLB
Colu
mn
Cent
er C
olum
n
CLB
Colu
mn
CLB
Colu
mn
Righ
t IO
B Co
lum
n
2IOBs
Bloc
k Se
lect
RAM
Con
tent
Bloc
k Se
lect
RAM
Inte
rcon
nect
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PARBIT Tool - Introdution
• A Tool that transforms configuration bitfiles to generate partial configuration bitfiles with hardware realocation
• Command-line interface• Environment
– Windows (Cygwin)– Unix
• Devices supported:– XCV50E, XCV100E, XCV200E, XCV300E, XCV400E,
XCV405E, XCV600E, XCV812E, XCV1000E, XCV1600E, XCV2000E,XCV2600E, XCV3200E.
• http://www.arl.wustl.edu/arl/projects/fpx/parbit/
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PARBIT Tool - Introdution
ENDN
Error MessageParametersOK ?
Write Trailer
Y
Write Header
User Parameters
Copy Config. Bits
END
FPGA TypeCoordinatesShutdownConfiguration Port
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PARBIT Tool - Introdution
• Utilization– parbit option original partial target
• Input Files– option: user parameters– original: Dynamic Hardware Plugin (DHP)
bitstream – target: infrastructure bitstream
• Output File– partial: generated partial bitstream
• Generating the input bitstream files– Xilinx Tools– Constraints commands in the UCF file
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PARBIT Tool - Introdution
• Original Bitstream File– DHP User Module – Locks the interface signals to the infrastrucuture– Locks the area of user logic
• Target Bitstream File– Infrastructure Logic– Locks the interface signals to the DHP User
Module– Allocate blank areas (targets) to download new
DHP Modules
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PARBIT Tool – Original Bitstream
– Dynamic Hardware Plugin (DHP) confined in a rectangular region
– PARBIT parameters
• Start Row and Start Col
• End Row and End Col
Left
IOBs
RAM
RAM
RAM
RAM
RAM
RAM
Right IOBs
RAM
RAM
Bottom IOBs
Top IOBs
Start Column = 8
End Column = 17
DHP
End Row = 74
Start Row = 7
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FD
FD
FD
FD FD
FD
FD
FDdout din
dout
dout
dout
din
din
din
gask_out[0]
gask_out[1]
gask_out[2]
gask_out[3]
gask_in[0]
gask_in[1]
gask_in[2]
gask_in[3]
INGASK
DHP
COL8COL5
gask_clk
GASK_DHP
OUTGASK
OUTGASK
OUTGASK
OUTGASK INGASK
INGASK
INGASK
• Interface signals and flops
Original Bitstream - DHP Module
• DHP User Module
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DHP User Module - Example
• 8 stages of combinatorial function, with registered outputs• Connects to gas_dhp entity buses (din, dout)• Consumes 32 CLBs
Func
tion
Func
tion
Func
tion
din[1]
din[0]
din[2]
din[3]
dout[0]
dout[1]
dout[2]
dout[3]
clk
Stage 1Stage 7 Stage 0
USER_DHP_V101
CK
DQ
CK
DQ
CK
DQ
CK
DQ
CK
DQ
CK
DQ
CK
DQ
CK
DQ
CK
DQ
CK
DQ
CK
DQ
CK
DQ
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DHP Module - VHDLlibrary IEEE; use IEEE.std_logic_1164.all;
-- Top Level Entity of DHP also specifies -- pins so that a FPGA can be routed and placedentity gask_dhp is port( gask_in: in std_logic_vector(3 downto 0); gask_clk: in std_logic; gask_out: out std_logic_vector(3 downto 0)); end gask_dhp;
library IEEE; use IEEE.std_logic_1164.all; USE ieee.std_logic_arith.ALL;
-- Entity of a Dynamic Hardware Pluginentity dhp is port( din: in std_logic_vector(3 downto 0); clk: in std_logic; dout: out std_logic_vector(3 downto 0)); end dhp;
architecture dhp_arch of dhp is -- The User's Module Logic goes HERE
signal stage0_sig: std_logic_vector (3 downto 0);signal stage1_sig: std_logic_vector (3 downto 0);signal stage2_sig: std_logic_vector (3 downto 0);signal stage3_sig: std_logic_vector (3 downto 0);signal stage4_sig: std_logic_vector (3 downto 0);signal stage5_sig: std_logic_vector (3 downto 0);signal stage6_sig: std_logic_vector (3 downto 0);
begin
Stage0: process (clk) begin if(clk'event AND clk = '1') then stage0_sig(0) <= NOT din(0) OR din(1); stage0_sig(1) <= din(2) XOR din(0); stage0_sig(2) <= NOT din(3) NOR din(2); stage0_sig(3) <= din(1) AND din(0); end if; end process;
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DHP Module - VHDL-- The User's Module is the Main Component of
the Module design component dhp is port( din: in std_logic_vector(3 downto 0); clk: in std_logic; dout: out std_logic_vector(3 downto 0)); end component;
signal ding,doutg:std_logic_vector(3 downto 0);
begin
D: dhp port map(ding,gask_clk,doutg);
-- Specifies the same Flops in the same locationG: for i in 0 to 3 generate
INGASK : FD port map( gask_in(i), gask_clk, ding(i));
Stage1: process (clk)……………………………………………………………………Stage7: process (clk) begin if(clk'event AND clk = '1') then dout(0) <= stage6_sig(2) NAND stage6_sig(0); dout(1) <= NOT stage6_sig(3) NAND
stage6_sig(3); dout(2) <= NOT stage6_sig(0) XOR
stage6_sig(2); dout(3) <= stage6_sig(1) NAND stage6_sig(1); end if; end process;
end dhp_arch;
architecture gask_dhp_arch of gask_dhp is component FD port( D: in std_logic; C: in std_logic; Q: out std_logic); end component;
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DHP Module - VHDL and UCF File
# Include Region for DHP User ModuleINST /D* LOC=clb_r3c6:clb_r6c7; # FLOPSINST /OUTGASK_0* LOC=clb_r3c5.s0;INST /OUTGASK_1* LOC=clb_r4c5.s0;INST /OUTGASK_2* LOC=clb_r5c5.s0;INST /OUTGASK_3* LOC=clb_r6c5.s0;
INST /INGASK_0* LOC=clb_r3c8.s1;INST /INGASK_1* LOC=clb_r4c8.s1;INST /INGASK_2* LOC=clb_r5c8.s1;INST /INGASK_3* LOC=clb_r6c8.s1;
# gask_dhp.ucf# PINSNET gask_clk LOC=B8;NET gask_in<0> LOC=C8;NET gask_in<1> LOC=B7;NET gask_in<2> LOC=A6;NET gask_in<3> LOC=D8;NET gask_out<0> LOC=F3;NET gask_out<1> LOC=D1;NET gask_out<2> LOC=G3;NET gask_out<3> LOC=F5;
OUTGASK : FD port map( doutg(i), gask_clk, gask_out(i));
end generate;
end gask_dhp_arch;
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DHP Module – FPGA Editor (XCV50E)
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ROW 6
ROW 4
ROW 5
ROW 3
COL 5 COL 6 COL 7 COL 8
DHP Module – FPGA Editor (XCV50E)
DHP User
Module
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PARBIT Tool – Target Bitstream
– Infrastructure with target regions reserved for DHP modules insertions
– PARBIT parameters
• Target Locations (Row, Col)
Right IO
BsL
eft I
OB
s
Top IOBs
RA
M
RA
M
RA
M
RA
M
RA
M
RA
M
TARGET 1 TARGET 2 TARGET 3 TARGET 4T1 (7,8) T2 (7,20) T3 (7,68) T4 (7,80)
Bottom IOBs
INFRASTRUCTURE
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Target Bitstream - Infrastructure Module
FD FD
FD FDgask_out[1]
GASKOUT GASKIN
FD FDgask_out[2]
GASKOUT GASKIN
FD FDgask_out[3]
GASKOUT GASKIN
gask_out[0]
gask_in[0]
gask_in[1]
gask_in[2]
gask_in[3]
GASKIN
GASK_INF
GASKOUT
GASK_IO[0]
GASK_IO[1]
GASK_IO[2]
GASK_IO[3]
COL5 COL8
gask_clk
• On-chip system logic
• Interface signals and flops
• I/O Pads
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Infrastructure Module - VHDLlibrary IEEE; use IEEE.std_logic_1164.all;
-- Top Level Entity of Infrastructureentity gask_inf is port( gask_in: in std_logic_vector(3 downto 0); gask_clk: in std_logic; gask_out: out std_logic_vector(3 downto 0)); end gask_inf;
library IEEE; use IEEE.std_logic_1164.all;
-- Each gask_io module provides an input/ouput-- interface between the infrastructure and
moduleentity gask_io is port( di: in std_logic; clk: in std_logic; qo: out std_logic); end gask_io;
architecture gask_io_arch of gask_io is component FD port( D: in std_logic; C: in std_logic; Q: out std_logic); end component;
signal q0 : std_logic;
-- Each gas_io module has two Flops, one-- on each edge of DHPbegin GASKIN : FD port map(D => di, C => clk, Q => q0);
GASKOUT: FD port map(D => q0, C => clk, Q => qo);
end gask_io_arch;
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Infrastructure Module - VHDL and UCF Filearchitecture gask_inf_arch of gask_inf is component gask_io port( di: in std_logic; clk: in std_logic; qo: out std_logic); end component;
begin G: for i in 0 to 3 generate
-- Bus contains an array of gask_io modules GASK : gask_io port map( gask_in(i), gask_clk, gask_out(i));
end generate;
end gask_inf_arch;
# Exclude Region for DHP User ModuleCONFIG PROHIBIT=CLB_R3C6:CLB_R6C7;
# FLOPSINST /GASK_0/GASKOUT* LOC=clb_r3c5.s0;INST /GASK_1/GASKOUT* LOC=clb_r4c5.s0;INST /GASK_2/GASKOUT* LOC=clb_r5c5.s0;INST /GASK_3/GASKOUT* LOC=clb_r6c5.s0;
INST /GASK_0/GASKIN* LOC=clb_r3c8.s1;INST /GASK_1/GASKIN* LOC=clb_r4c8.s1;INST /GASK_2/GASKIN* LOC=clb_r5c8.s1;INST /GASK_3/GASKIN* LOC=clb_r6c8.s1;
# gask_inf.ucf# PINSNET gask_clk LOC=B8;NET gask_in<0> LOC=C8;NET gask_in<1> LOC=B7;NET gask_in<2> LOC=A6;NET gask_in<3> LOC=D8;NET gask_out<0> LOC=F3;NET gask_out<1> LOC=D1;NET gask_out<2> LOC=G3;NET gask_out<3> LOC=F5;
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Infrastructure – FPGA Editor (XCV50E)
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COL 5 COL 7COL 6 COL 8
ROW 3
ROW 4
ROW 5
ROW 6
Infrastructure – FPGA Editor (XCV50E)
Reserved Area
(Target) for DHP Module
Flops and Interconnect Signals(Same location as in DHP Module)
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PARBIT Tool - Example
• Utilization– parbit option original partial target
• Example– Visit:
http://www.arl.wustl.edu/arl/projects/fpx/parbit– In the Download Section, right click on
parbit-expl.tar
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Demonstration
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PARBIT Tool - Demonstration
• Example (Cygwin Window)– Run parbit
• parbit parbit-gask.opt gask_dhp.bit gask-part.bit gask_inf.bit• Compare the sizes of gask_dhp.bit and gask-part.bit
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PARBIT Tool - Exercises
Exercise 1 Change the user parameters and generate a new partial
configuration bitstream (gask-part2.bit) for one user module confined in a rectangular area with:
– Start row = 2– Start col = 5– Height = 3 rows– Width = 4 columns– Target location = Row 10, Col 15
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PARBIT Tool - Exercises
Exercise 2• Go to the PARBIT web page and get the project files for
the gasket example (gask-design.tar)• Modify the UCF files in order to change the location of
the DHP user module two rows down• Compile each project:
– xflow –p xcv50e-8-fg256 –implement gask-i gask_dhp
• Open each project with the FPGA Editor:– fpga_editor gask_dhp.ncd
• Check the new logic locations• Edit the file gask_dhp.ucf
– Add 2 to the row numbers (rX)
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ORIGINAL BITS
Configuration Frames - Full Slice
TARGET BITS
TARGET BITS
