Parameter Variations and Impact on Circuits and Micro Architecture

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Parameter Variations and Impact on Circuitsand M croarchi ecture

Shekhar Borkar, Tanay Karnik, Siva Narendra, Jim Tschanz, Ali Keshavarzi, Vivek DeCircuit Research, Intel Labs, JF3-334, 21 11 NE 2!jthAve, Hillsboro, OR [email protected] ABSTRACTParameter variation in scaled technologies beyond 90nm willpose a major challenge for design of future high performancemicroprocessors. In this paper, we discuss process, voltage andtemperature variations; and their impact on circuit andmicroarchitecture. Possible solutions to reduce the impact ofparameter variations and to achieve higher frequency bins arealso presented.Categories and Subject DescriptorsB.7.1 Microprocessorsandmicrocomputers, VLSI.General Terms: Design, Performance, Reliability.Keywords: Parameter variation, high performance deisgn,body bias.1. INTRODUCTIONSystematic and random variations in process, supply voltage andtemperature (P, V, T) are posing a major challenge to the futurehigh performance microprocessor design [1,2]. Technologyscaling beyond 90nm is causing higher levels of deviceparameter variations, which are changing the design problemfrom deterministic to probabilistic [3,4]. The demand for lowpower causes supply voltage scaling and hence making voltagevariations a significant part of the overall challenge. Finally, thequest for growth in operating frequency has manifested insignificantly high junction temperature and within dietemperature variation. We discuss the impact of P, V, Tvariations on circuits and microarchitecture. We will alsopresent possible solutions to reduce or tolerate the parametervariations in high frequency microprocessor designs.The paper is organized as follows. Process, supply voltage andtemperature variations are introduced in Section 2. The seriousimpact of these variations on circuits and microarchitecture ispresented in Sect ion 3. Section 4 consists of possible solutionsto mitigate parameter variation including V, modulation byforward body bias (FBB), leakage reduction by reverse bodybias (RBB) or power/performance tradeoff by adaptive bodybias (ABB). Section 4 also includes approaches to controlsupply voltage and temperature variations. We conclude thispaper in Section 5 .

Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and thatcopies bear this notice and the full citation on the first page. To copyotherwise, or republish, to post on servers or to redistribute to lists,requires prior specific permission and/or a fee.DAC2003, June 2-6,2003,Anaheim, Califomia,USA.Copyright 2003 ACM 1-58113-688-9/03/0006.. 5.00.

2. VARIATIONS - P, V, TIn this section, we will introduce the P, V, T variations based onmeasurement data in advanced CMOS technologies.2.1 Process VariationsFigure 1 plots distributions of frequency and standby leakagecurrent (I$,) of microprocessors in a wafer. The spread infrequency and leakage distributions is due to variation intransistor parameters, causing about 20x variation in chipleakage and 30% variation in chip frequency. This variation infrequency has introduced the concept of frequency binning.Notice that the highest frequency chips have a wide distributionof leakage, and for a given leakage, there is a wide distributionin the frequency of the chips. The highest frequency chips withlarge I$,, and low frequency chips with reasonably high ISb mayhave to be discarded, affect ing the yield.

1.4,

$1.3-a,g1.2-

. 1.1U.U --

1.0-z

_ _0 15Normalii~dLeakageIsb) 20

Figure 1: Leakage and frequency variationsThe spread in standby current is due to variation in channellength and variations in the threshold voltage. Figure 2illustrates the die-to-die Vt distribution and its resulting chip ISbvariation. V, variation is normally distributed and its 30variation is about 30mV in a 18Onm CMOS logic technology.This variation causes a significant variation in circuitperformance and leakage. The most critical paths in a chip maybe different from chip to chip. Figure 2 also shows the 2Ox ISbvariation distribution in detail.I I

39.71 -25.27 -10.83 3.61 18.05 32% 20.11 16.29 12.47 8.64 4.82 1.00AVm(mV) (Normalied)Figure 2: Die-to-dieV , Isbvariation

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2.2 Supply Voltage Variations

Time @sec)Figure 3: Supply voltage variation

Variations in switching activity across the die and diversity ofthe type of logic, result in uneven power dissipation across thedie. This variation results in uneven supply voltage distributionand temperature hot spots, across a die, causing transistorsubthreshold leakage variation across the die.Supply voltage (Vcc) will continue to scale modestly by 15%,not by the historic 30%per generation, due to (1) difficulties inscaling threshold voltage (VJ, and (2) to meet the transistorperformance goals. Maximum Vcc is specified as a reliabilitylimit for a process and minimum Vcc is required for the targetperformance. Vcc variation inside the max-min window isshown in Figure 3 . This figure shows a droop in Vcc, whichdegrades the performance. Packaging and platform technologiesdo not follow the scaling trends of CMOS process. Therefore,power delivery impedance does not scale with Vcc and AVcchas become a significant percentage of Vcc.2.3 Temperature VariationFigure 4 shows the thermal image of a leading microprocessordie with as high as 120C hot spots.

1.37 1.30 1.22 1.15 1.07 1.00Frequency (Normalized)

Figure 5: Die-to-die frequency variationparts need to be discarded which in turn affects the yield andhence the cost.3. IMPACT ON CIRCUITS ANDMICROARCHITECTUREThe P, V, T variations impact all levels of design. In this sectionwe will highlight some of the impact process has on circuit andmicroarchitecture design choices.Dual-Vt circuit designs [5,6] can reduce leakage power duringactive operation, burn-in and standby. Two V,s are provided bythe process technology for each transistor. High-V, transistors inperformance critical paths are either upsized or are made low-Vtto provide the target chip performance. Figure 6 is a conceptualview of this tradeoff. On the left side, larger transistor sizesincrease the relative probability of achieving the targetfrequency at the expense of switching power. The right chartshows that increasing low-V, usage also boosts the probability,but with a penalty in leakage power. It was shown in [5,6], thatby carefully employing low-V, devices, 24% delay improvementis possible to trade off leakage and switching powercomponents, while maintaining the same total power.

Figure4: Within die temperature variationWithin die temperature fluctuations have existed as a majorperformance and packaging challenge for many years. Both thedevice and interconnect performance have temperaturedependence, with higher temperature causing performancedegradation. Additionally, temperature variation acrosscommunicating blocks on the same chip may cause performancemismatches, which may lead to logic or functional failures.The net consequence of the P, V, T variation manifests itself onchip fiequency variation. Figure 5 rolls up the distribution ofmicroprocessor dies in 18Onm technology across a fiequencyrange. Variation in frequency is due to variation of otherparameters discussed in Figure 2. This frequency distributionhas serious cost implications associated with it: Low performing

I ower I

small largeTransistor size

I arget frequency probability

0.50 less moreLow-Vt usage

Figure 6: Circuit design tradeoffsThe number of critical paths that determine the target fiequencyvary depending on the microarchitecture design choice.Microarchitecture designs that demand increased parallelismand/or functionality require increase in the number of criticalpaths. Designs that require deeper pipelining, to support higherfiequency of operation, require increase in the number of criticalpaths and decrease in the logic depth. The impact processvariation has on these choices are described next.Testchip measurements in Figure 7 show that as the number ofcritical paths on a die increases, within-die delay variationsamong critical paths cause both mean (p)and standard deviation(0 )of the die frequency distribution to become smaller. This isconsistent with statistical simulation results [11 indicating that

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Clock kequencyFigure 7: Die-to-die critical path distribution

the impact of within-die parameter variations on die frequencydistribution is significant. As the number of critical pathsexceeds 14, there is no noticeable change in the fiequencydistribution. So , microarchitecture designs that increase thenumber of critical paths will result in reduced mean frequency,since the probability that at least one of the paths is slower willincrease.Historically, the logic depth of microarchitecture critical pathshas been decreasing to accommodate a 2x growth in theoperating frequency every generation, faster than the 42%supported by technology scaling. As the number of logic gatesthat determine the frequency of operation reduces, the impact ofvariation in device parameter increases, as illustrated in Figure8. Measurement on 49-stage ring oscillators showed that (T ofthe within-die fiequency distribution was 4x smaller than 0 ofthe device saturation current distribution [I]. However,measurements on a testchip containing 16-stage critical pathsshow that 0 s of within die (WID) critical path delaydistributions and NMOS/PMOS drive current distributions arecomparable.

Logic depth: 16

5.6%

LogicdepthFigure 8: Impact of logic depth

Figure 9 summarizes the impact of process variation on themicroarchitecture design choices. The bar charts conceptuallyshow that with either smaller logic depth or with increasingnumber of microarchitecture critical paths, performanceimprovement is possible. However, the probability of achievingthe target frequency that translates to performance, drops due tothe impact of within-die process variation.4. VARIATION TOLERANCE ANDREDUCTIONIn this section, we describe some of the research and designwork to enhance the variation tolerance of circuits andmicroarchitecture and to reduce the variations by clever circuitand microarchitectural techniques. We first describe the body

performance target frequency probabili ty--large small less more# uArch critical pathsogic depth

Figure 9: Microarchitecture tradeoffs(substrate) biasing techniques, followed by supply voltage and

temperature variation tolerance methods.

Device performance can be improved by lowering V,, however,that leads to higher leakage current Isb. One possible method totrade off performance with leakage power is to apply a separatebias to critical devices.

4.1 Body Bias Control Techniques

4.1.1 Vt Modulation by Forward Body Bias (FBB)

Figure 10: OptimalFBB for sub30nm generationsDevice V, is a function of body to source potential (VBs).V, canbe modulated for higher performance by forward biasing thebody. This method also reduces the impact of short channeleffects, hence reducing V, variations. Figure 10 plots thepercentage frequency gain as a function of FBB. It was shownempirically that 450mV is the optimal FBB for sub-9Onmgenerations at high temperature [7].

Figure 11: Forward body bias evaluation testchipA 6.6M transistors communications router chip [8], with on-chip circuitry to provide forward body bias (FBB) to PMOSdevices during active operation and zero body bias (ZBB)during standby mode, was implemented in a 150nm CMOStechnology (Figure 11). FBB is withdrawn during standby modeto reduce leakage power.

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0.9 1.1 1.3 1.5 1.7vcc (v)Figure 12: Forward body bias results

Performance of the chip is compared with the original designthat has no body bias (NBB) in Figure 12. F of the NBB andFBB router chips are compared from 0.9V to 1.8V Vcc at 6OoC(Figure 13). The FBB chip with forward body bias achieveslGHz operation at l .l V, compared to 1.25V required for theNBB chip. The switching power is 23% smaller at 1GHz. Thefrequency of FBB is 33% higher than NBB at 1.1V.4. .2 Leakage Reduction by Reverse Body Bias

1E-05@B)150nm,27C

I 40.5 1 1.5E-0%Reverse V (V)

Figure 13: Leakage reduction by reverse body biasAn alternate method for reducing Isb is to apply reverse VBS.Figure 13 plots the leakage current for the worst-case channellength (L, dashed) and the nominal channel length (L,,,dotted) as a function of RBB. The measured full-chip leakagecurrent is within these upper and lower leakage current boundsover a range of RBB values. The optimum RBB value derivedfrom the measured chip for minimum leakage is 500mV [ 9 ] .Using RBB values larger than this value causes the junctionleakage current to increase and overall leakage power to go up.However, effectiveness of RBB reduces as channel lengthsbecome smaller or V, is lowered. Essentially, the V,-modulationcapability by RBB weakens as short-channel effects becomeworse or body effect diminishes due to lower channel doping.4. .3 Power/Performanceand Bin Improvement byAdaptive Body Bias (ABB)The previous two subsections presented the advantages of bothFBB and RBB. It is possible to utilize both of these approachesas shown in Figure 14. Due to the frequency spread in fabricatedparts caused by process variations, the low frequency parts maybe discarded for lower performance and the high frequency partsmay be discarded for higher leakage power. As shown on theright side, devices can be adaptively biased to increase theperformance of the slow parts by FBB and to decrease leakagepower of the fast parts by RBB.

FrequencyFigure 14: Target frequency binning by adaptive body bias

A testchip (Fig. 15) has been implemented in a 15Onm CMOStechnology to evaluate effectiveness of the adaptive body bias(ABB) technique [ lo ] for minimizing impacts of both die-to-dieand within-die parameter variations on processor frequency andactive leakage power. The bias is based on a 5-bit digital code,which provides one of 32 different body bias values with 32mVresolution to PMOS transistors. NMOS body is biasedexternally across the chip.

Number of- 21dBodybias range :4zLE lo

I 32mV IFigure 15: Adaptive body bias evaluation testchip

Bidirectional ABB is used for both NMOS and PMOS devicesto increase the percentage of dies that meet both frequencyrequirement and leakage constraint. As a result, die-to-diefrequency variations( d ~ )educe by an order of magnitude, and100% of the dies become acceptable (Figure 16). Bin 2 is thehighest frequency bin while Bin 1 is the lowest acceptablefrequency bin - any dies that are slower than Bin 1 arediscarded. Almost 50% of dies with NBB fell below Bin 1 butare recovered using ABB. In addition, 30% of the dies are nowin the highest frequency bin allowed by the power density limit.WID-ABB (applying multiple bias values per die to compensatefor within-die as well as die-to-die variation) reduces 0 f thedie frequency distribution by SO%, compared to ABB. Inaddition, almost all of the dies are accepted in the highestpossible frequency bin, compared to 30% for ABB.

100%-280%

60%5 40%En

$20%w/*," Bin 1 Bin2 Bin 3

Figure 16: Adaptive body bias results

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4.2 Supply Voltage and TemperatureControl Techniques

740/o BFixedVccW Adaptive Vcc

E3 20%Bin 2 Bin3 .=

Figure17: Bin improvement by adaptive VccAs introduced in Section 3, variations in switching activityacross the die, and diversity of the type of logic, results inuneven power dissipation across the die. This variation results inuneven supply voltage distribution and temperature hot spots.A technique to increase yield in the high frequency bins, is toapply adaptive Vcc. Figure 17 shows the advantage of adaptiveVcc over fixed Vcc. Bin 3 is the highest frequency bin, whileBin 1 is the lowest acceptable frequency bin. The dark barsindicate that adaptive Vcc has pushed more than 20% dies fromBin 1 to Bin 2 and even Bin 3, as well as recovered those diesthat fell below Bin 1 .

Tmc n,

Figure 18: Effectivenessof on-die decoupling capacitorsAdaptive Vcc does not solve the AVcc problem. Figure 18shows a well-known technique to mitigate voltage variations,namely, adding on-die decoupling capacitors. AVcc reducesfrom 15% to 4 0 % by carefully placing appropriate amount ofdecaps on microprocessor dies [l I] . However, it has to be notedthat decoupling capacitors cost silicon area. In sub-90nmtechnologies designers are facing a challenge of gate oxideleakage. Decap layouts are designed for high capacitance to arearatio, however, that tends to increase the gate oxide area. Theoxide leakage and area penalty must be traded off with AVcc.

I I

I Throttle f

I ITime @sec)Figure 19: Temperature based Vcdfrequency throttl ing

Maximum temperature and within die temperature variationshave to be controlled. Throttling is used to control the dietemperature. Figure 19 explains the method. When thetemperature rises above the maximum limit set by frequency andpower, the operating frequency is lowered, followed by the dieVcc. Subsequently, the power consumption drops followed by adrop in on-die temperature. When the die comes out of powersaving mode, Vcc is raised followed by frequency. Manycommercial processors incorporate throttling.5. CONCLUSIONSWe presented a major challenge for future designs at circuit andmicroarchitecture levels, namely, parameter variations. Wediscussed process, voltage and temperature variations; and theirimpact on circuit and microarchitecture. Possible solutions toreduce the impact of parameter variations and to achieve higherfrequency bins were also presented. Variations will posesignificant challenge, necessitating a shift in the designparadigm, from todays deterministic design to statistical orprobabilistic design.6. REFERENCES[l] Bowman, K., et. al, Impact of die-to-die and within-dieparameter fluctuations on the maximum clock frequency

distribution for gigascale integration, IEEE Journal ofSolid-state Circuits, Volume 37, Feb 2002, pp.183-190.

[2] Borkar, S ., Parameter Variations and Impact on Circuits &Microarchitecture, C2S2 MARC0 review, March 2003.131 Sery G., et al., Life is CMOS: why chase the life after?[4] Kamik, T., et al., Sub-9Onm Technologies-Chal lengesand Opportunities for CAD, ICCAD 2002, pp. 203-206.[5] Kamik, T., et al., Total power optimization by

simultaneous dual-Vt allocation and device sizing in highperformance microprocessors, DAC 2 002, pp. 486-491.

[6] Tschanz, J., et al., Design optimizations of a highperformance microprocessor using combinations of dual-Vtallocation and transistor sizing, VLSI Circuits Symposium

[7] Tschanz, J., et al., Dynamic-Sleep Transistor and BodyBias for Active Leakage Power Control of Micro-processors, ISSCC 2003, pp.102-103.

[8] Narendra, S. , et al., 1.1 V 1 GHz communications routerwith on-chip body bias in 150 nm CMOS, ISSCC 2002,[9 ] Keshavarzi, A., et al., Effectiveness of Reverse Body Bias

for Leakage Control in Scaled Dual Vt CMOS Ics,ISLPED 2001, pp.207-210.

[10]Tschanz, J., et al., Adaptive Body Bias for ReducingImpacts of Die-to-Die and Within-Die ParameterVariations on Microprocessor Frequency and Leakage,

[llIRahal-Arabi, T., et al., Design and validation of thePentium 111 and Pentium 4 processors power delivery,VLSI Symposium 2002, pp220-223.

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pp. 270-271.

ISSCC 2002, pp.422-423.

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Parameter Variations and Impact on Circuits and Micro Architecture

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