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Designing a Compact Genetic Algorithm with MinimalFPGA Resources

Alejandro Len-Javier1, Marco A. Moreno-Armendriz

1and

Nareli Cruz-Corts1,

1 Centro de Investigacin en Computacin - IPNAv. Juan de Dios Batz s/n Unidad Profesional Adolfo Lpez Mateos

Col. Nueva Industrial Vallejo, Mexico City, 07738, [email protected], {marco_moreno, nareli}@cic.ipn.mx

Abstract. The Compact Genetic Algorithms (cGA) are searching methods used

in different engineering applications. These algorithms have interesting featuressuch as their capability to operate with very low memory resources whilesolving complex optimization problems. In this paper we present a novel designfor the implementation of a cGA on a FPGA. This design is modular, so itscomponents would be used for designing other Evolutionary Algorithms.

Keywords: Compact Genetic Algorithm, FPGA implementation, minimalresources.

1 Introduction

The Compact Genetic Algorithms (cGA) are searching methods based on the

behavior of the standard Genetic Algorithm with uniform crossover [1]. The cGA are

very useful tools for applications where there are only few resources of memory and acomplex optimization problem must be solved [2].

For applications that require real time processing while doing global numerical

optimization, the Evolutionary Algorithms, such as the Genetic Algorithms, can be a

competitive option; however most of them require a huge amount of resources and

execution time. To overcome this problem the cGA were developed [3]. In our

opinion, a competitive cGA implemented in hardware, must accomplish the three

following requirements: 1) it should be based on a top-down methodology with a

group of basic synchronized components through a machine states, 2) to use minimal

resources, and 3) it must have the ability to operate in real time. So, we decided to

implement it by using a FPGA with the VHDL language.

In the specialized literature, we can find some works implementing Evolutionary

Algorithms based on a hardware platform. For example, in [4] it was proposed the

design of a Genetic Algorithm (GA) working as an optimization engine on a FPGA.

In that work the authors take advantage of some important features exhibited by a

FPGA, such as parallelization and reprogramming, to increase the GA's speedup.


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Some other proposals presented VLSI-based architectures for coarse and fine

grained parallel GA [5].

In [6] a chip LSI is described. It includes hardware, reconfigurable logic hardware,

a memory to maintain the individuals, a training data memory and, a 16-bits CPU

core.

In [7] a cGA design and implementation was presented by using languageVERILOG.

Gallagher et al., [8] proposed to add elitism and mutation to the cGA. These

features improved the solutions found by the cGA in a very important manner. In

addition to that, they proposed to use a modular design to implement this algorithm on

micro-controllers using VHDL.

In [9] the authors proposed a parallel cellular cGA topology which is implementedon a FPGA.

In addition to the mentioned proposals, there exist other GA implementations.

Some of them require more than one FPGA. All these disadvantages show up thenecessity of having a cGA version properly implemented on a hardware platform.

2 The Compact Genetic Algorithm

The cGA represents a population of potential solutions to a problem, through a

probability distribution over the s et of possible solutions, called a Probability Vector

(PV). This PV is processed by an updating rule based on the typical operations of

selection and crossover of a GA [2]. The PVis initialized with value 0.5 and, at theend of the algorithm's execution it must contain only 0s or 1s. This final vector

represents the solution obtained by the cGA.

The pseudo code of the cGA is presented in Figure 1. The input parameters for this

algorithm are the following: population size (n) and the chromosome length (l). A

population is represented by a 1-dimensional Probability Vector (PV). The PV[i] is

the probability that the i th-position bit of an individual, randomly picked up from the

population, will be one. First, thePV is initialized to (0.5, 0.5,..., 0.5). Next, theindividuals a and b are generated according to the PV. Then, the fitness value of the

individuals is compared and, the element with better fitness is named the winner and

the other one is called loser. Now, ifwinner[i] loser[i], thePVof the winner will be

updated as follows: If the winner[i]=1 then the PV will be increased by 1/n, if

winner[i] loser[i] the VPwill be decreased by 1/n. Note that ifwinner[i] = loser[i],

the VP will not be updated. The loop is repeated until each PV[i] becomes zero orone. Finally,PVrepresents the final solution [7].


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Fig. 1. Pseudo code for the cGA [3]

3 VHDL design

For the VHDL design we need to consider different issues. The cGA algorithm

needs that thePVcontains real numbers and its updating rule (plus or minus 1/n) mustkeep its values into the interval (0,1). However, for this implementation, we decided

to use a random generator [10] that generates integer numbers in the range (0,

2147483647). Then, this means that the values in the PVmust be in the same rangebecause we need to do comparisons between these elements.

In this work, we defined different components in order to obtain the possibility to

perform different calculus at same time. These components are explained next:

Random Number Generator (RNG). This component generates the random

numbers used for the individuals generation. There exists different kinds of

algorithms, we decided to use a very efficient one proposed by Park & Miller in [10],

and it generates the next random numberIj+1 based on the following expression:

Ij+1=aIj mod m. (1)

1) Initialize probability vectorfor i:=1 to l do VP[i]:=0.5;

2) Generate two individuals from the vectora:=generate(VP);

b:=generate(VP);

3) Let them competewinner, loser:=compete(a,b);

4) Update the probability vector towards the better onefor i:=1 to l do

ifwinner[i]loser[i] then

ifwinner[i]=1 then

VP[i]:= VP[i]+1/n;

else

VP[i]:= VP[i]-1/n;

5) Check if the vector has convergedfor i:=1 to l do

if VP[i]>0 and VP[i]


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With a = 75 = 16807 and m = 231-1 = 2147483647. In order to use this RNG with

32 bits, we must join it with the Schrage algorithm [10]. So, the new form of theexpression is:

Ij+1=aIj mod m= aIj mod q-r[Ij/q] IfIj+1 0aIj mod q-r[Ij /q]+m Otherwise

(2)

With q = 127773 and r= 2836.

Individual Generator (IndGen). This component receives two random numbers and

the PV. It generates two bits ( rng1 and rng2), the first bit (rng1) corresponds to the

individual one (ind1) and, the second bit (rng2) to the individual two (ind2) at thesame position. The conditions for the generation of the numbers are shown in Figure

2.

Fig. 2. Pseudo code of the individual generator component.

Fitness Evaluator (FEv). The evaluation is made by using two individuals in thefollowing way: First, we measure the fitness of each individual and compare them, if

the fitness of the individual one is greater or equal than the fitness of the individual

two, then the winner is the individual one, otherwise the individual two wins

(assuming that we are handling a maximization problem). The definition of the fitness

function depends on the kind of optimization problem to be solved. Once the fitness

function is selected, this function must be implemented in VHDL code to finish this

component.

Probability Vector Updating (PVU). To update the PV three data are received: 1)

who is the winner, 2) the bit from individual 1 in the current position and 3) the bit

from individual 2 in the current position. Then we apply the conditions presented in

Figure 3.

Where:y op indicates which individual is the winner. The value '1' is for the

number one and '0' for the number two.

if rng1


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y oe is used to specify if the current bits of both individuals are equal (value

'1') or not (value '0').

Fig. 3. Conditions for updating the PV.

The conditions vect23 (min) are required to restrict

the variations of the vector to the interval (0, 2147483647), for the reason that we are

working with elements of 32 bits. The max and min values of the variable vectare

defined by the number of individuals in the population, in our design we use 50, so

the step size is 42949672. It is possible to modify this number by changing the values

of the step size and the max and min values.

Probability Vector Checking (PVC). Here we verify if the probability vector (PV)

already converges to the max or min values, when this event occurs the flag is set to

RDY='1'.

Compact Genetic Algorithm (cGA). This is the main component and is based on the

other components. To obtain a correct synchronization we use a finite state machine,

presented in the next section.

4 Finite-State Machine

A finite-state machine is a sequential circuit with a finite number of states. The

usage of this machine guaranties the correct behavior of the whole design. The

machine is defined by two functions, the first one calculates the next state of the

system and the second one the output [11].

There are two kinds of finite-state machines, the Mealys and the Moores. In our

case we use the Mealy. This type of machine uses a clock as synchronized signal for

the transitions. We used it for the cGA component as it is shown in Figure 4. For the

if (oe='1'and ind1='1') then

if (op='1'and vect


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Fig. . Interconnection of cGA's components.


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To evaluate our cGA we conducted some simulation tests on a Quartus II of Altera,

which is a software tool for analysis and synthesis of HDL designs. We accomplishedthe simulation using a Cyclone II EP2C70F896C6 with a clock of 50 MHz obtaining

the results shown on Table 1. The selected problem for the simulations was the max-

one, which consists in maximize the number of ones of a bitstring, this implies a

simple objective function, which is not costly.

Furthermore, we accomplished software tests on a PC with 3 GB of RAM and

Core 2 Duo processor to 1.80 GHz. The cGA was programmed of the same manner

than in VHDL, but on a sequential way on the language C#. The obtained results are

shown in Table 2.

The Table 3 shows the features of a synthesized Random Number Generator

component.

It is important to note that the generation of random numbers can be costly

according to the algorithm that we used. For our case, this component occupies many

Table 1. Simulation results

Max-One Simulation Results

8-bits

Run time: 40.28sIterations: 335

Combinational functions: 18796/68416Dedicated logic registers: 826/68416

Embedded Multiplier 9-bits elements: 192/300


12-bitsCombinational functions: 28149/68416

Dedicated logic registers: 1214/68416Embedded Multiplier 9-bits elements: 288/300

Table 2. Results in software


8-bits

Run time: 1.4996 sIterations: 335

12-bitsRun time: 2.1840s

Iterations: 345


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element

te FPGA (embedded multi liers), since we required two R

G

components for each PVs bit, which allows paralleli ing this part ofthe algorithm.

One way of decreasing the usage of the FPGA's resources for the component

R

G, is using a Cellular Automaton based Pseudo-Random Number Generator

(CAPRNG). The CAPRNGs can be from any length (no necessarily 32 bits), thatis,we can have sequences of 2

n-1 elements (being n the number of bits ofCAPRNG);

only we need a memory cell (a D-flip-flop synchronous with set and clear) and its

correspondent state rule (a combinational function) for each bit. These generators we

allow emulating populations of 2n-1 individuals (being n the number of bits of

CAPRNG), this way we allow achieving a reduction of bits in the generator and

probability vector. The CAPR NG design for 6 bits (emulating a population of 62

individuals) is shown in Figure 6.

Fi

j 6j CAPRNG of 6 bits, Cellk l

and Cell150.

In Figure 6 we can notice thatCAPRNG of 6 bits is composed of cells containing

the rule 90 or 150 (Cell90 and Cell150 respectively). The rule 90 is: ac, and the

rule 150 is:abc.m

here the pin ais connecting with pin sta ofthe left cell, pin

bis connecting with pin sta ofthe same cell and pin cis connecting with pin sta ofthe

right cell. In [12] it show how design CAPRNGs from 4 to 28 bits oflength.

In order for use the CAPRNG of Figure 6, the Probability Vector should reduce to

6 bits and we should modify the conditions of PVU componentto vect< n o (max) and

vect>

(min), the step sie will be of

. The PV will be initiali

ed to 32 (thatis the

a

c

clear

clk

set

Sta

0

a

b

c

clear

clk

set

Sta

a

c

clear

clk

set

Sta

a

b

c

clear

clk

set

Sta

a

c

clear

clk

set

Sta

a

b

c

clear

clk

set

Sta0

Cell90:cell_01

Cell150:cell_02Cell90:cell_03

Cell150:cell_04Cell90:cell_05

clk

PRNG[5..0]

set[5..0]

clear[5..0]

Cell150:cell_06

clear

clk

d

set

q

clk

a

b

c

set

clear

Sta

FF_D:Flipflop

funcclear

clk

d

set

q

func

clk

a

c

set

clear

Sta

FF_D:Flipflop

T

l

RNG Component

Component Data Synthesis

Random NumberGenerator



Cell150 Cell90

Cell150Cell90 Cell150

Cell90 Cell150

Cell90


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median element of the interval that can be generated, that is, is the probability of 0.5

ofPV). When we synthesizing the CAPRNG of 6 bits, this consuming resourcesshown in Table 4.

The simulation results of cGA with CAPRNGs of 6 bits are shown in Table 5.

Table

. Simulation results


8-bits

Run time: 41.86s

Iterations: 348




12-bitsCombinational functions: 703/68416Dedicated logic registers: 314/68416


The results of cGA in software with CAPRNGs of 6 -bits are shown in Table 6.

Table 4. CAPRNG Component of 6 bits

Component Data Synthesis

CellularAutomaton basedPseudo-Random

NumberGenerator

Combinational functions: 24/68416Dedicated logic registers: 6 /68416


Table

. Results in software


8-bits


12-bitsRun time: 2.3088041 s

Iterations: 358


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6 Conclusions and future work

The Compact Genetic Algorithms (cGA) are a viable option to compute global

numerical optimization. Their main feature is that they need only very few

computational resources when compared against the classic Genetic Algorithms. For

this reason and because their inherent parallelism, the cGA are especially well suited

to be implemented in a hardware architecture.

In this work we presented some experiments implementing a cGA on hardware

and software platforms. As it was expected, the hardware version obtained the

quickest results.

Meanwhile in the hardware version the results were obtained in only few

microseconds, for the software version, they required several seconds. This feature

makes the cGA especially attractive to be used in real time processing applications.

As a future work, we are planning to implement a fitness function design capable

of handling floating point numbers.

7 Acknowledgment

The authors thank the support of the Mexican Government (CONAC

T, SNI,

SIP-IPN, COFAA-IPN, and PIFI-IPN), also we appreciate the support of Vctor

Maruri and Altera Corporation for the donation of DE2-70 kit and Quartus II

academic licenses.

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