PAGE 01 INDEX (THIS PAGE) PAGE 02 PLATFORM FLASH …...Design by: R.Isocrate EDA-02264-V4-0...
31
PAGE 11 1MX36 DUAL PORT RAM PAGE 10 FPGA VCCAUX, VCCINT PAGE 09 FPGA POWER GND PAGE 08 FPGA MGT POWER VCC, VTT PAGE 05 FPGA GTX MGT100, MGT101, MGT102, MGT103 PAGE 04 FPGA BANK 32, BANK 33, BANK 34, BANK 35 PAGE 03 FPGA BANK 22, BANK 23, BANK 24, BANK 25 PAGE 02 PLATFORM FLASH AND FPGA CONFIGURATION PAGE 01 INDEX (THIS PAGE) PAGE 30 ANTI-RESONANCE COMPENSATION CAPACITORS 1/2 PAGE 29 LINEAR LDO P1V8, VREF, SM PAGE 28 DC-DC CONVERTER 5-1.0 (MGTAVCC) AND 5-1.2 (MGTAVTT) PAGE 27 DC-DC CONVERTER 5-1.5 (VCCDPRAM) AND 5-3.3(P3V3) PAGE 26 DC-DC CONVERTER 5-2.5 (VCCAUX) AND 5-2.5 (P2V5) PAGE 25 INPUT POWER CONNECTOR AND 12-1 DC-DC CONVERTER PAGE 24 POWER SUPPLY SYSTEM CONTROLLERS PAGE 23 I2C SYSTEM MONITOR BUS. TEMPERATURE SENSORS PAGE 22 I2C CONTROL BUS, I/O EXPANDERS AND LED DRIVER PAGE 21 DUAL TDC AND P3V3 TO P2V5 LOGIC TRANSLATORS PAGE 20 LOCAL JTAG CONNECTOR, GENERAL PURPOSE DIP SW PAGE 19 TRANSCEIVERS ADD-ON CONNECTORS PART 2/2 PAGE 18 TRANSCEIVERS ADD-ON CONNECTORS PART 1/2 PAGE 17 PCI EXPRESS FINGER CONNECTOR PAGE 16 PCI EXPRESS CLOCK 4X4 CROSSBAR PAGE 15 GTX CLOCK 4X4 CROSSBAR, ADC CLOCK 2X2 CROSSBAR PAGE 14 GTX CLOCK 2 TO 12 FANOUT PAGE 13 DELAYED CLOCK 2 TO 8 FANOUT PAGE 12 CLOCK CONDITIONER AND DELAY LINES PAGE 07 FPGA GTX MGT112, MGT113, MGT114, MGT115 PAGE 06 FPGA GTX MGT104, MGT105, MGT110, MGT111 PCI EXPRESS PRE PROCESSING CARD PAGE 31 ANTI-RESONANCE COMPENSATION CAPACITORS 2/2 LAST_MODIFIED=Fri May 27 10:34:17 2011 1/31 Project file:pcieppc.cpm 1/31 Design by: R.Isocrate EDA-02264-V4-0 MODULE:pcieppc PROJECT:GGP PCB by: PV DATE: 24/05/2017 SYSTEM: 16.03 Project: 1211 GENEVA 23 SWITZERLAND E E A A B C C 2 2 3 3 4 5 6 6 7 7 8 8 D 1 B D 5 1 Sheet: Module: European Organization for Nuclear Research 4 TS/DEM
Transcript of PAGE 01 INDEX (THIS PAGE) PAGE 02 PLATFORM FLASH …...Design by: R.Isocrate EDA-02264-V4-0...
PAGE 11 1MX36 DUAL PORT RAMPAGE 10 FPGA VCCAUX, VCCINTPAGE 09 FPGA POWER GNDPAGE 08 FPGA MGT POWER VCC, VTT
PAGE 05 FPGA GTX MGT100, MGT101, MGT102, MGT103PAGE 04 FPGA BANK 32, BANK 33, BANK 34, BANK 35PAGE 03 FPGA BANK 22, BANK 23, BANK 24, BANK 25PAGE 02 PLATFORM FLASH AND FPGA CONFIGURATIONPAGE 01 INDEX (THIS PAGE)
PAGE 30 ANTI-RESONANCE COMPENSATION CAPACITORS 1/2PAGE 29 LINEAR LDO P1V8, VREF, SMPAGE 28 DC-DC CONVERTER 5-1.0 (MGTAVCC) AND 5-1.2 (MGTAVTT)PAGE 27 DC-DC CONVERTER 5-1.5 (VCCDPRAM) AND 5-3.3(P3V3)PAGE 26 DC-DC CONVERTER 5-2.5 (VCCAUX) AND 5-2.5 (P2V5)PAGE 25 INPUT POWER CONNECTOR AND 12-1 DC-DC CONVERTERPAGE 24 POWER SUPPLY SYSTEM CONTROLLERSPAGE 23 I2C SYSTEM MONITOR BUS. TEMPERATURE SENSORSPAGE 22 I2C CONTROL BUS, I/O EXPANDERS AND LED DRIVERPAGE 21 DUAL TDC AND P3V3 TO P2V5 LOGIC TRANSLATORSPAGE 20 LOCAL JTAG CONNECTOR, GENERAL PURPOSE DIP SWPAGE 19 TRANSCEIVERS ADD-ON CONNECTORS PART 2/2PAGE 18 TRANSCEIVERS ADD-ON CONNECTORS PART 1/2PAGE 17 PCI EXPRESS FINGER CONNECTORPAGE 16 PCI EXPRESS CLOCK 4X4 CROSSBARPAGE 15 GTX CLOCK 4X4 CROSSBAR, ADC CLOCK 2X2 CROSSBARPAGE 14 GTX CLOCK 2 TO 12 FANOUTPAGE 13 DELAYED CLOCK 2 TO 8 FANOUTPAGE 12 CLOCK CONDITIONER AND DELAY LINES
PAGE 07 FPGA GTX MGT112, MGT113, MGT114, MGT115PAGE 06 FPGA GTX MGT104, MGT105, MGT110, MGT111
PCI EXPRESS PRE PROCESSING CARD
PAGE 31 ANTI-RESONANCE COMPENSATION CAPACITORS 2/2
LAST_MODIFIED=Fri May 27 10:34:17 20111/31
Project file:pcieppc.cpm
1/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
MODE[2..0]
PAGE 02 PLATFORM FLASH AND FPGA CONFIGURATION
101 ---> JTAG110 ---> SELECT_MAP(DEFAULT)
LAST_MODIFIED=Tue May 30 11:15:35 20172/31
Project file:pcieppc.cpm
2/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
1.0K
330
BSS138N1206_TC164
1%4.7k
XCF128XFTG64C
4.7k
R
HSMF-C114
B
G
0R0
150
GND=DGND;VCC=P2V5
40MHz
S1614B-40.0000
100 100
100nF
100nF
100NF
10V
0R0
0R0
4.7K
4.7K
100NF
100NF
4.7K
4.7K
4.7K
MOUNTED=NO
0R0
GSD
FTG64C
0R0
GND_TESTMON
R42R40R221R249R257R223R222R258R224
R248R256R251R244R246R255R247R41R254R243R250R245R252R253
LD1
QZ4
T1
R210
R48
C120
C149
TP1
R242
R241
RN6
R47
R39
RN5
ST11R163
ST10R162
ST9R161
C148
R203
R200
R215
R201R202
C515
C467
IC46IC16
FLASH_D0
FLASH_A18FLASH_A19FLASH_A20
FPGA_TDOFPGA_TMSFPGA_TCKFPGA_TDI
FOE_BFCS_B
FLASH_A8FLASH_A9
FLASH_D9FLASH_D8FLASH_D7FLASH_D6
FLASH_A1FLASH_A0
INIT_B
MODE_0MODE_1MODE_2
PROGRAM_BFPGA_DONE
TSTM_VFS
L#WR_PRTCT
FLASH_A22FLASH_A21
FLASH_A19
CCLK
TSTM_VP0
FLASH_A11FLASH_A12
FLASH_A3
FLASH_A18
FLASH_A20
FLASH_A10FLASH_A11
FLASH_A7FLASH_A8FLASH_A9
FLASH_A14FLASH_A15
FLASH_A5FLASH_A6
FLASH_A12
FLASH_A16
FLASH_A4
FLASH_A7
FLASH_A10
FLASH_A2
INIT_B
REM_INIT
CCLK
FLASH_D13
FLASH_D5
FLASH_D1FLASH_D2
FLASH_D11FLASH_D10
INIT_BCCLK
FPGA_DXNFPGA_DXP
FPGA_TDOFLASH_A6
FLASH_A14
FLASH_A16
FLASH_A21FLASH_A22
PROGRAM_B
FWE_B
FLASH_A17
INIT_B
FLASH_D12
FLASH_D14
FLASH_A2
FLASH_A0FLASH_A1
FLASH_A3
FLASH_A13
FPGA_DONE
MODE_2
FPGA_TCKFPGA_TDI
FPGA_TMS
NC
FLASH_A17
FLASH_A15
FLASH_A13
TSTM_VFS
TSTM_VN0
FLASH_D3FLASH_D4
FLASH_D15
TSTM_VREFPTSTM_VN0TSTM_VP0
MODE_1MODE_0
TSTM_AVDD
FLASH_A4FLASH_A5
4
3
2
1
31
8
7
6
5
1
2
3
4
161514131211109
1 2 3 4 5 6 7 8
G2
G8
H4
A4
G4
D4
B8
H1F1
F8B4
E7G7H5F5F4F3E3E1H7G6G5E5E4G3E2F2
G1A8C8C7B7A7D8D7C5B5A5C4D3C3B3A3C2A2D2D1C1B1A1
V18U17
U18V17
AE25
N10AC10
P10
AD10
AA10AE10AB10
AA25P25
L25M24M25
L10
M10 W18W17
AD25
M11
R10AB25AC24
T17T18
DGND
DGND
DGNDP1V8
DGND
P2V5
P2V5
P2V5
P2V5P2V5
P1V8
AGND
P2V5
A<22>
E*G*
VDD<1-0>VDDQ
VPP
READY_WAIT
K
WP*RP*
L*
W*
A<21>A<20>A<19>A<18>A<17>A<16>A<15>A<14>A<13>A<12>A<11>A<10>A<9>A<8>A<7>A<6>A<5>A<4>A<3>A<2>A<1>A<0>
DQ<15>DQ<14>DQ<13>DQ<12>DQ<11>DQ<10>DQ<9>DQ<8>DQ<7>DQ<6>DQ<5>DQ<4>DQ<3>DQ<2>DQ<1>DQ<0>
VSSQVSS<1-0>
DGND
PAD2
PAD2
PAD2
DGND
P2V5
DGNDDGNDDGND
P2V5
DGND
DGND
P2V5
DGND
P2V5
DGND
P2V5
P2V5
DGND
EN/D OUT
DGND
1/28BANK 0XC6VHX380TFF1154
TDO_0
VCCO_0_AC10VCCO_0_N10
DXP_0DXN_0
DOUT_BUSY_0
VREFN_0VREFP_0VN_0VP_0VFS_0AVDD_0AVSS_0
M0_0M1_0M2_0
TDI_0TCK_0TMS_0
CSI_B_0DIN_0
PROGRAM_B_0
INIT_B_0DONE_0
CCLK_0
RDWR_B_0
VBATT_0
HSWAPEN_0
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 03 FPGA BANK 22, BANK 23, BANK 24, BANK 25LAST_MODIFIED=Tue May 30 11:16:24 2017
3/31
Project file:pcieppc.cpm
3/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
100NF
10V
VREF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
10V
10V
100NF
100NF
VREF
10V
100NF
R204
R205
R219
R220
R207
R206
R199
R198
C437
C435
C438
C434
C440
C441
C439
C458
C457
C436
C407
C401
C396
C397
C380
C399
C400
C398
C445
C428
IC16IC16IC16IC16
DPRAM_DATA_R33
DPRAM_DATA_R18DPRAM_ADDR_L6DPRAM_ADDR_R5DPRAM_DATA_R32DPRAM_DATA_R26DPRAM_DATA_R29DPRAM_READY_LDPRAM_ADDR_R7DPRAM_DATA_R20DPRAM_DATA_R19
DPRAM_ADDR_L8DPRAM_DATA_R25DPRAM_DATA_R23VRP_22VRN_22DPRAM_WRP_RDPRAM_READY_RDPRAM_DATA_R21DPRAM_ADDR_L7DPRAM_DATA_R28DPRAM_CQ_R1_PDPRAM_DATA_R22DPRAM_RET_RDPRAM_ADS_LDPRAM_ADDR_L9DPRAM_ADDR_L5DPRAM_ADS_RDPRAM_ADDR_R9DPRAM_ADDR_R8
DPRAM_WRP_LDPRAM_DATA_R31DPRAM_DATA_R35DPRAM_DATA_R24DPRAM_DATA_R27DPRAM_ADDR_R6DPRAM_DATA_R34DPRAM_DATA_R30
CLK_FPGA_RAW_PCLK_FPGA_RAW_N
FLASH_D1
FWE_B
FPGA_TDC_SSNCLK_FPGA_BASECLK_FBK_ADC_NCLK_FBK_ADC_P
FPGA_TDC_STARTVRP_25VRN_25
FPGA_TDC_CLKREFFPGA_PWUP_RESETFPGA_TDC_SIFPGA_TDC_SCK
CLK_LINK_NFPGA_TDC_EN_STOP2
CLK_LINK_PFPGA_TDC_STOP2
FPGA_PCIE_PERSTFPGA_PCIE_WAKE
BOOT_FLASH_SCKBOOT_FLASH_RESETLINK_OUT_1_PLINK_OUT_1_NLINK_IN_1_PLINK_IN_1_NLINK_IN_0_PLINK_IN_0_NLINK_OUT_0_PLINK_OUT_0_N
ADDON_CODE1NC
NC
ADDON_CODE0I2C_RST
FPGA_TDC_STOP1
FPGA_CTL_SDA
BOOT_FLASH_SO
BOOT_FLASH_SIFPGA_PMB_SDAFPGA_PMB_SCL
FLASH_D9FLASH_D8FLASH_D7FLASH_D6FLASH_D5FLASH_D4
CLK_FPGA_DLD_PCLK_FPGA_DLD_N
DPRAM_ADDR_L4DPRAM_DATA_L21DPRAM_DATA_L18DPRAM_ADDR_R0
DPRAM_DATA_L33
DPRAM_ADDR_R2DPRAM_DATA_L20DPRAM_DATA_L19
DPRAM_DATA_L22
DPRAM_ADDR_L0
VRN_23VRP_23
DPRAM_CQ_L1_P
FPGA_PLL_UWIRE_CLKFPGA_TDC_INTNFPGA_TDC_SO
VRN_24VRP_22VRN_22
FPGA_TDC_RESET
FPGA_TDC_EN_START
FPGA_AO_PMB_ALERT
FPGA_TDC_EN_STOP1
DPRAM_DATA_L28DPRAM_DATA_L27
DPRAM_RET_LDPRAM_ADDR_L2DPRAM_DATA_L31DPRAM_DATA_L35DPRAM_DATA_L24DPRAM_DATA_L30DPRAM_DATA_L29DPRAM_DATA_L32
DPRAM_DATA_L26DPRAM_BUSY_RDPRAM_DATA_L34
DPRAM_CLK_RDPRAM_CNTINT_R
DPRAM_ADDR_R3DPRAM_ADDR_R4
DPRAM_DATA_L25DPRAM_DATA_L23DPRAM_ADDR_R1DPRAM_CNTINT_L
DPRAM_ADDR_L1
DPRAM_ADDR_L3DPRAM_CLK_LDPRAM_BUSY_L
VRP_24VRP_23VRN_23
CLK_FBK_DLD_PCLK_FBK_DLD_NCLK_FBK_GTX_PCLK_FBK_GTX_NFLASH_D15FLASH_D14FLASH_D13FLASH_D12FLASH_D11FLASH_D10
FPGA_AO_PMB_SDAFLASH_D3FLASH_D2
FLASH_D0FCS_BFOE_B
NCNC
VRN_24VRP_24L#FPGA_AO_PMB_SCLFPGA_CTL_SCL
VRP_25VRN_25
1 1 12
K19G18F21C20B23
A18A19
K20J20
D18C18
M20L20
F18E18
M19L19
J18H18
E20D20
L18K18
B20B21
B22A22
B19A20
F22E22
D19C19
C21C22
G19F19
E21D21
J19H19
H21G21
G20F20
M23J22H25E24A26
L22K22
D25D26
F23E23
C26C27
D23C23
B24A25
H22G22
B25B26
K21J21
B27A27
L24K25
A23A24
J24J25
D24C24
H24G24
L23K23
G25F25
J23H23
F24E25
M21M22
AP27
AM23
AH25
AF21
AE24
AE22
AF22
AK25
AL25
AK23
AL23
AF25
AG25
AH23
AJ23
AM26
AN27
AD23
AE23
AN26
AP26
AC23
AD24
AM24
AN24
AC21
AC22
AD21
AE21
AF23
AF24
AN23
AP23
AG24
AH24
AP24
AP25
AJ24
AJ25
AG22
AH22
AL24
AM25
AN28
AP28
AN20AK19AJ22AG18AC20
AD20AE20
AG21AH21
AF19AG19
AJ21AK21
AH19AJ19
AC18AC19
AL19AM19
AM22AN22
AN18AP18
AM21AN21
AN19AP19
AD18AD19
AP20AP21
AE18AF18
AF20AG20
AH18AJ18
AJ20AK20
AK18AL18
AL20AM20
AK22AL22
DGND DGND DGNDDGND DGND DGND DGND DGNDDGND DGND DGND DGND DGND
5/28BANK 25XC6VHX380TFF1154
VCCO_25_K19VCCO_25_G18VCCO_25_F21VCCO_25_C20VCCO_25_B23
IO_L19N_GC_25IO_L19P_GC_25IO_L18N_GC_25IO_L18P_GC_25IO_L17N_25IO_L17P_25IO_L16N_VRP_25IO_L16P_VRN_25IO_L15N_SM15N_25IO_L15P_SM15P_25IO_L14N_VREF_25IO_L14P_25IO_L13N_SM14N_25IO_L13P_SM14P_25IO_L12N_SM13N_25IO_L12P_SM13P_25IO_L11N_SRCC_25IO_L11P_SRCC_25IO_L10N_MRCC_25IO_L10P_MRCC_25IO_L9N_MRCC_25IO_L9P_MRCC_25IO_L8N_SRCC_25IO_L8P_SRCC_25IO_L7N_SM12N_25IO_L7P_SM12P_25IO_L6N_SM11N_25IO_L6P_SM11P_25IO_L5N_SM10N_25IO_L5P_SM10P_25IO_L4N_VREF_25IO_L4P_25IO_L3N_SM9N_25IO_L3P_SM9P_25IO_L2N_SM8N_25IO_L2P_SM8P_25IO_L1N_25IO_L1P_25IO_L0N_25IO_L0P_25
4/28BANK 24XC6VHX380TFF1154
VCCO_24_M23VCCO_24_J22VCCO_24_H25VCCO_24_E24VCCO_24_A26
IO_L19N_24IO_L19P_24IO_L18N_24IO_L18P_24IO_L17N_VRP_24IO_L17P_VRN_24IO_L16N_CSO_B_24IO_L16P_RS0_24IO_L15N_RS1_24IO_L15P_FWE_B_24IO_L14N_VREF_FOE_B_MOSI_24IO_L14P_FCS_B_24IO_L13N_D0_FS0_24IO_L13P_D1_FS1_24IO_L12N_D2_FS2_24IO_L12P_D3_24IO_L11N_SRCC_24IO_L11P_SRCC_24IO_L10N_MRCC_24IO_L10P_MRCC_24IO_L9N_MRCC_24IO_L9P_MRCC_24IO_L8N_SRCC_24IO_L8P_SRCC_24IO_L7N_D4_24IO_L7P_D5_24IO_L6N_D6_24IO_L6P_D7_24IO_L5N_D8_24IO_L5P_D9_24IO_L4N_VREF_D10_24IO_L4P_D11_24IO_L3N_D12_24IO_L3P_D13_24IO_L2N_D14_24IO_L2P_D15_24IO_L1N_GC_24IO_L1P_GC_24IO_L0N_GC_24IO_L0P_GC_24
DGNDDGND
3/28BANK 23XC6VHX380TFF1154
IO_L0P_23
VCCO_23_AP27VCCO_23_AM23VCCO_23_AH25VCCO_23_AF21VCCO_23_AE24
IO_L19N_23IO_L19P_23IO_L18N_23IO_L18P_23IO_L17N_23IO_L17P_23IO_L16N_23IO_L16P_23IO_L15N_23IO_L15P_23IO_L14N_VREF_23IO_L14P_23IO_L13N_23IO_L13P_23IO_L12N_VRP_23IO_L12P_VRN_23IO_L11N_SRCC_23IO_L11P_SRCC_23IO_L10N_MRCC_23IO_L10P_MRCC_23IO_L9N_MRCC_23IO_L9P_MRCC_23IO_L8N_SRCC_23IO_L8P_SRCC_23IO_L7N_23IO_L7P_23IO_L6N_23IO_L6P_23IO_L5N_23IO_L5P_23IO_L4N_VREF_23IO_L4P_23IO_L3N_23IO_L3P_23IO_L2N_23IO_L2P_23IO_L1N_23IO_L1P_23IO_L0N_23
DGND
P2V5P2V5P2V5P2V5P2V5P2V5P2V5P2V5P2V5P2V5
P2V5P2V5
P2V5P2V5
P1V5P1V5P1V5P1V5P1V5
P1V5
P1V5
P1V5P1V5P1V5P1V5
DGND
P1V5
P1V5
P1V5
DGND DGND DGND DGND DGND DGND DGND
2/28BANK 22XC6VHX380TFF1154
VCCO_22_AN20VCCO_22_AK19VCCO_22_AJ22VCCO_22_AG18VCCO_22_AC20
IO_L19N_22IO_L19P_22IO_L18N_22IO_L18P_22IO_L17N_22IO_L17P_22IO_L16N_22IO_L16P_22IO_L15N_22IO_L15P_22IO_L14N_VREF_22IO_L14P_22IO_L13N_22IO_L13P_22IO_L12N_VRP_22IO_L12P_VRN_22IO_L11N_SRCC_22IO_L11P_SRCC_22IO_L10N_MRCC_22IO_L10P_MRCC_22IO_L9N_MRCC_22IO_L9P_MRCC_22IO_L8N_SRCC_22IO_L8P_SRCC_22IO_L7N_22IO_L7P_22IO_L6N_22IO_L6P_22IO_L5N_22IO_L5P_22IO_L4N_VREF_22IO_L4P_22IO_L3N_22IO_L3P_22IO_L2N_22IO_L2P_22IO_L1N_22IO_L1P_22IO_L0N_22IO_L0P_22
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 04 FPGA BANK 32, BANK 33, BANK 34, BANK 35LAST_MODIFIED=Tue May 30 11:17:06 2017
4/31
Project file:pcieppc.cpm
4/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
VREF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
100NF
10V
100NF
10V
100NF
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
100NF
10V
10V
100NF
10V
VREF
R212
R211
R217
R216
R214
R213
R208
R209
C450
C444
C443
IC16
C463
C442
C466
C503
C464
C465
IC16
C468
C516
C517
C500
C499
IC16
C487
C462
C461
C501
C498
C460
IC16
FAN_SPEED_INFPGA_SYNC_PLL
SM_IN_0_PSM_IN_0_NSM_IN_1_PSM_IN_1_NFPGA_PLL_UWIRE_LEFPGA_PLL_UWIRE_DATASM_IN_2_PSM_IN_2_NSM_IN_3_P
FPGA_DPRAM_MRST
SYNC_OUT_0_PSYNC_OUT_0_N
SYNC_AUX_IN_P
SYNC_OUT_1_P
SYNC_AUX_OUT_PSYNC_AUX_OUT_N
SYNC_OUT_1_N
SYNC_AUX_IN_N
FPGA_PLL_LOS
FPGA_PLL_GOE
CLK_FPGA_LOC_PCLK_FPGA_LOC_NCLK_FPGA_PCI_P
CLK_FPGA_GTX_PCLK_FPGA_GTX_NFLASH_A3FLASH_A2
FPGA_AO_CTL_SDAFPGA_AO_CTL_SCL
CLK_FPGA_PCI_N
FLASH_A1FLASH_A0REM_INIT
FLASH_A22
CLK_FPGA_ADC_NCLK_FPGA_ADC_P
REM_TCK
FLASH_A14FLASH_A13FLASH_A12FLASH_A11FLASH_A10FLASH_A9FLASH_A8FLASH_A7FLASH_A6FLASH_A5FLASH_A4
DPRAM_DATA_R6
DPRAM_OE_LDPRAM_DATA_R0DPRAM_DATA_R17
DPRAM_RW_L
DPRAM_DATA_R12DPRAM_CQ_R0_P
FLASH_A21FLASH_A20FLASH_A19
VRN_34VRN_33VRP_34VRP_33
VRN_35
DPRAM_CNTRST_R
SYNC_IN_0_N
VRP_35VRN_35SM_IN_7_NSM_IN_7_P
SM_IN_6_NSM_IN_6_PSM_IN_5_NSM_IN_5_PFPGA_PLL_LD
SYNC_IN_1_NSYNC_IN_1_P
SYNC_IN_0_PSM_IN_4_NSM_IN_4_PSM_IN_3_N
DPRAM_DATA_L0DPRAM_ADDR_R11
DPRAM_DATA_L7DPRAM_DATA_L11DPRAM_DATA_L12DPRAM_CNTMSK_R
DPRAM_ADDR_L17DPRAM_ADDR_L19
DPRAM_DATA_R1DPRAM_DATA_R2
DPRAM_DATA_L4
VRN_32
DPRAM_ADDR_R10DPRAM_DATA_L15 DPRAM_DATA_R9
VRN_32DPRAM_DATA_L2
DPRAM_DATA_L6DPRAM_ADDR_R14
DPRAM_CNTEN_LDPRAM_INT_LDPRAM_ADDR_L10DPRAM_CNTMSK_L
DPRAM_CNTEN_RDPRAM_DATA_L16
DPRAM_CNTRST_LDPRAM_ADDR_L12
DPRAM_DATA_R10
VRN_34
DPRAM_DATA_R5DPRAM_DATA_R4
DPRAM_DATA_R3
DPRAM_DATA_L17DPRAM_DATA_L13
DPRAM_DATA_L8DPRAM_ADDR_R12DPRAM_ADDR_L11
DPRAM_DATA_L14DPRAM_DATA_L10DPRAM_ADDR_L13VRP_32
DPRAM_INT_RDPRAM_ADDR_R13DPRAM_DATA_L9
DPRAM_FTSEL_L
DPRAM_ADDR_L15DPRAM_DATA_R8
DPRAM_DATA_R15
DPRAM_CQ_L0_P
DPRAM_DATA_L5DPRAM_DATA_L3
DPRAM_DATA_L1
DPRAM_ADDR_L14
VRP_35VRP_32
DPRAM_RW_R
VRP_33
DPRAM_DATA_R13DPRAM_DATA_R11
DPRAM_ADDR_R19
DPRAM_ADDR_R16
VRN_33
DPRAM_ADDR_R15
DPRAM_ADDR_R17
DPRAM_ADDR_L18
DPRAM_OE_R
REM_TDIREM_TDOREM_TMS
FLASH_A15
FLASH_A18FLASH_A17FLASH_A16
VRP_34
DPRAM_ADDR_L16DPRAM_FTSEL_RDPRAM_DATA_R14DPRAM_DATA_R16DPRAM_ADDR_R18DPRAM_DATA_R7
2
AP17AM13AL16AH15AD17
AC17AC16
AL15AL14
AG16AH16
AK13AL13
AJ16AK16
AM15AN14
AM16AN16
AH14AJ14
AP16AP15
AM17AN17
AP14AP13
AE17AF17
AM14AN13
AG17AH17
AJ15AK15
AD16AE16
AF15AG15
AK17AL17
AD15AE15
AF14AG14
AP7AN10
AJ12AF11AE14
AP11AP10
AG11AH11
AM12AN12
AF10AG10
AK12AL12
AN8AN7
AG12AH12
AE12AF12
AC12AC11
AM11AN11
AP9AP8
AC14AD14
AM9AN9
AH13AJ13
AL10AM10
AE13AF13
AK11AK10
AC13AD13
AJ11AJ10
AD11AE11
M13J12F11C10B13
J13H13
F10E10
L13K13
C9B9
B12A12
C12B11
J14H14
A9A8
M14L14
D9C8
K10J10
H12G12
M12L12
F12E12
K12K11
D11C11
J11H11
B10A10
G11G10
E11D10
L16H15E14D17A16
D16C16
E15D14
C17B16
G15F15
F17E17
B17A17
H17G17
B15A15
L17K17
C14B14
A14A13
E16D15
F13E13
H16G16
D13C13
M15L15
G14F14
K16J16
K15J15
M17M16
P1V5P1V5P1V5P1V5P1V5P1V5P1V5P1V5P1V5
P1V5
DGND
P1V5
P1V5P1V5
DGND DGND
DGND
DGND
6/28BANK 32XC6VHX380TFF1154
VCCO_32_AP17VCCO_32_AM13VCCO_32_AL16VCCO_32_AH15VCCO_32_AD17
IO_L19N_32IO_L19P_32IO_L18N_32IO_L18P_32IO_L17N_32IO_L17P_32IO_L16N_32IO_L16P_32IO_L15N_32IO_L15P_32IO_L14N_VREF_32IO_L14P_32IO_L13N_32IO_L13P_32IO_L12N_VRP_32IO_L12P_VRN_32IO_L11N_SRCC_32IO_L11P_SRCC_32IO_L10N_MRCC_32IO_L10P_MRCC_32IO_L9N_MRCC_32IO_L9P_MRCC_32IO_L8N_SRCC_32IO_L8P_SRCC_32IO_L7N_32IO_L7P_32IO_L6N_32IO_L6P_32IO_L5N_32IO_L5P_32IO_L4N_VREF_32IO_L4P_32IO_L3N_32IO_L3P_32IO_L2N_32IO_L2P_32IO_L1N_32IO_L1P_32IO_L0N_32IO_L0P_32
DGNDDGND DGND DGND DGND
DGND
DGND DGND
7/28BANK 33XC6VHX380TFF1154
VCCO_33_AP7VCCO_33_AN10
VCCO_33_AJ12VCCO_33_AF11VCCO_33_AE14
IO_L19N_33IO_L19P_33IO_L18N_33IO_L18P_33IO_L17N_33IO_L17P_33IO_L16N_33IO_L16P_33IO_L15N_33IO_L15P_33IO_L14N_VREF_33IO_L14P_33IO_L13N_33IO_L13P_33IO_L12N_VRP_33IO_L12P_VRN_33IO_L11N_SRCC_33IO_L11P_SRCC_33IO_L10N_MRCC_33IO_L10P_MRCC_33IO_L9N_MRCC_33IO_L9P_MRCC_33IO_L8N_SRCC_33IO_L8P_SRCC_33IO_L7N_33IO_L7P_33IO_L6N_33IO_L6P_33IO_L5N_33IO_L5P_33IO_L4N_VREF_33IO_L4P_33IO_L3N_33IO_L3P_33IO_L2N_33IO_L2P_33IO_L1N_33IO_L1P_33IO_L0N_33IO_L0P_33
DGND DGND DGND
DGND
DGND DGND DGND
8/28BANK 34XC6VHX380TFF1154
VCCO_34_M13VCCO_34_J12VCCO_34_F11VCCO_34_C10VCCO_34_B13
IO_L19N_VRP_34IO_L19P_VRN_34IO_L18N_A16_34IO_L18P_A17_34IO_L17N_A18_34IO_L17P_A19_34IO_L16N_A20_34IO_L16P_A21_34IO_L15N_A22_34IO_L15P_A23_34IO_L14N_VREF_A24_34IO_L14P_A25_34IO_L13N_A00_D16_34IO_L13P_A01_D17_34IO_L12N_A02_D18_34IO_L12P_A03_D19_34IO_L11N_SRCC_34IO_L11P_SRCC_34IO_L10N_MRCC_34IO_L10P_MRCC_34IO_L9N_MRCC_34IO_L9P_MRCC_34IO_L8N_SRCC_34IO_L8P_SRCC_34IO_L7N_A04_D20_34IO_L7P_A05_D21_34IO_L6N_A06_D22_34IO_L6P_A07_D23_34IO_L5N_A08_D24_34IO_L5P_A09_D25_34IO_L4N_VREF_A10_D26_34IO_L4P_A11_D27_34IO_L3N_A12_D28_34IO_L3P_A13_D29_34IO_L2N_A14_D30_34IO_L2P_A15_D31_34IO_L1N_GC_34IO_L1P_GC_34IO_L0N_GC_34IO_L0P_GC_34
DGND DGND DGND
DGND
P2V5 P2V5 P2V5 P2V5 P2V5P2V5P2V5P2V5P2V5P2V5
P2V5 P2V5
P2V5P2V5
P1V5
9/28BANK 35XC6VHX380TFF1154
VCCO_35_L16VCCO_35_H15VCCO_35_E14VCCO_35_D17VCCO_35_A16
IO_L19N_GC_35IO_L19P_GC_35IO_L18N_GC_35IO_L18P_GC_35IO_L17N_35IO_L17P_35IO_L16N_VRP_35IO_L16P_VRN_35IO_L15N_SM7N_35IO_L15P_SM7P_35IO_L14N_VREF_35IO_L14P_35IO_L13N_SM6N_35IO_L13P_SM6P_35IO_L12N_SM5N_35IO_L12P_SM5P_35IO_L11N_SRCC_35IO_L11P_SRCC_35IO_L10N_MRCC_35IO_L10P_MRCC_35IO_L9N_MRCC_35IO_L9P_MRCC_35IO_L8N_SRCC_35IO_L8P_SRCC_35IO_L7N_SM4N_35IO_L7P_SM4P_35IO_L6N_SM3N_35IO_L6P_SM3P_35IO_L5N_SM2N_35IO_L5P_SM2P_35IO_L4N_VREF_35IO_L4P_35IO_L3N_SM1N_35IO_L3P_SM1P_35IO_L2N_SM0N_35IO_L2P_SM0P_35IO_L1N_35IO_L1P_35IO_L0N_35IO_L0P_35
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 05 FPGA GTX MGT100, MGT101, MGT102, MGT103LAST_MODIFIED=Tue May 30 11:11:53 2017
5/31
PROJECT:GGPProject file:pcieppc.cpm
5/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
10V100NF
100NF
100NF
10V
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
C179
C178
C181
C180
C183
C182
C203
IC16
C189
C188
C197
C196
IC16
C193
C192
C199
C198
C195
C194
C201
C200
C187
C186
C202
IC16
C185
C184
C191
C190IC16
GTX100_42_TX_NGTX100_42_TX_P
GTX103_30_RX_NGTX103_30_RX_P
GTX102_34_RX_NGTX102_34_RX_P
CLKGTX_110_P
GTX100_40_RX_NGTX100_40_RX_P
CLKDLD_110_P
CLKGTX_110_N
GTX100_42_RX_PGTX100_42_RX_N
CLKDLD_110_N
GTX101_38_RX_PGTX101_38_RX_N
GTX100_41_RX_P
GTX104_26_RX_NGTX104_26_RX_P
GTX102_33_TX_NGTX102_33_TX_P
GTX102_33_RX_NGTX102_33_RX_P
GTX101_38_TX_NGTX101_38_TX_P
GTX104_25_RX_NGTX104_25_RX_P
GTX102_32_RX_PGTX102_32_RX_N
GTX102_32_TX_PGTX102_32_TX_N
GTX101_39_TX_NGTX101_39_TX_P
GTX101_37_TX_NGTX101_37_TX_P
GTX104_24_TX_NGTX104_24_TX_P
GTX101_39_RX_PGTX101_39_RX_N
GTX101_37_RX_PGTX101_37_RX_N
GTX104_24_RX_PGTX104_24_RX_N
GTX101_36_RX_PGTX101_36_RX_N
GTX100_40_TX_PGTX100_40_TX_N
GTX101_36_TX_NGTX101_36_TX_P
GTX100_41_TX_N
GTX100_43_TX_PGTX100_43_TX_N
GTX100_41_TX_P
CLKDLD_102_NCLKDLD_102_P
CLKGTX_102_NCLKGTX_102_P
GTX104_25_TX_PGTX104_25_TX_N
CLKGTX_103_PCLKGTX_103_N
GTX114_12_RX_PGTX114_12_RX_N
GTX114_12_TX_PGTX114_12_TX_N
CLKDLD_101_NCLKDLD_101_P
CLKGTX_101_NCLKGTX_101_P
GTX100_41_RX_N
GTX100_43_RX_PGTX100_43_RX_N
AF34
AH34
AJ32
AK34
AF33
AH33
AJ31
AK33
AB30
AC32
AD30
AE32
AB29
AC31
AD29
AE31
AC27AC28
AE27AE28
AL32
AM34
AN32
AP34
AL31
AM33
AN31
AP33
AF30
AG32
AH30
AK30
AF29
AG31
AH29
AK29
AG27AG28
AJ27AJ28
K34
M34
P34
T34
K33
M33
P33
T33
P30
T30
R32
U32
P29
T29
R31
U31
R27R28
U27U28
V34
Y34
AB34
AD34
V33
Y33
AB33
AD33
V30
W32
Y30
AA32
V29
W31
Y29
AA31
W27W28
AA27AA28
DGND
XC6VHX380TFF1154MGT 101 11/28
MGTREFCLK1N_101MGTREFCLK1P_101
MGTREFCLK0N_101MGTREFCLK0P_101
MGTTXN3_101MGTTXP3_101
MGTTXN2_101MGTTXP2_101
MGTTXN1_101MGTTXP1_101
MGTTXN0_101MGTTXP0_101
MGTRXN3_101MGTRXP3_101
MGTRXN2_101MGTRXP2_101
MGTRXN1_101MGTRXP1_101
MGTRXN0_101MGTRXP0_101
10/28MGT 100XC6VHX380TFF1154
MGTREFCLK1N_100MGTREFCLK1P_100
MGTREFCLK0N_100MGTREFCLK0P_100
MGTTXN3_100MGTTXP3_100
MGTTXN2_100MGTTXP2_100
MGTTXN1_100MGTTXP1_100
MGTTXN0_100MGTTXP0_100
MGTRXN3_100MGTRXP3_100
MGTRXN2_100MGTRXP2_100
MGTRXN1_100MGTRXP1_100
MGTRXN0_100MGTRXP0_100
12/28MGT 102XC6VHX380TFF1154
MGTREFCLK1N_102MGTREFCLK1P_102
MGTREFCLK0N_102MGTREFCLK0P_102
MGTTXN3_102MGTTXP3_102
MGTTXN2_102MGTTXP2_102
MGTTXN1_102MGTTXP1_102
MGTTXN0_102MGTTXP0_102
MGTRXN3_102MGTRXP3_102
MGTRXN2_102MGTRXP2_102
MGTRXN1_102MGTRXP1_102
MGTRXN0_102MGTRXP0_102
13/28MGT 103XC6VHX380TFF1154
MGTTXN3_103MGTRXN3_103MGTTXP3_103MGTRXP3_103
MGTTXN2_103MGTTXP2_103MGTRXP2_103
MGTTXN1_103MGTRXN1_103MGTRXP1_103
MGTTXN0_103MGTRXN0_103MGTTXP0_103MGTRXP0_103
MGTREFCLK0N_103MGTREFCLK0P_103
MGTREFCLK1N_103MGTREFCLK1P_103
MGTTXP1_103
MGTRXN2_103
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 06 FPGA GTX MGT104, MGT105, MGT110, MGT111LAST_MODIFIED=Tue May 30 11:17:39 2017
6/31
Project file:pcieppc.cpm
6/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
MGT_AVTT
100
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
C171
C170
C175
C174
C218
C217
C220
C219
C210
C209
C212
C211
C214
C213
C216
C215
R160
IC16
IC16
C173
C172
C177
C176
IC16
IC16
GTX105_21_TX_N
GTX103_28_RX_PGTX103_28_RX_N
CLKDLD_104_NCLKDLD_104_P
CLKGTX_104_NCLKGTX_104_P
GTX104_27_RX_N
GTX113_8_TX_NGTX113_8_TX_P
GTX105_21_TX_P
GTX113_8_RX_NGTX113_8_RX_P
GTX105_21_RX_PGTX105_21_RX_N
GTX105_22_RX_PGTX105_22_RX_N
GTX105_23_RX_PGTX105_23_RX_N
CLKDLD_105_PCLKDLD_105_N
CLKGTX_105_NCLKGTX_105_P
CLKGTX_111_PCLKGTX_111_N
CLKDLD_111_PCLKDLD_111_N
GTX111_0_TX_PGTX111_0_TX_N
PCIEL0_RX_P
PCIEL3_TX_PPCIEL3_TX_N
CLKPE0_110_NCLKPE0_110_P
GTX111_1_TX_PGTX111_1_TX_N
PCIEL2_RX_N
PCIEL1_RX_PPCIEL1_RX_N
PCIEL0_RX_N
PCIEL2_TX_PPCIEL2_TX_N
PCIEL1_TX_N
PCIEL0_TX_PPCIEL0_TX_N
PCIEL1_TX_P
PCIEL2_RX_P
PCIEL3_RX_NPCIEL3_RX_P
GTX105_20_RX_NGTX105_20_RX_P GTX111_0_RX_P
GTX111_0_RX_N
GTX111_1_RX_PGTX111_1_RX_N
GTX111_2_RX_PGTX111_2_RX_N
GTX111_3_RX_PGTX111_3_RX_N
GTX105_20_TX_NGTX105_20_TX_P
GTX104_27_RX_P
GTX114_13_TX_PGTX114_13_TX_N
GTX114_13_RX_NGTX114_13_RX_P
A32
B34
C32
D34
A31
B33
C31
D33
D30
F30
H30
J32
D29
F29
H29
J31
AM30
G27G28
J27J28
AP30
E32
F34
G32
H34
E31
F33
G31
H33
K30
L32
M30
N32
K29
L31
M29
N31
L27L28
N27N28
AF1
AH1
AJ3
AK1
AF2
AH2
AJ4
AK2
AB5
AC3
AD5
AE3
AB6
AC4
AD6
AE4
AC8AC7
AE8AE7
AL3
AM1
AN3
AP1
AL4
AM2
AN4
AP2
AF5
AG3
AH5
AK5
AF6
AG4
AH6
AK6
AG8AG7
AJ8AJ7
VCC
15/28MGT 105XC6VHX380TFF1154
MGTRREF_105MGTAVTTRCAL_105
MGTREFCLK1N_105MGTREFCLK1P_105
MGTREFCLK0N_105MGTREFCLK0P_105
MGTTXN3_105MGTTXP3_105
MGTTXN2_105MGTTXP2_105
MGTTXN1_105MGTTXP1_105
MGTTXN0_105MGTTXP0_105
MGTRXN3_105MGTRXP3_105
MGTRXN2_105MGTRXP2_105
MGTRXN1_105MGTRXP1_105
MGTRXN0_105MGTRXP0_105
14/28MGT 104XC6VHX380TFF1154
MGTREFCLK1N_104MGTREFCLK1P_104
MGTREFCLK0N_104MGTREFCLK0P_104
MGTTXN3_104MGTTXP3_104
MGTTXN2_104MGTTXP2_104
MGTTXN1_104MGTTXP1_104
MGTTXN0_104MGTTXP0_104
MGTRXN3_104MGTRXP3_104
MGTRXN2_104MGTRXP2_104
MGTRXN1_104MGTRXP1_104
MGTRXN0_104MGTRXP0_104
17/28MGT 111XC6VHX380TFF1154
MGTREFCLK1N_111MGTREFCLK1P_111
MGTREFCLK0N_111MGTREFCLK0P_111
MGTTXN3_111MGTTXP3_111
MGTTXN2_111MGTTXP2_111
MGTTXN1_111MGTTXP1_111
MGTTXN0_111MGTTXP0_111
MGTRXN3_111MGTRXP3_111
MGTRXN2_111MGTRXP2_111
MGTRXN1_111MGTRXP1_111
MGTRXN0_111MGTRXP0_111
16/28MGT 110XC6VHX380TFF1154
MGTREFCLK1N_110
MGTREFCLK1P_110
MGTREFCLK0N_110
MGTREFCLK0P_110
MGTTXN3_110
MGTTXP3_110
MGTTXN2_110
MGTTXP2_110
MGTTXN1_110
MGTTXP1_110
MGTTXN0_110
MGTTXP0_110
MGTRXN3_110
MGTRXP3_110
MGTRXN2_110
MGTRXP2_110
MGTRXN1_110
MGTRXP1_110
MGTRXN0_110
MGTRXP0_110
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 07 FPGA GTX MGT112, MGT113, MGT114, MGT115LAST_MODIFIED=Tue May 30 11:18:07 2017
7/31
Project file:pcieppc.cpm
7/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
100NF
MGT_AVTT
100
100NF
R218
IC16IC16
IC16
C206
C207
IC16
GTX112_5_RX_NGTX112_5_RX_P
GTX115_17_RX_NGTX115_17_RX_P
GTX113_11_RX_NGTX113_11_RX_P
GTX114_15_RX_PGTX114_15_RX_N
CLKGTX_112_NCLKGTX_112_P
GTX103_29_RX_P
GTX103_31_RX_NGTX103_31_RX_P
GTX115_19_RX_N
CLKGTX_113_PCLKGTX_113_N
GTX113_10_RX_PGTX113_10_RX_N
GTX115_19_RX_P
GTX113_9_TX_N
GTX112_7_RX_PGTX112_7_RX_N
GTX115_18_RX_NGTX115_18_RX_P
GTX115_16_RX_NGTX115_16_RX_P
GTX102_35_RX_P
GTX112_6_RX_P
GTX102_35_RX_N
GTX112_6_RX_N
GTX112_4_RX_NGTX112_4_RX_P
GTX114_14_RX_PGTX114_14_RX_N
GTX103_29_RX_N
GTX113_9_RX_PGTX113_9_RX_N
CLKDLD_113_P
CLKDLD_114_NCLKDLD_114_P
CLKDLD_113_N
CLKGTX_115_PCLKGTX_115_N
GTX113_9_TX_P
CLKGTX_114_NCLKGTX_114_P
A3
B1
C3
D1
A4
B2
C4
D2
D5
F5
H5
J3
D6
F6
H6
J4
AM5
G8G7
J8J7
AP5
K1
M1
P1
T1
K2
M2
P2
T2
P5
T5
R3
U3
P6
T6
R4
U4
R8R7
U8U7
V1
Y1
AB1
AD1
V2
Y2
AB2
AD2
V5
W3
Y5
AA3
V6
W4
Y6
AA4
W8W7
AA8AA7
E3
F1
G3
H1
E4
F2
G4
H2
K5
L3
M5
N3
K6
L4
M6
N4
L8L7
N8N7
VCCDGND
DGND
21/28MGT 115XC6VHX380TFF1154
MGTRREF_115MGTAVTTRCAL_115
MGTREFCLK1N_115MGTREFCLK1P_115
MGTREFCLK0N_115MGTREFCLK0P_115
MGTTXN3_115MGTTXP3_115
MGTTXN2_115MGTTXP2_115
MGTTXN1_115MGTTXP1_115
MGTTXN0_115MGTTXP0_115
MGTRXN3_115MGTRXP3_115
MGTRXN2_115MGTRXP2_115
MGTRXN1_115MGTRXP1_115
MGTRXN0_115MGTRXP0_115
19/28MGT 113XC6VHX380TFF1154
MGTREFCLK1N_113MGTREFCLK1P_113
MGTREFCLK0N_113MGTREFCLK0P_113
MGTTXN3_113MGTTXP3_113
MGTTXN2_113MGTTXP2_113
MGTTXN1_113MGTTXP1_113
MGTTXN0_113MGTTXP0_113
MGTRXN3_113MGTRXP3_113
MGTRXN2_113MGTRXP2_113
MGTRXN1_113MGTRXP1_113
MGTRXN0_113MGTRXP0_113
18/28MGT 112XC6VHX380TFF1154
MGTREFCLK1N_112MGTREFCLK1P_112
MGTREFCLK0N_112MGTREFCLK0P_112
MGTTXN3_112MGTTXP3_112
MGTTXN2_112MGTTXP2_112
MGTTXN1_112MGTTXP1_112
MGTTXN0_112MGTTXP0_112
MGTRXN3_112MGTRXP3_112
MGTRXN2_112MGTRXP2_112
MGTRXN1_112MGTRXP1_112
MGTRXN0_112MGTRXP0_112
20/28MGT 114XC6VHX380TFF1154
MGTRXP0_114
MGTREFCLK1N_114MGTREFCLK1P_114
MGTREFCLK0N_114MGTREFCLK0P_114
MGTTXN3_114MGTTXP3_114
MGTTXN2_114MGTTXP2_114
MGTTXN1_114MGTTXP1_114
MGTTXN0_114MGTTXP0_114
MGTRXN3_114
MGTRXP3_114
MGTRXN2_114
MGTRXP2_114
MGTRXN1_114
MGTRXP1_114
MGTRXN0_114
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 08 FPGA MGT POWER VCC, VTTLAST_MODIFIED=Tue May 30 11:11:55 2017
8/31
Project file:pcieppc.cpm
PCB by: PV DATE: 24/05/2017
8/31
SYSTEM: 16.03
Design by: R.Isocrate
MODULE:pcieppc
EDA-02264-V4-0 PROJECT:GGP
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
MGT_AVTT
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
MGT_AVCC
MGT_AVCCMGT_AVTT
C532
C533
C534
C535
C536
C537
C538
C539
C512
C510
C508
C507
C506
C505
C504
C509
C522
C521
C520
C519
C518
C514
C395
C394
C393
C392
C391
C390
C388
C387
C386
C385
C384
C383
C382
C389
C381
C523
C531
C530
C529
C528
C527
C526
C524
C525
C365
C366
C371
C374
C376
C377
C378
C379
IC16IC16
Y3W2AM3AL2AH3AG2AD3AC2
T3R2M3L2H3G2D3C2
Y32W33AM32AL33AH32AG33AD32AC33
T32R33M32L33H32G33D32C33
Y8AL7AK8AH8AF8AD8AB8
V8T8P8M8K8H8F8E7
Y27AL28AK27AH27AF27AD27AB27
V27T27P27M27K27H27F27E28
DGND
VCC
VCC
VCC
VCC
DGND
23/28MGT POWERXC6VHX380TFF1154
MGTAVTT_LS_Y32MGTAVTT_LS_W33MGTAVTT_LS_AM32MGTAVTT_LS_AL33MGTAVTT_LS_AH32MGTAVTT_LS_AG33MGTAVTT_LS_AD32MGTAVTT_LS_AC33
MGTAVTT_LN_T32MGTAVTT_LN_R33MGTAVTT_LN_M32MGTAVTT_LN_L33MGTAVTT_LN_H32MGTAVTT_LN_G33MGTAVTT_LN_D32MGTAVTT_LN_C33
MGTAVTT_RS_Y3MGTAVTT_RS_W2MGTAVTT_RS_AM3MGTAVTT_RS_AL2MGTAVTT_RS_AH3MGTAVTT_RS_AG2MGTAVTT_RS_AD3MGTAVTT_RS_AC2
MGTAVTT_RN_T3MGTAVTT_RN_R2MGTAVTT_RN_M3MGTAVTT_RN_L2MGTAVTT_RN_H3MGTAVTT_RN_G2MGTAVTT_RN_D3MGTAVTT_RN_C2
22/28MGT POWERXC6VHX380TFF1154
MGTAVCC_LS_Y27MGTAVCC_LS_AL28MGTAVCC_LS_AK27MGTAVCC_LS_AH27MGTAVCC_LS_AF27MGTAVCC_LS_AD27MGTAVCC_LS_AB27
MGTAVCC_LN_V27MGTAVCC_LN_T27MGTAVCC_LN_P27MGTAVCC_LN_M27MGTAVCC_LN_K27MGTAVCC_LN_H27MGTAVCC_LN_F27MGTAVCC_LN_E28
MGTAVCC_RS_Y8MGTAVCC_RS_AL7MGTAVCC_RS_AK8MGTAVCC_RS_AH8MGTAVCC_RS_AF8MGTAVCC_RS_AD8MGTAVCC_RS_AB8
MGTAVCC_RN_V8MGTAVCC_RN_T8MGTAVCC_RN_P8MGTAVCC_RN_M8MGTAVCC_RN_K8MGTAVCC_RN_H8MGTAVCC_RN_F8MGTAVCC_RN_E7
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 09 FPGA POWER GNDLAST_MODIFIED=Tue May 30 11:11:56 2017
9/31
Project file:pcieppc.cpm
9/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
IC16IC16IC16
Y9Y7Y4
Y31Y28Y26Y25Y24Y22Y20Y18Y16Y14Y12Y10
W9W6W5
W34W30W29W26W25W23W21W19W15W13W11W10
W1
V9V7V4
V32V31
V3
V28V26V25V24V22V20V16V14V12V10
U9U6U5
U34U33U30U29U26U25U23U21
U2
U19U15U13U11U10
U1
T9T7T4
T31
T28T26T25T24T22T20T16T14T12T10
R9R6R5
R34R30R29R26R25R23R21R19R17R15R13R11
R1
P9P7P4
P32P31
P3
P28P26P24P22P20P18P16P14P12
N9N6N5
N34N33N30N29N26N25N23N21
N2
N19N17N15N13N11
N1M31M28M26M18
M9M7M4
L9L6L5
L34L30L29L26L21L11
L1
K9K7K4
K32K31
K3
K28K26K24K14
J9J6J5
J34J33J30J29J26
J2
J17
J1
H9H7H4
H31H28H26H20H10
G9G6G5
G34G30G29G26G23G13
G1
F9F7F4
F32F31
F3
F28F26F16
E9E8E6E5
E34E33E30E29E27
E26
E2
E19
E1
D8D7D4
D31D28D27D22D12
C7C6C5
C34C30C29C28C25C15
C1
B8B7B6B5B4
B32B31B30
B3
B29B28B18
AP6AP4
AP32AP31
AP3
AP29AP22AP12
AN6AN5
AN34AN33AN30AN29AN25
AN2
AN15
AN1
AM8AM7AM6AM4
AM31AM29AM28AM27AM18
AL34
AL9AL8AL6AL5
AL30AL29AL27AL26AL21AL11
AL1
AK9AK7AK4
AK32AK31
AK3
AK28AK26AK24AK14
AJ9AJ6AJ5
AJ34AJ33AJ30AJ29AJ26
AJ2
AJ17
AJ1
AH9AH7AH4
AH31AH28AH26AH20AH10
AG9AG6AG5
AG34AG30AG29AG26AG23AG13
AG1
AF9AF7AF4
AF32AF31
AF3
AF28AF26AF16
AE9
AE6AE5
AE34AE33AE30AE29AE26
AE2
AE19
AE1
AD9AD7AD4
AD31AD28AD26AD22AD12
AC9AC6AC5
AC34AC30AC29AC26AC25AC15
AC1
AB9AB7AB4
AB32AB31
AB3
AB28AB26AB24AB22AB20AB18AB16AB14AB12
AA9AA6AA5
AA34AA33AA30AA29AA26AA23AA21
AA2
AA19AA17AA15AA13AA11
AA1
A7A6A5
A34A33A30A29A28A21
A2
A11
A1
DGND DGNDDGND DGNDDGNDDGND
26/28GND 3XC6VHX380TFF1154
GND_Y31GND_Y28GND_Y26GND_Y25GND_Y24GND_Y22GND_Y20GND_Y18GND_Y16GND_Y14GND_Y12GND_Y10GND_Y9GND_Y7GND_Y4
GND_W34GND_W30GND_W29GND_W26GND_W25GND_W23GND_W21GND_W19GND_W15GND_W13GND_W11GND_W10GND_W9GND_W6GND_W5GND_W1
GND_V32GND_V31GND_V28GND_V26GND_V25GND_V24GND_V22GND_V20GND_V16GND_V14GND_V12GND_V10GND_V9GND_V7GND_V4GND_V3
GND_U34GND_U33GND_U30GND_U29GND_U26GND_U25GND_U23GND_U21GND_U19GND_U15GND_U13GND_U11GND_U10GND_U9GND_U6GND_U5GND_U2GND_U1
GND_T31
GND_T28GND_T26GND_T25GND_T24GND_T22GND_T20GND_T16GND_T14GND_T12GND_T10GND_T9GND_T7GND_T4GND_R34GND_R30GND_R29GND_R26GND_R25GND_R23GND_R21GND_R19GND_R17GND_R15GND_R13GND_R11GND_R9GND_R6GND_R5GND_R1GND_P32GND_P31GND_P28GND_P26GND_P24GND_P22GND_P20GND_P18GND_P16GND_P14GND_P12GND_P9GND_P7GND_P4GND_P3GND_N34GND_N33GND_N30GND_N29GND_N26GND_N25GND_N23GND_N21GND_N19GND_N17GND_N15GND_N13GND_N11GND_N9GND_N6GND_N5GND_N2GND_N1GND_M31GND_M28GND_M26GND_M18
25/28GND 2XC6VHX380TFF1154
GND_M9GND_M7GND_M4
GND_L34GND_L30GND_L29GND_L26GND_L21GND_L11GND_L9GND_L6GND_L5GND_L1
GND_K32GND_K31GND_K28GND_K26GND_K24GND_K14GND_K9GND_K7GND_K4GND_K3
GND_J34GND_J33GND_J30GND_J29GND_J26GND_J17GND_J9GND_J6GND_J5GND_J2GND_J1
GND_H31GND_H28GND_H26GND_H20GND_H10GND_H9GND_H7GND_H4
GND_G34GND_G30GND_G29GND_G26GND_G23GND_G13GND_G9GND_G6GND_G5GND_G1
GND_F32GND_F31GND_F28GND_F26GND_F16GND_F9GND_F7GND_F4GND_F3
GND_E34GND_E33GND_E30GND_E29GND_E27
GND_E26GND_E19GND_E9GND_E8GND_E6GND_E5GND_E2GND_E1GND_D31GND_D28GND_D27GND_D22GND_D12GND_D8GND_D7GND_D4GND_C34GND_C30GND_C29GND_C28GND_C25GND_C15GND_C7GND_C6GND_C5GND_C1GND_B32GND_B31GND_B30GND_B29GND_B28GND_B18GND_B8GND_B7GND_B6GND_B5GND_B4GND_B3GND_AP32GND_AP31GND_AP29GND_AP22GND_AP12GND_AP6GND_AP4GND_AP3GND_AN34GND_AN33GND_AN30GND_AN29GND_AN25GND_AN15GND_AN6GND_AN5GND_AN2GND_AN1GND_AM31GND_AM29GND_AM28GND_AM27GND_AM18GND_AM8GND_AM7GND_AM6GND_AM4GND_AL34
24/28GND 1XC6VHX380TFF1154
GND_AL30GND_AL29GND_AL27GND_AL26GND_AL21GND_AL11GND_AL9GND_AL8GND_AL6GND_AL5GND_AL1
GND_AK32GND_AK31GND_AK28GND_AK26GND_AK24GND_AK14GND_AK9GND_AK7GND_AK4GND_AK3
GND_AJ34GND_AJ33GND_AJ30GND_AJ29GND_AJ26GND_AJ17GND_AJ9GND_AJ6GND_AJ5GND_AJ2GND_AJ1
GND_AH31GND_AH28GND_AH26GND_AH20GND_AH10GND_AH9GND_AH7GND_AH4
GND_AG34GND_AG30GND_AG29GND_AG26GND_AG23GND_AG13GND_AG9GND_AG6GND_AG5GND_AG1
GND_AF32GND_AF31GND_AF28GND_AF26GND_AF16GND_AF9GND_AF7GND_AF4GND_AF3
GND_AE34GND_AE33GND_AE30GND_AE29GND_AE26GND_AE19GND_AE9
GND_AE6GND_AE5GND_AE2GND_AE1GND_AD31GND_AD28GND_AD26GND_AD22GND_AD12GND_AD9GND_AD7GND_AD4GND_AC34GND_AC30GND_AC29GND_AC26GND_AC25GND_AC15GND_AC9GND_AC6GND_AC5GND_AC1GND_AB32GND_AB31GND_AB28GND_AB26GND_AB24GND_AB22GND_AB20GND_AB18GND_AB16GND_AB14GND_AB12GND_AB9GND_AB7GND_AB4GND_AB3GND_AA34GND_AA33GND_AA30GND_AA29GND_AA26GND_AA23GND_AA21GND_AA19GND_AA17GND_AA15GND_AA13GND_AA11GND_AA9GND_AA6GND_AA5GND_AA2GND_AA1GND_A34GND_A33GND_A30GND_A29GND_A28GND_A21GND_A11GND_A7GND_A6GND_A5GND_A2GND_A1
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 10 FPGA VCCAUX, VCCINT PROJECT:GGPEDA-02264-V4-0
MODULE:pcieppc
Design by: R.Isocrate
SYSTEM: 16.03
10/31
DATE: 24/05/2017PCB by: PV
Project file:pcieppc.cpm
LAST_MODIFIED=Tue May 30 11:11:56 201710/31
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
VCCAUX
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
VCCAUXC456
C449
C448
C473
C472
C471
C470
C469
C474
C475
C476
C477
C451
C482
C481
C480
C479
C478
C483
C484
C485
C486
C491
C490
C489
C488
C431
C432
C433
C419
C420
C421
C422
C427
C426
C425
C424
C423
C429
C430
C412
C455
C446
C411
C410
C409
C417
C416
C415
C414
C413
C418
C406
C405
C404
C403
C402
C408
C493
C494
C495
C496
C497
C492
IC16IC16
Y23Y21Y19Y17Y15Y13W22W20W16W14W12V23V21V19V15V13U22U20U16U14U12T23T21T19T15T13R22R20R18R16R14R12P23P21P19P17P15P13N22N20N18N16N14AB21AB19AB17AB15AB13AA22AA20AA18AA16AA14AA12
Y11W24V11U24T11R24P11N24N12
AB23AB11AA24
DGND
P1V0
P1V0VCC
P1V0
DGND
VCC
DGND
28/28VCCINTXC6VHX380TFF1154
VCCINT_Y23VCCINT_Y21VCCINT_Y19VCCINT_Y17VCCINT_Y15VCCINT_Y13VCCINT_W22VCCINT_W20VCCINT_W16VCCINT_W14VCCINT_W12VCCINT_V23VCCINT_V21VCCINT_V19VCCINT_V15VCCINT_V13VCCINT_U22VCCINT_U20VCCINT_U16VCCINT_U14VCCINT_U12VCCINT_T23VCCINT_T21VCCINT_T19VCCINT_T15VCCINT_T13VCCINT_R22VCCINT_R20VCCINT_R18VCCINT_R16VCCINT_R14VCCINT_R12VCCINT_P23VCCINT_P21VCCINT_P19VCCINT_P17VCCINT_P15VCCINT_P13VCCINT_N22VCCINT_N20VCCINT_N18VCCINT_N16VCCINT_N14VCCINT_AB21VCCINT_AB19VCCINT_AB17VCCINT_AB15VCCINT_AB13VCCINT_AA22VCCINT_AA20VCCINT_AA18VCCINT_AA16VCCINT_AA14VCCINT_AA12
27/28VCCAUXXC6VHX380TFF1154
VCCAUX_Y11VCCAUX_W24VCCAUX_V11VCCAUX_U24VCCAUX_T11VCCAUX_R24VCCAUX_P11VCCAUX_N24VCCAUX_N12VCCAUX_AB23VCCAUX_AB11VCCAUX_AA24
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 11 1MX36 DUAL PORT RAM
DEFAULT-----------------ST3 2-3ST8 1-2ST6 2-3ST5 1-2----------------
Design by: R.Isocrate
LAST_MODIFIED=Tue May 30 11:19:54 2017
PCB by: PV
PROJECT:GGPProject file:pcieppc.cpm
MODULE:pcieppc
EDA-02264-V4-0
11/31
DATE: 24/05/2017
11/31
SYSTEM: 16.03
MOUNTED=NO
GSD
BSS138N
4.7K
100nF
330
0R0
VREF
100nF
100nF
CYD36S36V18-200BGXCCYD36S36V18-200BGXC
BGA
VREF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
VREF
330
330
330
BGA
4.7K
4.7K
100nF
ST6
ST5
ST7
ST8
R195
C599
C604
C611
C622
C591
C600
C615
C587
C612
C585
C617
C597
C608
C609
C595
C610
C614
C621
C593
C613
C603
C594
C607
C592
C598
C590
C601
C606
C589
C586
C584
C605
C602
C620
C619
C588
R190
R191
T3
R194
R188
R189
R192
R193
IC19IC19
DPRAM_DATA_L12DPRAM_DATA_L13DPRAM_DATA_L14DPRAM_DATA_L15DPRAM_DATA_L16DPRAM_DATA_L17DPRAM_DATA_L18DPRAM_DATA_L19DPRAM_DATA_L20DPRAM_DATA_L21DPRAM_DATA_L22DPRAM_DATA_L23
DPRAM_DATA_L11DPRAM_DATA_L10
DPRAM_BUSY_L
DPRAM_FTSEL_L
DPRAM_ADDR_L10DPRAM_ADDR_L11
DPRAM_DATA_R16DPRAM_DATA_R17DPRAM_DATA_R18
FPGA_DPRAM_MRST
DPRAM_DATA_R29DPRAM_DATA_R28DPRAM_DATA_R27DPRAM_DATA_R26DPRAM_DATA_R25DPRAM_DATA_R24DPRAM_DATA_R23DPRAM_DATA_R22DPRAM_DATA_R21DPRAM_DATA_R20DPRAM_DATA_R19
DPRAM_DATA_R15
DPRAM_ADDR_L0
DPRAM_ADDR_L2DPRAM_ADDR_L3DPRAM_ADDR_L4DPRAM_ADDR_L5
LOC_TRST
DPRAM_FTSEL_R
DPRAM_ADDR_L1
DPRAM_ADDR_L6DPRAM_ADDR_L7DPRAM_ADDR_L8DPRAM_ADDR_L9
DPRAM_ADDR_L13DPRAM_ADDR_L14DPRAM_ADDR_L15
DPRAM_ADDR_L17
DPRAM_ADDR_L19
DPRAM_CNTMSK_LDPRAM_ADS_LDPRAM_CNTEN_LDPRAM_CNTRST_LDPRAM_RET_LDPRAM_CNTINT_LDPRAM_CLK_LDPRAM_WRP_L
DPRAM_INT_L
DPRAM_DATA_R14DPRAM_DATA_R13
DPRAM_DATA_L33
DPRAM_DATA_L29
DPRAM_DATA_L26
DPRAM_DATA_L24
DPRAM_DATA_L8DPRAM_DATA_L9
DPRAM_DATA_L7DPRAM_DATA_L6DPRAM_DATA_L5DPRAM_DATA_L4DPRAM_DATA_L3DPRAM_DATA_L2DPRAM_DATA_L1DPRAM_DATA_L0
DPRAM_TDO
DPRAM_CQ_L0_P
DPRAM_CQ_L1_P
DPRAM_READY_L
FPGA_TCKFPGA_TDO
DPRAM_DATA_L34DPRAM_DATA_L35
FPGA_TMS
DPRAM_OE_LDPRAM_RW_L
DPRAM_DATA_L32
LOC_TRST
DPRAM_READY_R
DPRAM_DATA_R31
DPRAM_DATA_R34
DPRAM_BUSY_R
DPRAM_ADDR_L12
DPRAM_INT_R
DPRAM_WRP_RDPRAM_CLK_RDPRAM_CNTINT_RDPRAM_RET_RDPRAM_CNTRST_R
DPRAM_ADS_RDPRAM_CNTEN_R
DPRAM_CNTMSK_R
DPRAM_ADDR_R0DPRAM_ADDR_R1DPRAM_ADDR_R2DPRAM_ADDR_R3DPRAM_ADDR_R4
DPRAM_ADDR_R6DPRAM_ADDR_R5
DPRAM_ADDR_R7DPRAM_ADDR_R8DPRAM_ADDR_R9DPRAM_ADDR_R10DPRAM_ADDR_R11DPRAM_ADDR_R12DPRAM_ADDR_R13DPRAM_ADDR_R14
DPRAM_ADDR_R16DPRAM_ADDR_R15
DPRAM_ADDR_R17DPRAM_ADDR_R18DPRAM_ADDR_R19
DPRAM_DATA_R0DPRAM_DATA_R1DPRAM_DATA_R2DPRAM_DATA_R3DPRAM_DATA_R4DPRAM_DATA_R5DPRAM_DATA_R6DPRAM_DATA_R7DPRAM_DATA_R8DPRAM_DATA_R9
DPRAM_DATA_R11DPRAM_DATA_R10
DPRAM_DATA_R12
DPRAM_DATA_R30
DPRAM_DATA_R32DPRAM_DATA_R33
DPRAM_DATA_R35
DPRAM_OE_RDPRAM_RW_RDPRAM_CQ_R0_P
DPRAM_CQ_R1_P
DPRAM_ADDR_L18
DPRAM_ADDR_L16
DPRAM_MRST
DPRAM_DATA_L28
DPRAM_DATA_L30DPRAM_DATA_L31
DPRAM_MRST
DPRAM_DATA_L27
DPRAM_DATA_L25
K3D11
H3
V18Y19W20W19Y20
G3
J3
U3
D14D10
L4
W4
D9
T4
V3
AB8Y9
AA9AB9Y10
AA10AB10
C6B6A6C7B7A7
Y11
C8B8A8C9B9A9
C10B10A10C11
AA11
B11A11Y6
AA6AB6Y7
AA7AB7Y8
AA8
AB11
U4
D6D7W6W7
T3
D13
R3
P3
L3F3F4
D12
H4G4P4R4
N3
L2L1K2K1J2J1H2H1G2
T2T1R2R1P2P1N2N1M2M1
G1
K20W12
H20
G20
J20
U20
W9W13
L19
W14
T19
V20
AB15Y14AA14AB14Y13AA13AB13
C17B17A17C16B16A16
Y12
C15B15A15C14B14A14C13B13A13C12
AA12
B12A12Y17AA17AB17Y16AA16AB16Y15AA15
AB12
L20
U19
D17D16W17W16
T20
W10
R20
P20
F20F19
W11
H19G19P19R19
N20
L21L22K21K22J21J22H21H22G21
T21T22R21R22P21P22N21N22M21M22
G22
P1V5
PAD3
PAD3
DGND
PAD3
DGND
P1V5
PAD3
DGND
P1V5
P1V5
DGNDDGND
P2V5
P2V5P1V5
DGND
DGND DGND
DGND DGND
P1V5
DGND
P1V5
DGND
PORTSTD1LPORTSTD0LCQENLFTSELL*
BUSYL*
WRPL*
INTL*
CNTINTL*CL
RETL*CNTRSTL*CNTENL*
CNT/MSKLADSL*
DNU[88]
MRST*
VDDIOL[34]VREFL[2]
VCORE[16]VTTL[12]VSS[118]
CQ1L*CQ1L
CQ0LCQ0L*
R/WLOEL*CE1L
BE3L*CE0L*
BE2L*BE1L*BE0L*
A0L
A3LA2LA1L
A4LA5L
A8LA7LA6L
A9LA10L
A13L
A11LA12L
A14LA15L
A17LA16L
A18LA19L
DQ0LDQ1LDQ2LDQ3LDQ4LDQ5LDQ6LDQ7LDQ8L
DQ10LDQ9L
DQ11LDQ12LDQ13LDQ14LDQ15LDQ16L
DQ18LDQ17L
DQ19LDQ20LDQ21L
DQ23LDQ22L
DQ24L
DQ26LDQ25L
DQ28LDQ27L
DQ29L
DQ31LDQ30L
DQ33LDQ32L
DQ34LDQ35L
ZQ0LZQ1LREADYL*LOWSPDL*
TCKTDITDOTMSTRST*
PORTSTD1RPORTSTD0RCQENRFTSELR*
BUSYR*
VREFR[1..0]VDDIOR[20..0]
LOWSPDR*READYR*ZQ1RZQ0R
INTR*
WRPR*CR
CNTINTR*RETR*
CNTRSTR*
ADSR*CNTENR*
CNT/MSKR
A0RA1RA2RA3RA4R
A6RA5R
A7RA8RA9R
A10RA11RA12RA13RA14R
A16RA15R
A17RA18RA19R
DQ0RDQ1RDQ2RDQ3RDQ4RDQ5RDQ6RDQ7RDQ8RDQ9R
DQ11RDQ10R
DQ12R
DQ14RDQ13R
DQ15RDQ16RDQ17R
DQ19RDQ18R
DQ21RDQ20R
DQ22R
DQ24RDQ23R
DQ25RDQ26RDQ27RDQ28RDQ29R
DQ31RDQ30R
DQ32RDQ33RDQ34RDQ35R
BE0R*BE1R*BE2R*BE3R*
CE1RCE0R*
OER*R/WRCQ0RCQ0R*CQ1RCQ1R*
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
CLKOUT4 LVDS
CLKOUT0 LVDS
CLKOUT3 LVPECLCLKOUT2 LVCMOSCLKOUT1 LVPECL
PLL2 LOOP FILTER
PAGE 12 CLOCK CONDITIONER AND DELAY LINES
PLL1 LOOP FILTER
LAST_MODIFIED=Tue May 30 11:20:54 201712/31
Project file:pcieppc.cpm
12/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
MOUNTED=NO
820nF
18nF
12k
MOUNTED=NO
16V
12nF
VCC_PLL
VCC_PLL
1uF
470
5.6nF
50V
P3V3
VCC_PLL
100nF
100nF
120120
120120
100NF
10uF
10V
100nF470nF
VCC_PLL
LLP
VCC_PLL
100nF
100nF100nF
P3V3
100NF
1.5k
0R00R0
GND=DGND
100NF
100NF
100NF
LMK04033BISQ
100NF
100nF
100nF
100NF
P3V3
P3V3
100nF
100nF
SY89295UMG
100NF
10V
1.5k
1/16W
1%
100NF
100nF
P3V3
P3V3
GND=DGND
QFN
GND=DGND;VCC=P2V5
GND=DGND;VCC=P2V5QFN
SY89295UMG
49.9 49.9
49.949.9
10V
90-MMCX-S50-0-55
MOUNTED=NO
16V
12nF
100NF
SMDCVHD-950X-100.000
100MHZ
50V
680pF
100NF49.9
100NF
100
VCC_PLL
C89
C88
C99
C100
C101
C553
C555
C554
C91
C93
C92
C547
C546
C339
C338
IC9
R7R6
PX5
C85
C84 C83
C94
IC12
C550
C549
R260
R261
C551
C552
R262
R263
C548
R36
R35
R30R31
C341
IC10
R37
C122
R32
C102
R26
C87
C86
R28
C97
C98
R29
R27
C90
QZ2
DLY_CLOCK_3_P
VCXO_OUT
DLY_CLOCK_1_N
DLY_10
DLY_3
DLY_6
DLY_8DLY_9LEN1
CRS_PLL_IN_P
PLL_UWIRE_CLK
PLL_LD
PLL_GOE
DLY_4
DLY_CLOCK_1_P
DLY_5
DLY_1DLY_2
DLY_7
DLY_0
PLL_LOS
PLL_UWIRE_DATAPLL_UWIRE_LE
SYNC_PLL
PLL_OUT_3_PPLL_OUT_3_N
DLY_10
LEN0DLY_9
DLY_7
DLY_4DLY_5DLY_6
DLY_2DLY_3
DLY_0DLY_1
DLY_8
PLL_OUT_1_N
PLL_OUT_3_N
DLY_CLOCK_3_N
PLL_OUT_1_P
PLL_OUT_1_NPLL_OUT_1_P
CRS_PLL_IN_N
VCXO_OUT
PLL_OUT_0_P
PLL_OUT_3_P
PLL_OUT_4_NPLL_OUT_4_P
PLL_OUT_0_N
3130
24221918138
4643403733
3
27
2928
6
109
12
11
2
16
5
3223
4
48474544424139381514
352625
34
2120
36
786
1112
2021
10
54
16
3
213231302927262523
1415
786
1112
2021
10
54
16
3
21
3231302927262523
1415
21
1
4
1 3
2
P2V5
VCC
P2V5
IN
EN*IN*
D[1]D[0]
D[3]D[2]
D[6]D[5]D[4]
D[8]D[7]
D[9]
SETMAXLEN
SETMIN
QQ*
CASCADE*CASCADE
D10
VCFVEF
VBB
VCC
DGND DGND
VCC
DGND DGND
GNDVDD
V/C OUT
DGND DGND
DGND DGND
DGND
VCC
VCC
VCC
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
P2V5
P2V5
DGND
DGND
DGND
P2V5
P2V5
CLKIN1CLKIN1*CLKIN1_LOS
CLKOUT1CLKOUT1*
FOUTCPOUT1CPOUT2
CLKOUT0CLKOUT0*
VCC8VCC9
VCC10VCC11VCC12
VCC14VCC13
CLKIN0_LOSCLKIN0CLKIN0*
OSCINOSCIN*
GOESYNC*LD
LEUWIREDATAUWIRECLKUWIRE
DLD_BYP
BIAS
LDOBYP2LDOBYP1
VCC2VCC1
VCC3VCC4VCC5VCC6VCC7
CLKOUT2CLKOUT2*CLKOUT3
CLKOUT3*CLKOUT4
CLKOUT4*
DGNDDGNDDGND
IN
EN*IN*
D[1]D[0]
D[3]D[2]
D[6]D[5]D[4]
D[8]D[7]
D[9]
SETMAXLEN
SETMIN
QQ*
CASCADE*CASCADE
D10
VCFVEF
VBB
DGNDDGND
DGNDDGND
DGND
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 13 DELAYED CLOCK 2 TO 8 FANOUTLAST_MODIFIED=Tue May 30 11:11:47 2017
13/31
Project file:pcieppc.cpm
13/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
19.1
100nF
100nF
GND=DGND;VCC=P2V5
100NF
100NF
100NF
100nF
100nF
SY89113UMG
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF100NF
100NF
100NF
100NF
100
100NF
10NF MLF
C336
C334
C543
C545R168
R33
C337
C114
C115
C118
C119
C109
C108
C104
C105
C107
C106
C111
C110
C116
C117
C113
C112IC11
DLY_CLOCK_3_N
CLK_FPGA_DLD_PCLK_FPGA_DLD_N
CLKDLD_113_NCLKDLD_113_P
CLKDLD_110_NCLKDLD_110_P
CLKDLD_101_P
CLKDLD_111_PCLKDLD_111_N
CLKDLD_114_NCLKDLD_114_P
CLK_FBK_DLD_NCLK_FBK_DLD_P
MGTFO_0_SEL
DLY_CLOCK_3_P
CLKDLD_105_PCLKDLD_105_N
CLKDLD_101_N
CLKDLD_104_PCLKDLD_104_N
CLKDLD_102_PCLKDLD_102_N
3
4
97
18192021242526272930313235363738
14151617
3940414212
44
108
5
2
DGND
P2V5
DGND
P2V5
P2V5
Q0Q0*Q1
Q1*Q2
Q2*Q3
Q3*
Q4*Q4
Q5Q5*Q6
Q6*Q7
Q7*Q8
Q8*Q9
Q9*Q10
Q11Q10*
Q11*
EN
CLK_SEL
VREF_AC0
CLK0VT0CLK0*
CLK1CLK1*
VBB1SE-TERM
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 14 GTX CLOCK 2 TO 12 FANOUTLAST_MODIFIED=Tue May 30 11:11:47 2017
14/31
Project file:pcieppc.cpm
14/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
GND=DGND;VCC=P2V5MLF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100
100NF
SY89113UMG
100NF
100NF
100nF
100nF
100nF
100nF
C567
C568
C565
C566
C133
C134
R38
IC15
C137
C138
C145
C144
C141
C140
C130
C129
C126
C125
C135
C136
C147
C146
C143
C142
C132
C131
C128
C127
CLKGTX_110_PCLKGTX_110_N
CLKGTX_103_PCLKGTX_103_N
CLKGTX_111_PCLKGTX_111_N
CLK_FBK_GTX_NCLK_FBK_GTX_P
MGTFO_1_SEL
PLL_OUT_0_P
CLKGTX_114_PCLKGTX_114_N
CLKGTX_115_PCLKGTX_115_N
CLKGTX_112_PCLKGTX_112_N
CLKGTX_113_PCLKGTX_113_N
CLKGTX_101_PCLKGTX_101_N
CLKGTX_105_PCLKGTX_105_N
CLKGTX_102_PCLKGTX_102_N
CLKGTX_104_PCLKGTX_104_N
PLL_OUT_0_N
CLK_FPGA_GTX_PCLK_FPGA_GTX_N
3
4
97
18192021242526272930313235363738
14151617
3940414212
44
108
5
2
DGND
P2V5
Q0Q0*Q1
Q1*Q2
Q2*Q3
Q3*
Q4*Q4
Q5Q5*Q6
Q6*Q7
Q7*Q8
Q8*Q9
Q9*Q10
Q11Q10*
Q11*
EN
CLK_SEL
VREF_AC0
CLK0VT0CLK0*
CLK1CLK1*
VBB1SE-TERM
P2V5
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 15 GTX CLOCK 4X4 CROSSBAR, ADC CLOCK 2X2 CROSSBAR
LAST_MODIFIED=Tue May 30 11:11:47 201715/31
Project file:pcieppc.cpm
15/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
GND=DGND;VCC=P2V5
GND=DGND;VCC=P2V5
S1614B-100.000
100MHz
MOUNTED=NOMOUNTED=NO
240
SY58603UMG
EP=DGND;VCC=P2V5
MLF8
100nF
MOUNTED=NO
20
MOUNTED=NO
100nF
49.9
49.9
100nF
GND=DGND
GND=DGND
LVDS
0R0
100nF
100nF
100nF
100nF
100NF10V
100NF
DFN8
0R0
240
100100NF
90-MMCX-S50-0-55
GND=DGND
100NF
90-MMCX-S50-0-55
GND=DGND
20
90-MMCX-S50-0-55
90-MMCX-S50-0-55
100NF
100NF
100NF33
GND=DGND
MOUNTED=NO
100NF
20
100MHZ
100nF
100nF
MLFI100
10
10
0R0
100NFMOUNTED=NO
0R0
MOUNTED=NOSY58605UMG
GND=DGND;VCC=P2V5
MOUNTED=NO
QZ3
IC2
C5
C278
C277
C274
C272
C571
C569
C544
IC13
R9
R8
IC25
R5
R2
R1
R34C333
C570 R259
C123
C124
C3
C4
C2
C1
IC14
PX3
PX4
PX2
PX1
QZ1
R3
R4
C276
R111
R110
C275
R113
R112
ADC_SEL0
CLK_FBK_ADC_NCLK_FBK_ADC_P
CRS_PLL_IN_P
ADC_CLOCK_NADC_CLOCK_P
CR0_SIN0
CLK_SMA_IN_P
CLK_SMA_IN_N
CLK_FPGA_LOC_P
CLK_FPGA_LOC_N
CR0_SIN<0..1>CR0_SOUT<0..1>
CLK_REF_PCIE_N
CLK_REF_PCIE_P
CLK_SMA_OUT_P
CR0_SIN1
CR0_SOUT0CR0_SOUT1
ADC_SEL1
CR0_LOADCR0_CONF
CLK_REF_P
CLK_FPGA_RAW_N
CLK_FPGA_RAW_P
CLK_REF_N
CLK_SMA_OUT_N
CRS_PLL_IN_N
CLK_FPGA_ADC_N
CLK_FPGA_BASE
DLY_CLOCK_1_PDLY_CLOCK_1_N
CLK_FPGA_ADC_P
31
40
3
9
16
42
1
11
14
33
32
30
29
27
26
24
23
5
39
41
2
4
8
10
15
17
7
2 3
67
41
2 3
67
41
5
16
6
15
109
1112
3
42
1
6
541
3
P2V5
DGND
DGND
P2V5
P2V5
P2V5
DGND
DGND
DGND
P2V5
DGND
P2V5
DGND
DGND
P2V5
ININ*
VT
Q*Q
VREF-AC
DGNDDGND
P2V5
VREF/AC
QQ*
VT
IN*IN
DGNDDGND
DGND
P2V5
P2V5
DGND
P2V5
DGND
SY58023U
Q1*
VCC<1-0>
GND<1-0>
Q1VT1IN1*SEL1
IN1IN0*
IN0VT0
SEL0Q0
Q0*
OUT
VDD
OEOUT*
GND
P2V5
DGND
P2V5
DGND
EN/D OUT
SY89540U
VT3
VT0
IN3
SOUT[1..0]SIN[1..0]LOADCONF
OUT3*
OUT3
OUT2*
OUT2
OUT1*
OUT1
OUT0*
OUT0
VREF3IN3*
VREF2IN2*VT2IN2
VREF1IN1*VT1IN1
VREF0IN0*
IN0
DGND
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 16 PCI EXPRESS CLOCK 4X4 CROSSBARLAST_MODIFIED=Tue May 30 11:11:48 2017
16/31
Project file:pcieppc.cpm
16/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
100
MOUNTED=NO
100NF
100NF
GND=DGND;VCC=P2V5
MLFI56
100nF
GND=DGND;VDD=P3V3TSSOP
ICS854104AGLF
1
49.9
49.9
100nF
100nF
100nF
01
0
IC57
C158
C160
C157C578
R267
R266
IC58
R265
C577
C576
CLK_REF_PCIE_P
CR1_SIN<1..0>CR1_SOUT<1..0>
CLKPE0_110_NCLKPE0_110_P
PLL_OUT_4_P
CR1_LOADCR1_CONF
PLL_OUT_4_N
CLK_FPGA_PCI_N
CLK_FPGA_PCI_P
CLK_REF_PCIE_N
PCIE_CLK_P
CR1_SIN0CR1_SIN1
CR1_SOUT0
PCIE_CLK_N
CR1_SOUT1
40
3
9
16
42
1
11
14
33
32
30
29
27
26
24
23
5
39
41
2
4
8
10
15
17
78
3
2
1
9
11
13
15
10
12
14
16
76
SY89540U
VT3
VT0
IN3
SOUT[1..0]SIN[1..0]LOADCONF
OUT3*
OUT3
OUT2*
OUT2
OUT1*
OUT1
OUT0*
OUT0
VREF3IN3*
VREF2IN2*VT2IN2
VREF1IN1*VT1IN1
VREF0IN0*
IN0
P2V5
DGND
P2V5
DGND
P2V5
DGND
DGND
P2V5
DGNDDGND
P2V5
QE[3]
QE[2]
QE[1]
QE[0]
CLKCLK*
Q[3]*
Q[2]
Q[3]Q[2]*
Q[1]Q[1]*
Q[0]Q[0]*
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 17 PCI EXPRESS FINGER CONNECTORLAST_MODIFIED=Tue May 30 11:27:04 2017
17/31
Project file:pcieppc.cpm
17/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
4.7k
MOUNTED=NO
CON64AB_PCIE_CARD
0R0
MOUNTED=NO
4.7K
15
0R0
0R0
R271
R270
R269
R268
R43
R44
P1
PCIE_WAKE
PCI_PRSNT
PCI_PRSNT_X1
PCIEL0_RX_NPCIEL0_RX_P
PCIEL1_RX_PPCIEL1_RX_N
PCIEL2_RX_PPCIEL2_RX_N
PCIEL3_RX_PPCIEL3_RX_N
PCI_PRSNT_X4
PCIE_PERST
PCIE_CLK_PPCIE_CLK_N
PCIEL3_TX_NPCIEL3_TX_P
PCIEL2_TX_NPCIEL2_TX_P
PCIEL1_TX_NPCIEL1_TX_P
PCIEL0_TX_NPCIEL0_TX_P
PCI_PRSNT_X4
PCI_PRSNT_X1 PCI_PRSNT
1
B11
B9A8A7A6A5
B6B5
B30
B12
A32
A19
A14A13
B31
B17
A1
B27
B23
B19
B14
B28
B24
B20
B15
A11
A29
A25
A21
A16
A30
A26
A22
A17
B32A31
A28A27
A24A23
A20
A18
A15
A12
A4
B29
B26B25
B22B21
B18
B16
B13
B7
B4
B10 A10A9
B8
A3A2
B3B2B1
DGND
P3V3D
DGND
P3V3D
DGND
P3V3DP3V3D
GNDPETp1PETn1GNDGNDPETp2PETn2GNDGNDPETp3PETn3GNDRSVD_B30PRSNT2#_B31GND
PRSNT2#_B17GND
+12V+12V+12VGNDSMCLKSMDATGND+3.3V
3.3Vaux
RSVD_B12GNDPETp0
TRST#
PERn0GND
RSVD_A19GND
PERp1
GNDGND
PERp2PERn2GNDGND
PERp3PERn3GND
RSVD_A32
PERp0
PRSNT1#+12V+12VGNDTCKTDITDOTMS
+3.3V+3.3V
PERST#
GNDREFCLK+REFCLK-
GND
PERn1
PETn0
WAKE#
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 18 TRANSCEIVERS ADD-ON CONNECTORS PART 1/2LAST_MODIFIED=Tue May 30 11:11:57 2017
18/31
Project file:pcieppc.cpm
18/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
84553-001LF84553-001LF
P5VP5V
RECEPTACLE
84553-001LF
RECEPTACLERECEPTACLE
J1J1J1
GTX112_5_RX_PGTX112_5_RX_N
GTX112_4_RX_PGTX112_4_RX_N
GTX115_17_RX_PGTX115_17_RX_N
GTX115_16_RX_PGTX115_16_RX_N
GTX103_29_RX_PGTX103_29_RX_N
GTX103_28_RX_PGTX103_28_RX_N
AO_PMB_ALERT
SYNC_AUX_IN_NSYNC_AUX_IN_P
SYNC_AUX_OUT_PSYNC_AUX_OUT_N
SYNC_OUT_1_NSYNC_OUT_0_N
ADC_CLOCK_P
VCC10_RUN
VCC11_RUN
TRIM_LOCK
DCDC_SYNC
AO_CTL_SCL
GTX102_35_RX_N
GTX102_34_RX_PGTX102_34_RX_N
GTX102_35_RX_P
GTX114_14_RX_NGTX114_14_RX_P
GTX103_31_RX_N
GTX103_30_RX_P
GTX103_31_RX_P
GTX115_18_RX_N
SYNC_OUT_1_P
SYNC_IN_1_NSYNC_IN_1_P
ADC_CLOCK_N
GTX103_30_RX_N
GTX115_18_RX_P
GTX115_19_RX_NGTX115_19_RX_P
GTX112_6_RX_NGTX112_6_RX_P
GTX112_7_RX_NGTX112_7_RX_P
SYNC_IN_0_PSYNC_IN_0_N
AO_PMB_SCL
AO_PMB_SDA
SYNC_OUT_0_P
AO_CTL_SDA
GTX111_3_RX_PGTX111_3_RX_N
GTX111_2_RX_PGTX111_2_RX_N
GTX114_15_RX_PGTX114_15_RX_N
GTX104_26_RX_NGTX104_26_RX_P
GTX104_27_RX_NGTX104_27_RX_P
GTX105_22_RX_N
GTX113_11_RX_PGTX113_11_RX_N
GTX113_10_RX_PGTX113_10_RX_N
GTX105_23_RX_PGTX105_23_RX_N
GTX105_22_RX_P
F9F8F7F6F5F4
F30
F3
F29F28F27F26F25F24F23F22F21F20
F2
F19F18F17F16F15F14F13F12F11F10
F1
E9E8E7E6E5E4
E30
E3
E29E28E27E26E25E24E23E22E21E20
E2
E19E18E17E16E15E14E13E12E11E10
E1
D9D8D7D6D5D4
D30
D3
D29D28D27D26D25D24D23D22D21D20
D2
D19D18D17D16D15D14D13D12D11D10
D1
C9C8C7C6C5C4
C30
C3
C29C28C27C26C25C24C23C22C21C20
C2
C19C18C17C16C15C14C13C12C11C10
C1
B9B8B7B6B5B4
B30
B3
B29B28B27B26B25B24B23B22B21B20
B2
B19B18B17B16B15B14B13B12B11B10
B1
A9A8A7A6A5A4
A30
A3
A29A28A27A26A25A24A23A22A21A20
A2
A19A18A17A16A15A14A13A12A11A10
A1
DGNDDGNDDGNDDGND
DGNDDGND
F30F29
F27F28
F26F25F24F23
F21F22
F20F19F18
F16F17
F15F14F13
F11F12
F10F9F8
F6F7
F5F4F3
F1F2
E30E29E28E27E26E25E24E23E22E21E20E19E18E17E16E15E14E13E12E11E10E9E8E7
E5E6
E4E3
E1E2
D30D29
D27D28
D26D25D24D23
D21D22
D20D19D18
D16D17
D15D14D13
D11D12
D10D9D8
D6D7
D5D4D3
D1D2
C30C29C28C27C26C25C24C23C22C21C20C19C18C17C16C15C14C13C12C11C10C9C8C7
C5C6
C4C3
C1C2
P3V3C
A8
B30B29
B27B28
B26B25B24B23
B21B22
B20B19B18
B16B17
B15B14B13
B11B12
B10B9B8
B6B7
B5B4B3
B1B2
A30A29A28A27A26A25A24A23A22A21A20A19A18A17A16A15A14A13A12A11A10A9
A7
A5A6
A4A3
A1A2
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 19 TRANSCEIVERS ADD-ON CONNECTORS PART 2/2LAST_MODIFIED=Tue May 30 11:22:26 2017
19/31
Project file:pcieppc.cpm
19/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
4.7k
4.7k
84553-001LF
GND=DGND
RECEPTACLE
FEMALE
QTE-014-01-L-D-DP-A
84553-001LF
RECEPTACLE
R169
R170
J2J1 J1
ADDON_CODE1ADDON_CODE0
GTX100_43_RX_N
GTX100_42_TX_PGTX100_42_TX_N
CLK_LINK_NCLK_LINK_PLINK_IN_1_NLINK_IN_1_PLINK_IN_0_NLINK_IN_0_P
LINK_OUT_1_NLINK_OUT_1_PLINK_OUT_0_NLINK_OUT_0_P
GTX100_42_RX_NGTX100_42_RX_P
GTX100_43_TX_NGTX100_43_TX_P
GTX100_43_RX_P
GTX101_38_RX_N
GTX100_40_RX_NGTX100_40_RX_P
GTX114_13_RX_PGTX114_13_RX_N
GTX100_40_TX_NGTX100_40_TX_P
GTX100_41_RX_N
GTX101_39_TX_P
GTX104_24_TX_NGTX104_24_TX_P
GTX101_39_TX_NGTX101_39_RX_N
GTX101_38_RX_P
GTX102_32_TX_N
GTX101_37_TX_N
GTX101_36_TX_N
GTX100_41_RX_P
GTX101_36_RX_NGTX101_36_RX_P
GTX101_37_RX_NGTX101_37_RX_P
GTX102_32_RX_NGTX102_32_RX_P
GTX102_33_RX_PGTX102_33_RX_N
GTX105_20_RX_NGTX105_20_RX_P
GTX105_21_RX_NGTX105_21_RX_P
GTX111_0_RX_NGTX111_0_RX_P
GTX111_1_RX_NGTX111_1_RX_P
GTX100_41_TX_PGTX100_41_TX_N
GTX101_36_TX_P
GTX101_37_TX_P
GTX102_32_TX_P
GTX102_33_TX_NGTX102_33_TX_P
GTX105_20_TX_NGTX105_20_TX_P
GTX105_21_TX_NGTX105_21_TX_P
GTX111_0_TX_NGTX111_0_TX_P
GTX111_1_TX_NGTX111_1_TX_P
GTX101_39_RX_P
GTX104_24_RX_NGTX104_24_RX_P
GTX104_25_RX_NGTX104_25_RX_P
GTX114_12_RX_NGTX114_12_RX_P
GTX113_8_RX_NGTX113_8_RX_P
GTX113_9_RX_NGTX113_9_RX_P
GTX101_38_TX_NGTX101_38_TX_P
GTX104_25_TX_NGTX104_25_TX_P
GTX114_12_TX_NGTX114_12_TX_P
GTX114_13_TX_NGTX114_13_TX_P
GTX113_8_TX_NGTX113_8_TX_P
GTX113_9_TX_NGTX113_9_TX_P
19171614
15131210119867542
28262725242223212018
31
H9H8H7H6H5H4
H30
H3
H29H28H27H26H25H24H23H22H21H20
H2
H19H18H17H16H15H14H13H12H11H10
H1
G9G8G7G6G5G4
G30
G3
G29G28G27G26G25G24G23G22G21G20
G2
G19G18G17G16G15G14G13G12G11G10
G1
J9J8J7J6J5J4
J30
J3
J29J28J27J26J25J24J23J22J21J20
J2
J19J18J17J16J15J14J13J12J11J10
J1
I9I8I7I6I5I4
I30
I3
I29I28I27I26I25I24I23I22I21I20
I2
I19I18I17I16I15I14I13I12I11I10
I1
DP3<0>
DP2<1>
DP2<0>
DP1<1>
DP1<0>
DP7<1>
DP6<1>
DP5<1>
DP4<1>
DP3<1>
DP14<1>
DP13<1>
DP12<1>
DP11<1>
DP10<1>
DP9<1>
DP8<1>
DP9<0>
DP10<0>
DP11<0>
DP12<0>
DP13<0>
DP14<0>
DP5<0>
DP4<0>
DP8<0>
DP6<0>
DP7<0>
DGNDDGNDDGNDDGND
G2
G30G29G28G27G26G25G24G23G22G21G20G19G18G17G16G15G14G13G12G11G10G9G8G7
G5G6
G4G3
G1
H30H29
H27H28
H26H25H24H23
H21H22
H20H19H18
H16H17
H15H14H13
H11H12
H10H9H8
H6H7
H5H4H3
H1H2
P2V5
I30I29I28I27I26I25I24I23I22I21I20I19I18I17I16I15I14I13I12I11I10I9I8I7
I5I6
I4I3I2I1
J30J29J28J27J26J25J24J23J22J21J20J19J18J17J16J15J14J13J12J11J10J9J8J7J6J5J4J3J2J1
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
1 --> REM0 --> LOC
REM/LOC JTAGBYPASS DPRAM
PAGE 20 LOCAL JTAG CONNECTOR, GENELAR PURPOSE DIP SWLAST_MODIFIED=Tue May 30 11:11:48 2017
20/31
Project file:pcieppc.cpm
20/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
100nF
100nF
VCC=P2V5GND=DGND
TSSOP
4.7K
4.7K
220
NC7SV19P6X
SC70GND=DGNDVCC=P2V5
74VHC157MTC
57202-G52-07LF
HSMH-C170
4.7k
4.7k
1%
1206_TC164
4.7k1%
1206_TC164
C139
C151
IC48
IC49
RN7
LD3
R49
R197
SW1
RN8
SW2
R196
RN4
J4
JTAG_SEL
JTAG_SEL
LOC_TCK
FPGA_TDI
FPGA_TCK
DPRAM_TDO
REM_TDO
LOC_TDOLOC_TDI
LOC_TDO
FPGA_TDO
DPRAM_TDO
LOC_TDIREM_TDI
FPGA_TMS
LOC_TCKREM_TCKLOC_TMSREM_TMS
LOC_TMSSW_DIP_0SW_DIP_1SW_DIP_2SW_DIP_3SW_DIP_4SW_DIP_5SW_DIP_6SW_DIP_7
REM_TDIREM_TCKREM_TMSREM_TDO
9
12
7
4
1
10
13
6
3
11
14
5
2
15
46
31
5
6
7
8
4
3
2
1
24
13
161514131211109
1 2 3 4 5 6 7 8
246810121416
13579
111315
5 6 7 8
4 3 2 1
1413121110987654321
P2V5
DGND
P2V5
DGND
DGND
DGND
DGND
P2V5
P2V5
DGND
I1DI0DI1CI0CI1BI0BI1AI0A
ZC
ZD
ZA
ZB
SE*
Y1Y0
E*A
P2V5
P2V5
13
657 8
10911 12
1413
42
P2V5
DGND
P2V5
DGND
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
DUAL PRECISION TDC
8/16 MBIT BOOT FLASH
PAGE 21 DIAL TDC AND P3V3 TO P2V5 LOGIC TRANSLATORSLAST_MODIFIED=Tue May 30 11:11:49 2017
21/31
Project file:pcieppc.cpm
21/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
74ALVC164245DGG
(P2V5:31,42)
(P3V3:7,18)
GND=DGND
TSSOP
(GND:4,10,15,21,28,34,39,45)
74ALVC164245DGG
(P2V5:31,42)
(GND:4,10,15,21,28,34,39,45)
TSSOP
GND=DGND
(P3V3:7,18)
33
33
100nF
GND=DGND;VCC=P2V5
100nF
P3V3
P3V3
100nF
100nF
100nF
100nF
100nF
100nF
P3V3
P3V3
100nF
P3V3
P3V3
100nF
100nF
P3V3
100nF
P3V3 P3V3
33
33
QFNTDC-GP2
C69
C68
C60
C59
C71
C70
C63
C62
C342
C343
C344
C66
IC39IC40
IC41
R166
R165
R164
R167
IC42
TDC_EN_STOP2TDC_EN_STOP1
TDC_SSNFPGA_SYNC_PLL SYNC_PLL
PLL_LOS
PCIE_PERST
AO_PMB_ALERT
FPGA_PLL_LD PLL_LDTDC_INTN
PCIE_WAKE
TDC_EN_START
BOOT_FLASH_SI BOOT_FLASH_SO
BOOT_FLASH_RESET
BOOT_FLASH_SCK
FPGA_TDC_INTNFPGA_PLL_LOSFPGA_PCIE_WAKEFPGA_PCIE_PERSTFPGA_TDC_SOFPGA_AO_PMB_ALERTFPGA_PWUP_RESET
TDC_SO
PWUP_RESET
TDC_INTNTDC_SO
TDC_STOP1
TDC_SITDC_RESET
TDC_START
PLL_UWIRE_CLKPLL_UWIRE_DATAPLL_UWIRE_LEPLL_GOE
TDC_EN_STOP2TDC_EN_STOP1TDC_STOP2
TDC_STARTTDC_STOP1
TDC_RESETTDC_CLKREFTDC_EN_START
FPGA_PLL_UWIRE_CLKFPGA_PLL_UWIRE_DATAFPGA_PLL_UWIRE_LEFPGA_PLL_GOE
FPGA_TDC_EN_STOP2FPGA_TDC_EN_STOP1FPGA_TDC_STOP2
FPGA_TDC_STOP1FPGA_TDC_START
FPGA_TDC_CLKREFFPGA_TDC_EN_START
FPGA_TDC_RESETTDC_SIFPGA_TDC_SITDC_SCKFPGA_TDC_SCKTDC_SSNFPGA_TDC_SSN
TDC_CLKREF
TDC_SCK
TDC_STOP2
5
812
34
2524
2322201917161413
2627293032333536
481
1211986532
3738404143444647
2524
2322201917161413
2627293032333536
481
1211986532
3738404143444647
2
1
273031
9
12
11
17
10
13
19202324
188
765
2526
32
15
16
DGND
P2V5
DGND
DGND
P2V5
DGND
DGND
P2V5
P2V5
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
P2V5
AT45DB161D
SO
WP*
CS*RESET*
SCKSI
DGND
DGND
P2V5
1DIR
1B<3>
1B<4>
1B<5>
1B<6>
1B<7>
2OE
2B<0>
2B<1>
1OE
1B<0>
1B<1>
1B<2>
2B<2>
2A<1>
2A<0>
2DIR
1A<7>
1A<6>
1A<5>
1A<4>
1A<3>
1A<2>
1A<1>
1A<0>
2B<3>
2B<4>
2B<7>
2B<6>
2B<5>
2A<7>
2A<6>
2A<5>
2A<4>
2A<3>
2A<2>
P2V5
DGND
P2V5
DGND DGND
1DIR
1B<3>
1B<4>
1B<5>
1B<6>
1B<7>
2OE
2B<0>
2B<1>
1OE
1B<0>
1B<1>
1B<2>
2B<2>
2A<1>
2A<0>
2DIR
1A<7>
1A<6>
1A<5>
1A<4>
1A<3>
1A<2>
1A<1>
1A<0>
2B<3>
2B<4>
2B<7>
2B<6>
2B<5>
2A<7>
2A<6>
2A<5>
2A<4>
2A<3>
2A<2>
EN_STARTSTARTSTOP1STOP2EN_STOP1EN_STOP2PT1PT2
LOADTSENSETCLK32IN
CLK32OUT
RSTN*
SO
SISCKSSN*
INTN*
FIRE_IN
FIRE1
XOUT
XIN
PT3PT4
GND[3]
VIO[2] VCC[2]
FIRE2
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PAGE 22 I2C CONTROL BUS, I/O EXPANDERS AND LED DRIVER
ADDR = $24
ADDR = $25
ADDR = $26
LAST_MODIFIED=Tue May 30 11:11:49 201722/31
Project file:pcieppc.cpm
22/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
1206_TC164
GND=DGND
PCA9306DCT
200K
200K
1%
1%
PCA9306DCT
SSOP/DCT
1206_TC164
1%
4.7k
1%
4.7k
I85
100nF16V_GEN
100nF
I83
I84
P3V3
100nF
P3V3
SSOP/DCTGND=DGND
100nF
100nF
100nF
P3V3
100nF
R45
R46
IC50
IC54
IC47
C164
C156
C154
C152
C155
C153
C103
RN12
RN10
IC56
IC55
FPGA_CTL_SCL
CR0_CONF
CR1_SIN0CR1_SIN1CR1_SOUT0CR1_SOUT1CR1_LOADCR1_CONF
DLY_5DLY_6
CR0_LOADCR0_SOUT1CR0_SOUT0
CTL_SDACTL_SCL
SW_DIP_3
DLY_10DLY_9DLY_8
DLY_3DLY_4
LEN1LEN0
DLY_7
DLY_2DLY_1DLY_0
SW_DIP_7SW_DIP_6SW_DIP_5SW_DIP_4
SW_DIP_2SW_DIP_1SW_DIP_0
ADC_SEL1ADC_SEL0MGTFO_1_SELMGTFO_0_SEL
CR0_SIN1CR0_SIN0
AO_CTL_SCL
CTL_SDA
CTL_SCL
FPGA_CTL_SDA
FPGA_AO_CTL_SDA
FPGA_AO_CTL_SCL
AO_CTL_SDA
1224
2322
2019181716151413
1110987654
1
3221
1224
2322
2019181716151413
1110987654
1
3221
1224
2322
2019181716151413
1110987654
1
3221
5 6 7 8
4 3 2 1
5 6 7 8
4 3 2 1
72
54
63
8
72
54
63
8
P2V5
PCA9555PW
A2
IO2_7IO2_6IO2_5IO2_4IO2_3IO2_2IO2_1IO2_0
IO1_7IO1_6IO1_5IO1_4IO1_3IO1_2IO1_1IO1_0
INT*
SDASCL
A1A0
VSSVDD
PCA9555PW
A2
IO2_7IO2_6IO2_5IO2_4IO2_3IO2_2IO2_1IO2_0
IO1_7IO1_6IO1_5IO1_4IO1_3IO1_2IO1_1IO1_0
INT*
SDASCL
A1A0
VSSVDD
PCA9555PW
A2
IO2_7IO2_6IO2_5IO2_4IO2_3IO2_2IO2_1IO2_0
IO1_7IO1_6IO1_5IO1_4IO1_3IO1_2IO1_1IO1_0
INT*
SDASCL
A1A0
VSSVDD
P2V5
P2V5
P2V5
DGND
DGND
P2V5
P2V5
DGND
DGND
DGND
DGND
DGND
P2V5
P2V5
P2V5
VREF1
SCL1
SDA1 SDA2
SCL2
EN
VREF2
P2V5
DGND
DGND
DGND
VREF1
SCL1
SDA1 SDA2
SCL2
EN
VREF2
P2V5
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
ADDR = $4B
ADDR = $18
ADDR = $4A
+12v Current
+2.5v Current
+2.5v Current
+5v Current
ADDR = $49
ADDR = $48
+3.3v Current
+1.2v Current
+1.5v Current
PAGE 23 I2C SYSTEM MONITOR BUS. TEMPERATURE SENSORS
ADDR = $35
ADDR = $6B
+1.0v Current
EDA-02264-V4-0
DATE: 24/05/2017
LAST_MODIFIED=Tue May 30 11:11:49 2017
PROJECT:GGP23/31
Project file:pcieppc.cpm
PCB by: PV
23/31
SYSTEM: 16.03
Design by: R.Isocrate
MODULE:pcieppc
100nF
100nF
P3V3
GND=DGNDSSOP/DCT
PCA9306DCT
1%
200K
200K
1%
100nF
0R0
GND=DGND;VS=P3V3MAX6626PMTT+
TDFN
P3V3 P3V3
GND=DGND;VS=P3V3MAX6626PMTT+
TDFN
GND=DGND;VS=P3V3MAX6626PMTT+
TDFN
TDFN
GND=DGND;VS=P3V3MAX6626PMTT+
1206_TC164
1%
100nF
1206_TC164
1%
4.7k
4.7k
MAX809SN160T1G
GND=DGND;VCC=P3V3
100nF
0R0
0R0
0R0
0R0
0R0
0R0
0R0
P3V3
P3V3
100nF
P3V3
P3V3
P3V3
DS1682S+
PCA9306DCT
P3V3
SSOP/DCTGND=DGND
100nF
P3V3
100nF
100nF
P3V3
P3V3
100nF
100nF
1.0K
1.0K
1.0K
1.0K
1.0K
1.0K
1.0K
1.0K
10NF
10NF
10NF
10NF
10NF
10NF
10NF
10NF
IC22
IC27
IC53
IC1
R24
R25
C362
C230
C363
C78
C364
C288
C285
C80
C79
C95
C96
IC17
C559
C563
C562
C558
C561
C556
C557
C560
RN9
IC51RN11
IC21
IC45
R235
R236
R226
R225
R228
R227
R233
R234
R231
R232
R239
R240
R237
R238
R230
R229
IC52
IC44
FPGA_PMB_SDA
FPGA_PMB_SCL
PMB_SDA
PMB_SCL
VCC0_CSSM_IN_0_P
PWUP_RESET
SW_DIP_0
VCC0_S_P
SM_IN_3_N
SM_IN_7_N
SM_IN_6_N
SM_IN_5_N
SM_IN_4_N
SM_IN_2_N
SM_IN_1_N
SM_IN_0_N
FPGA_AO_PMB_SCL
FPGA_AO_PMB_SDA
VCC3_CS
VCC5_CS
SM_IN_5_P
VCC7_S_P
VCC5_S_P
VCC3_S_PVCC2_S_P
SM_IN_3_P
VCC9_S_PVCC8_S_P
PMB_SDAPMB_SCL
AO_PMB_SDA
AO_PMB_SCL
VCC4_S_P
VCC1_S_P
VCC1_CS
VCC6_CS
VCC7_CS
VCC8_CS
FPGA_DXP
FPGA_DXN
VCC6_S_P
VCC4_CS
SM_IN_1_P
SM_IN_2_P
SM_IN_4_P
SM_IN_6_P
SM_IN_7_P
1
3
4
5
1
3
4
5
1
3
4
5
1
3
4
5
16
1413
15
34121110987
2
65
1
5 6 7 8
4 3 2 1
72
54
63
8
5 6 7 8
4 3 2 1
3 2
1
651 3
72
54
63
8
2
15
12
14
3
4
11610
DGND
DGND
MAX11611
VDDGND
SDASCL
AIN_7AIN_6AIN_5AIN_4AIN_3AIN_2AIN_1AIN_0
AIN_8AIN_9AIN_10A1N_11
DGND
DGND
MAX1617A
VCC
SMBDATAALERT*
SMBCLK
STBY*
ADD1ADD0
DXN
DXP
GND<1-0>
P2V5
VREF1
SCL1
SDA1 SDA2
SCL2
EN
VREF2
P2V5
GND
VCC RESET
ALARMSDA
EVENTSCL
DGND
DGND
DGND
VREF1
SCL1
SDA1 SDA2
SCL2
EN
VREF2
P2V5
OTADD
SDASCL
OTADD
SDASCL
OTADD
SDASCL
OTADD
SDASCL
ALIAS
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
ADDR = $12
1MHZ 20%SSP3 PHASES 33DEGREE
P2V5P1V5P3V3
2 VCCAUX 20MS
MGTVTT
PAGE 24 POWER SUPPLY SYSTEM CONTROLLERS
3 MGTVCC
1 VCCINT 30MS RAMP
POWER UP SEQUENCE:
500KHZ
ADDR = $7E
LAST_MODIFIED=Tue May 30 11:15:24 201724/31
Project file:pcieppc.cpm
24/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
10K
1%
4.7k
100nF
100nF
1206_TC164
1%
4.7k
1206_TC164
1%
4.7k
1206_TC164
1%
4.7k
0R0
0R0MOUNTED=NO
MOUNTED=NO
4.7UF
SMD
(26,27,29,35,41,49,76,77,78,81,99,100,44,59)
R
HSMF-C114
B
G
ISPPAC-POWR1220AT8-01TN100I
4.7K
I128
FCX491A
10K
15K
6.65k1/16W
100nF
NC7SZ74K8X
TQFP
GND=DGND;VCC=P3V3
100NF
100NF
4.7K
1/16W1%
4.7k
4.7k1%
1/16WMOUNTED=NO
1/16W
100nF
US8
4.7k1%
1%
1/16W 1%6.65k
1%
LTC6902IMS
VCCPROG 100nF
P3V3
330
0R0
4.7K
0R0
82k
1%
VCCPROG
10UF
MSOP
10NF
GND=DGND
100nF
1/16WMOUNTED=NO
2.4K
R141
LD2
ST3
IC35
R153
R148
R147
R152
R139
R138
C226
C225
C222
C223
C303
C304
R151
T2
IC33
R149R142
R143
RN1
R158
ST2
R159
R145
R144
ST4
IC34
RN3
RN2
IC37
C306
C228
C229
R150
R50
R51
C307
R146
C305
TI_GOOD
TI_TDI
VCC4_ADJVCC3_ADJ
TI_ENABLE
TI_TRST
VCC2A_EA_NVCC3_RUN
VCC10_RUN
VCC2_TEMP
PMBUS_ALERTPMB_SDAPMB_SCL
TI_RESET
VCC2A_FAULTVCC2A_SREVCC2A_PWM
TI_TCKTI_TDI
TI_TMS
VCC2A_EA_P
PMB_SDAPMB_SCL
VCC2_S_N
VCC3_S_NVCC4_S_PVCC4_S_N
VCC9_RUN
VCC6_S_NVCC7_S_PVCC7_S_N
VCC11_RUNTI_RESET
VCC2A_CS
VCC4_RUN
VCC2_S_P
VCC8_ADJ
VCC7_RUNVCC5_RUN
VCC2_INH
PMBUS_ALERTPOWER_OK
VCC8_RUN
VCC6_RUN
TI_GOOD
VCC1_S_NVCC1_S_PVCC0_S_N
VCC2_S_N
VCC0_S_P
VCC3_S_PVCC8_S_NVCC8_S_P
VCC6_S_PVCC5_S_NVCC5_S_P
VCC7_ADJVCC6_ADJVCC5_ADJ
VCC2_S_P
LAT_TCKLAT_TMS
TI_ENABLETI_TDI
TI_TCKTI_TMS
TI_TDO
VCC2_CK
POWER_OK
LAT_TDO
LAT_TCK
PMB_SCL
PMBUS_ALERT
TRIM_LOCK
POWER_OK
LAT_TDOLAT_TDI
LAT_TMS
LAT_TDI
TI_TDO
PMB_SDA
4
3
2
1
45
4
41
33
34
31
2423
30
46
282927
17
15
18
9
2221
5
1110
20 19
26
25
8
7
6
49
39
37
40
38
16
14
13
12
32
1
3
2
42
35
4344
48
35
7
26
1
5 6 7 8
4 3 2 1
110
3 7654
92
5 6 7 8
4 3 2 1
5 6 7 8
4 3 2 1
9089
6566636461625758555653545152485046
717269706768
47
3933
5
60
7374757980828384
2834
3231
37
9392
91
95
12111098
2524232120191817161514
96
76421
97
40428586
30
P3V3C
P3V3C
CLR*DCKPR*
QQ*
P3V3C
DGND
P3V3C
PAD3
P3V3C
VCC
VCC
DGND
PAD2
P3V3C P3V3C
SETV+
PHDIVMOD
OUT1
OUT4OUT3OUT2
P3V3C
P3V3C
DGND
RESETB9
MCLKPLDCLK
SCLSDA
VCCJTDO
TCKTMS
TDISELTDIATDI
IN63
IN33IN43IN53
IN23IN12
VMON12VMON12GS
VMON11VMON11GS
VMON10GS
VMON9GSVMON10
VMON9VMON8GSVMON8
VMON7VMON7GS
VMON5GSVMON6VMON6GS
VMON5VMON4GS
VMON3VMON3GSVMON4
VMON2GSVMON2
VMON1VMON1GS
VPS1VPS0
VCCINP
OUT19OUT20
OUT18
OUT16OUT17
OUT14OUT15
OUT13OUT12OUT11
OUT9OUT10
OUT8OUT7OUT6
HVOUT4
OUT5_SMBA
HVOUT2HVOUT3
TRIM8
HVOUT1
TRIM7TRIM6TRIM5TRIM4TRIM3TRIM2TRIM1
VCCPROG
VCCA7GNDA8
VCCD7GNDD8
DGND
DGND
P3V3C
AGND
DGND
DGND
DGND
+
+
DGND
DGND
P3V3C
DGND
AGND
P3V3C
P12V
DGND
PAD2
UCD9224
SEQ-1SEQ-2
EAN2
TEMP
EP
PMB_ALARM
TDO/SYNC_OUT
PMB_CNTLPMB_SDAPMB_SCL
DGND
V33FB
CS-3A
CS-1B
CS-2A
VIN
RESET*
FLT-1A
FLT-1B
FLT-2A
SRE-1ADPWM-1A
DPWM-1B
DPWM-2ASRE-2A
DPWM-3ASRE-3A
SRE-1B
TMUX-0TMUX-1
FLT-3A
PGOOD
TCKTDI/SYNC_IN
TMSTRST*
V33D V33A
BPCAP
EAP1EAN1
EAP2
CS-1A
ADDR_1ADDR_0
VTRACK
ADCREF
AGND[2..1]
DGND
P3V3C
P3V3C
P3V3C
P3V3C
P3V3C
DGND
DGND
DGND
DGND
DGND
DGND
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
100.6MV/A
100.6MV/A
VCCINT FPGA 1.0V@20A
PAGE 25 INPUT POWER CONNECTOR AND 12-1 DC-DC CONVERTER
1 - YELLOW +12V
SCALE BY 3
SCALE BY 2
2 - BLACK GROUND3 - BLACK GROUND4 - RED +5V
MOLEX 8981
INTERMEDIATE BUS POWER +12.0V
INTERMEDIATE BUS POWER +5.0V
LAST_MODIFIED=Tue May 30 11:25:09 2017
Project file:pcieppc.cpm
25/31
PROJECT:GGPMODULE:pcieppc
Design by: R.Isocrate
SYSTEM: 16.03
25/31
PCB by: PV DATE: 24/05/2017
EDA-02264-V4-0
1W_TL
US8
GND=DGND;VCC=P2V5
NC7NZ14K8X
SMAJ13ASMAJ6.5A
SMD
BNX022-01
SMD
BNX022-01
1W_TL0.005
1W_TL0.005
0.005
MOUNTED=NO
MOUNTED=NO
MSOP
220UF
INA333AIDGK
100nF
5.1K
100nF
5569-4A2
P5V
TSW-103-23-L-S
1.0K
0R0
3.9k1.0k
820PF
0R0
2.0K
820PF 1.0K
0R0
1.0K
P5V
MOUNTED=NO
0R0
820PF
PTD08A020WAD
1.0K
5.1K
220UF
22K
1500uF
100nF
IHLP-2525CZ-01
MSOP
VCCPROG
330uF
22uF
P5V
INA333AIDGK
0.22UH
0R0
750
INA118U
SOIC
P5V
20021121-00020T4LF
IC23
L6
L12
D1D2
IC24
R52
R53R54
R155
J6
J3
C287
C44
C224
C234
C235
C50
C233
R154
C248 R56
R59
R57
C286 R116
R115
R114
IC18
C309 R156
R140
IC36
R17
R157
L14
C227
J5
R117
IC32
R16
R58
R14
FAN_SPEED_INVCC2A_EA_P
VCC0_CS
VCC1_S_N
VCC1_S_P
VCC0_S_N
VCC0_S_P
VCC2_TEMP
VCC2A_FAULT
VCC2A_EA_N
VCC2A_CS
VCC2A_SREVCC2A_PWM
VCC2_INH
VCC1_CS
PMB_SCLPMB_SDAPMBUS_ALERTTI_ENABLE
TI_TMSTI_TCKTI_TDOTI_TDI
LAT_TMSLAT_TCKLAT_TDOLAT_TDI
6 2
3
21
3
21
6
2
3
47
8
1
5
321
2019181716151413121110987654321
41
12
51011
68
9
7
6
2
3
47
8
1
5
4321
6
2
3
47
8
1
5
21
21
VCC
+
++
P12V
DGND
DGND
DGND
DGND
DGND
DGND
P12V
DGND
DGND
VO
TEMP
VI
INH
GND[2] AGND
PWMSRE
VBIAS
IOUT
FAULT
V+ V-
REF
VOUT
VIN+RG
VIN-RG
DGND
DGND
+
P1V0
P12V
321
4
V+ V-
REF
VOUT
VIN+RG
VIN-RG
DGND
DGND
CG[3]
B
PSG
CB
CG[3]
B
PSG
CB
DGNDDGND
RGVIN-
RGVIN+
VOUT
REF
V-V+
DGND
YA
DGND
P12V
DGND
P12V
3
12
DGND
2018
10121416
1917
97
111315
531
8642
DGND
DGND
DGND
P3V3C
P3V3C
DGND
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
(TRIM_1)
560K-330NF --> RAMP 22MSEC
(TRIM_2)
VCCAUX FPGA 2.5V@8A
VCC I/0 FPGA/CROSSBARS 2.5V@8A
PAGE 26 DC-DC CONVERTER 5-2.5 (VCCAUX) AND 5-2.5 (P2V5)
LAST_MODIFIED=Tue May 30 11:26:00 201726/31
Project file:pcieppc.cpm
26/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
1W_TL0.005
1W_TL0.005
MOUNTED=NO MOUNTED=NO
22K
820K
3.09k
220PF
VCCAUXMOUNTED=NO
22K
MOUNTED=NO
MOUNTED=NO
MOUNTED=NO
INA333AIDGK
MSOP
100UF
100UF
1.0K
IHLP-2525CZ-01
IHLP-2525CZ-01
VCCAUX
1.0K
330NF
100KVOUT4
3.09k
100UF_X5R
P5V
2773021447 VIN3
0.22UH
0.22UH
INA333AIDGK
MSOP
P5V
P5V
100NF
220UF
P5V
220UF
P5V
820PF
560K
LTM4608EV
LGA
0R0
820PF
VOUT3
750
7502773021447 VIN4
100NF
P5V
100NF
SMD
220PF
VOUT4
VOUT3
100nF
100K
100UF_X5R
MOUNTED=NO
10UF
100K 100K
100UF_X5R 100UF_X5R
0R0
43K
0R0
100nF
5.23k
5.23k
1500uF
1500uF
VIN3
22K
MOUNTED=NO
22K
LTM4608EV
10UF
100NF
0R0
100K
51K
1%1%
51K
100NF
51K
1%1%
51K
LGA
VIN4
R66 R67
R73R72
R122
R118
R75
R63
C47
C39
R60
R70
R64
R76
C289 R119
R120
R121
R124
C290 R123
R125
C249
C43
L5
C42
R61
C253
C36
L4
C35
R71
C251 C250
IC7
R62
R69
C255 C254
IC6
R74
R79
R65
C252
R68
C48 C45 C46
R15
R77
C256
R78
C40 C37 C38
R13
IC26
C49
L11
IC28
C41
L10
VCC4_S_N
VCC3_ADJ
VCC4_CS
VCC3_CS
VCC4_PG
VCC3_PG
VCC2_CK
VCC3_S_P
VCC4_RUN
VCC3_CK VCC4_CK
VCC4_TRK
VCC3_S_N
VCC4_S_P
VCC3_CK
VCC3_TRK
VCC3_RUN
VCC4_ADJ
E5
F4
E1
F1E3
B4
C7B5
B8
F5F6E7
F2B3
B7
E5
F4
E1
F1E3
B4
C7B5
B8
F5F6E7
F2B3
B7
6
2
3
47
8
1
5
6
2
3
47
8
1
5
P2V5
VCC
P2V5
DGND
DGND
+
DGND
DGND
DGND+
DGND
V+ V-
REF
VOUT
VIN+RG
VIN-RG
DGND DGND
GND SGND
CLKIN
MGNBSEL
PGOODITHMITHFB
VOUT
PHMODEMODETRACKPLLLPFRUNSW
CLKOUT
VINSVIN
VCC VCC
DGND
DGND
DGND DGND
GND SGND
CLKIN
MGNBSEL
PGOODITHMITHFB
VOUT
PHMODEMODETRACKPLLLPFRUNSW
CLKOUT
VINSVIN
VCC
+
VCC
DGND
VCC
VCC
DGND
DGND
DGND
+
VCC
DGND DGND
DGND
DGND
+
VCC
DGND DGND
V+ V-
REF
VOUT
VIN+RG
VIN-RG
DGND
DGND
DGND
DGND
+
DGND
DGND
DGND
DGND
DGND
DGNDVCC
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
PLL VCC 3.3V@8A
VCC DPRAM 1.5V@8A
PAGE 27 DC-DC CONVERTER 5-1.5 (VCCDPRAM) AND 5-3.3(P3V3)
TRIM 4
TRIM 3
LAST_MODIFIED=Tue May 30 11:11:51 201727/31
Project file:pcieppc.cpm
27/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
1W_TL0.005
0.0051W_TL
6.65K
36K
680K
MOUNTED=NO
1500uF
MOUNTED=NO
P3V3
MOUNTED=NO
220PF
16K
2.2K
100UF_X5R 100UF_X5R MOUNTED=NO
0.22UH
8.2M
1500uF
MOUNTED=NOMOUNTED=NO
MOUNTED=NO
INA333AIDGK
MSOP
100UF
IHLP-2525CZ-01
100nF
100UF
820PF 750
IHLP-2525CZ-01
820PF
51K
100NF 100NF
100NF
VOUT2
1%
2773021447
100K
VIN2 VIN2
100NF 100NF
LTM4608EV
100K
100K
P5V
MSOP
INA333AIDGK
P5V
2773021447
220PF
P5V
P3V3
50V
0.22UH
100K
VOUT2
VOUT1LGA
VIN1VIN1
100NF
P5V
0R0
0R0
750
VOUT1
100nF
100K
P5V
LTM4608EVLGA
MOUNTED=NO
10UF
1.0K
0R0
100UF_X5R 100UF_X5R
10UF220UF
0R0
1.0K
5.23k
5.23k
100K
91K
24K
51K
1%
51K
51K
1% 1%
220UF
P5V
R102 R103
R176 R177
R134
R184R182
C17
C240
R101
R175
R105
R181
C296 R135
R137
R136
C359 R185
R186
R187
C265
C14
L1
C13
R100
C355
C237
L15
C236
R174
C267 C266
IC3
R104
R109
C357 C356
IC20
R178
R183
R106
R107
C268
R108
C19 C15 C16
R10
R179
C358
R180
C241 C238 C239
R55
IC31
C20
L7
IC43
C242
L16
VCC5_S_N
VCC5_S_P
VCC5_CS
VCC6_TRK
VCC6_CS
VCC6_S_N
VCC4_CK
VCC5_CK VCC6_CK
VCC5_CK
VCC5_PG
VCC5_RUN
VCC6_RUN
VCC5_ADJ
VCC6_PG
VCC5_TRK
VCC6_S_P
VCC6_ADJ
E5
F4
E1
F1E3
B4
C7B5
B8
F5F6E7
F2B3
B7
E5
F4
E1
F1E3
B4
C7B5
B8
F5F6E7
F2B3
B7
6
2
3
47
8
1
5
6
2
3
47
8
1
5
P1V5
P1V5
DGND
DGND
+
DGND
DGND
DGND+
DGND
V+ V-
REF
VOUT
VIN+RG
VIN-RG
DGND DGND
GND SGND
CLKIN
MGNBSEL
PGOODITHMITHFB
VOUT
PHMODEMODETRACKPLLLPFRUNSW
CLKOUT
VINSVIN
VCC VCC
DGND
DGND
DGND DGND
GND SGND
CLKIN
MGNBSEL
PGOODITHMITHFB
VOUT
PHMODEMODETRACKPLLLPFRUNSW
CLKOUT
VINSVIN
VCC
+
VCC
DGND
VCC
VCC
DGND
DGND
DGND
+
VCC
DGND DGND
DGND
DGND
+
VCC
DGND DGND
V+ V-
REF
VOUT
VIN+RG
VIN-RG
DGND
DGND
DGND
+
DGND
DGND
DGND
DGND
DGND
DGND
DGND
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
TRIM 5
MGT VCC 1.0V@8A
MGT VTT 1.2V@8A
TRIM 6
PAGE 28 DC-DC CONVERTER 5-1.0 (MGTAVCC) AND 5-1.2 (MGTAVTT)
LAST_MODIFIED=Tue May 30 11:11:52 201728/31
Project file:pcieppc.cpm
28/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PROJECT:GGP
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
1W_TL0.005
1W_TL0.005
1%
MOUNTED=NO
MOUNTED=NO
14k
10K
MOUNTED=NO
LTM4608EV
51K
1%
47K
MOUNTED=NO
820PF
100UF_X5R
0R0
1.0K
100UF
0.22UH
MOUNTED=NO
4.3MMOUNTED=NO
MOUNTED=NO
MOUNTED=NO
56K
100UF
IHLP-2525CZ-01
VIN8VIN8
51K
75K
MOUNTED=NO
VOUT7
VOUT8
820PF
100NF
INA333AIDGK
100K
P5V
100K
2773021447
100NF
100K
100NF
2773021447
MGT_AVCC
MGT_AVTT
MSOP
P5V
IHLP-2525CZ-01
0.22UH
MSOP
INA333AIDGK
P5V
220UF
P5V
MGT_AVTT
100K
100NF
VOUT7
VIN7
VOUT8
100NF
P5V
100K
100K
100NF
0R0
0R0
750
750
100nF
100nF
VIN7
10UF
220UF 10UF
100UF_X5R
24K
1500uF 100UF_X5R100UF_X5R
0R0
1.0K
5.6M
220PF
5.23k
5.23k
1500uF220PF
LGALTM4608EV
MGT_AVCC
51K
1%
51K
1%
LGA
P5V
R82 R83
R92 R93
R126
R130
R87
R97
R98
C32
C25
R81
R91
R86
C291 R127
R128
R129
C292 R131
R132
R133
C29
L3
C257 C259
C28
R80 R84
C22
L2
C261 C263
C21
R90 R94
C258
IC5
C260
R89
C262
IC4
C264
R99
R95
R85
R88
C33 C30 C31
IC29
R12
L9
R96
C26 C23 C24
IC30
R11
L8
C34
C27
VCC8_ADJ
VCC8_S_N
VCC7_CS
VCC8_S_P
VCC7_PG
VCC7_S_P
VCC7_CK
VCC7_RUN
VCC7_TRK
VCC8_TRK
VCC8_RUN
VCC8_CS
VCC7_CK
VCC7_S_N
DCDC_SYNC
VCC8_PG
VCC7_ADJ
VCC6_CK
1
E5
F4
E1
F1E3
B4
C7B5
B8
F5F6E7
F2B3
B7
E5
F4
E1
F1E3
B4
C7B5
B8
F5F6E7
F2B3
B7
6
2
3
47
8
1
5
6
2
3
47
8
1
5
DGND+
DGND
DGND DGND
DGND
+DGND
DGND DGND
DGND
DGND
GND SGND
CLKIN
MGNBSEL
PGOODITHMITHFB
VOUT
PHMODEMODETRACKPLLLPFRUNSW
CLKOUT
VINSVIN
VCC
DGND
VCC VCC
DGND
VCC
DGND
VCC
DGND
GND SGND
CLKIN
MGNBSEL
PGOODITHMITHFB
VOUT
PHMODEMODETRACKPLLLPFRUNSW
CLKOUT
VINSVIN
DGND
VCC VCC
DGND
DGND
VCC VCC
VCC
+
+
DGND DGND DGND
V+ V-
REF
VOUT
VIN+RG
VIN-RG
VCC
DGND
+
DGND DGND
V+ V-
REF
VOUT
VIN+RG
VIN-RG
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
+
VCC
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
DEFAULT 2-3
VREFP 1.25V
DPRAM VREF 0.75V@500MA
AVDD 2.5V
FLASH VCC 1.8V@1A
(READY IN 235US)
PAGE 29 LINEAR LDO P1V8, VREF, SMLAST_MODIFIED=Tue May 30 11:11:53 2017
29/31
PROJECT:GGP
Project file:pcieppc.cpm
29/31
Design by: R.Isocrate
EDA-02264-V4-0
MODULE:pcieppc
PCB by: PV DATE: 24/05/2017
SYSTEM: 16.03
GND=DGND
1500uF
27k
1UF
10V_GEN
4.7uF
100NF
4.7uF
10V_GEN
4.7uF
10V_GEN
82k
100nF10V
10V_GEN
4.7uF
1500uF
220UF
P5V
10UF
22nF
10UF
100K
P5V P3V3
100K
15k
10k
VREF
GND_TESTMON
GND_TESTMON
I103
LI0805H121R-10
SOT23
100NF
GND_TESTMON
1UF
LI0805H121R-10
P5V
1.0K
0R0
750
MOUNTED=NO
820PF
30k
MLF
MIC68220YML
P5V
QFNHMC976LP3E
VCC_PLL
100NF
6.8UH
330uF_R0015
C75
C81
C82
C76
R264
C579
C74
L13
C77
C73
REG1
ST1
C351
R173
R171
R172
L17
C324 C454
C54
C52
C51 C53
IC8IC38
C323
L18
R22
R18
R20
C56
R19
R21
R23
C57
VCC9_PG
TSTM_VREFP
TSTM_AVDD
VCC9_RUN
VCC9_S_N
VCC9_S_P4
11
15
3
2
5
1
3
2
1
20
15
19
14
2
7
1
6
4
9
17
12
5
10
3
8
21
18
13
21
3
DGND
P2V5
AGND
DGND
DGND
+
DGND DGND
DGNDDGND
VIN2
VOUT1
VOUT2
ADJ/SNS1
POR2
VOUT2
ADJ/SNS2
CASE
POR1
VOUT1
DELAY1
GND[2]
VIN2EN2RC2DELAY2
VIN1VIN1EN1RC1
REF3012AIDBZTIN OUT
GND
AGNDDGND
DGND
DGND
+
DGND
DGND
+
P1V8
DGND
DGND
DGND
DGND
DGND DGND DGND
+
VCC
HV
EN
REF
RD VRX
VRVDD
AGND
PAD3
P1V8
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
555,376512,419575,360 564,402456,402
555,376 559,356
454,399
523,409 563,402480,353504,405470,355
560,356565,400535,406 564,402 565,400535,388 524,353557,404570,369500,396 518,354
498,350
537,426 562,394
541,397
517,354550,399
535,405525,430516,354515,356
477,421 509,361
535,372498,418
518,406
525,406
565,401562,395548,355
PAGE 30 ANTI-RESONANCE COMPENSATION CAPACITORS 1/2
512,401 565,399
553,419516,358 481,387 464,392
548,410 565,401 553,376
565,401 565,401
518,403
559,356
520,376
LAST_MODIFIED=Tue May 30 11:11:57 201730/31
SYSTEM: 16.03
PCB by: PV
30/31
Design by: R.Isocrate
MODULE:pcieppc
EDA-02264-V4-0
DATE: 24/05/2017
Project file:pcieppc.cpm
PROJECT:GGP
4.7pF
0402
50V
25V
3.3pF
4.7pF
25V04020402
25V
4.7pF
VCCAUX
4.7pF
25V25V
040210pF 10pF
040250V 50V
0402040210pF 10pF
04024.7pF
25V
04024.7pF
25V
040225V
3.3pF
25V
4.7pF0402
0402
0402
4.7pF
0402 040210pF10pF
040225V
25V0402
0402
3.3pF
04024.7pF
25V04024.7pF
040225V
04024.7pF
25V04024.7pF
25V25V04020402
4.7pF4.7pF
25V0402
25V
4.7pF0402
25V0402
25V04023.3pF
25V04023.3pF
25V04023.3pF3.3pF 3.3pF
040225V
3.3pF0402 0402
25V 25V04023.3pF 3.3pF
040225V
3.3pF040225V25V
04023.3pF
25V0402
3.3pF040225V25V
3.3pF
25V0402
4.7pF0402
10pF
50V040210pF
50V
MGT_AVCC
VCCAUX
04024.7pF
25V25V
4.7pF
10pF040250V
10pF040250V
10pF040250V50V
040210pF
4.7pF
040250V50V
040210pF
MGT_AVCC
P3V3
P3V3
P5V
P5VVCCAUX
25V
4.7pF
25V
MGT_AVCC
50V0402
4.7pF
10pF10pF04020402
50V 50V50V
10pF
25V
4.7pF
0402
50V
10pF
50V
C312
C315C310
C574 C269 C330
C205 C367
C572
C11 C513 C540 C318 C64C221C328C163C302
C293 C169C165 C353 C300 C150
C332 C161 C453 C542 C168C313 C459 C327 C573 C331C325C564C58C159C575
C317C314C208C167C61C166C368C316C322C502C65C67C121C329C18
DGND DGND DGNDDGNDDGNDDGNDDGND
DGND DGNDDGND DGND DGND DGND
DGND DGND DGND DGND DGNDDGND DGND DGND DGND DGNDDGNDDGNDDGNDDGNDDGND
P2V5
DGNDDGNDDGND DGND DGNDDGNDDGNDDGNDDGNDDGNDDGNDDGNDDGNDDGNDDGND
DGND
DGNDDGND
VCC
VCCP2V5
VCC
P2V5VCC
VCCVCC
DGND DGND DGND
DGND DGND
DGND
DGND DGND
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
488,446 605,369628,354
513,355 610,390
PAGE 31 ANTI-RESONANCE COMPENSATION CAPACITORS 2/2
481,397518,433
555,376503,391
474,395
464,448 565,399 446,448 506,447 555,398 549,404
517,391
559,356
481,408 556,380558,388498,438526,398503,422483,401
562,394
512,448
459,355
492,425
563,403
480,404 616,429 487,394 490,442 498,438 534,417 547,417 559,397 628,354 425,350 606,370 612,441 518,433 625,447
491,442 503,426 487,394 424,349 612,443 498,437 561,401 484,402 558,403 509,418 626,448 523,432
532,420 533,416 532,417 431,376 556,381560,394
544,353
510,418
477,387
LAST_MODIFIED=Tue May 30 11:11:58 2017
Project file:pcieppc.cpm
30/30
PCB by: PV DATE: 24/05/2017
30/30
SYSTEM: 16.03
Design by: R.Isocrate
MODULE:pcieppc
EDA-02264-V1-0 PROJECT:GGPPROJECT:GGPEDA-02264-V4-0
MODULE:pcieppc
Design by: R.Isocrate
SYSTEM: 16.03
31/31
PCB by: PV
31/31
Project file:pcieppc.cpm
100nF
040250V0402
10V
100nF
MGT_AVCC
MGT_AVCC
MGT_AVCC
22pF040250V
P5VP5V P3V3P3V3
MGT_AVCC
22pF040250V50V50V 50V
040222pF
50V
100nF
10V
330pF330pF 330pF 330pF
68pF
330pF
100nF
10V
10V
10V
100nF
10V
100nF
100nF
10V
100nF
10V
100nF
10V
100nF
10V
100nF
10V
100nF
10V
100nF
10V
100nF
10V
100nF
10V
100nF
10V
10V
100nF
10V
100nF
10V
100nF
10V
100nF
10V
100nF
50V330pF50V
330pF50V50V
330pF50V
330pF50V
330pF50V
330pF50V
330pF50V
330pF50V50V 50V 50V
330pF
50V0402
50V
68pF0402
50V
68pF0402
50V
68pF0402
50V
68pF0402
50V
68pF0402
50V
68pF0402
50V
040250V
22pF040250V
50V50V50V50V
040250V
040250V50V
04020402 040222pF
50V
040222pF 22pF
0402 040222pF
040222pF22pF
22pF22pF040222pF22pF22pF22pF 22pF
C372
C447
C6
C295
C299
C298
C348
C346
C321
C10
C243
C270
C231
C245
C281
C320
C360
C350
C282
C8
C232 C246 C7 C244C12 C297 C294 C370 C361C280C284C349C247C55
C452C373C301C279C72C9
C319
C354 C271 C352C335 C345
C511 C541C375 C326C273C204C369 C308C311C162
C283
C347
C340
TSTM_VREFP
TSTM_AVDD
TSTM_AVDD
TSTM_VREFP
DGNDDGNDDGNDDGND
DGND DGND DGND DGNDDGND DGND DGND DGND DGNDDGND
DGND
DGNDDGNDDGNDDGND
DGNDDGND DGNDDGNDDGNDDGNDDGND
DGND
DGND DGND DGNDDGND DGND
DGND DGNDDGND DGNDDGNDDGNDDGNDDGND DGND
P2V5
VCC
VCC
VCC
DGND
P2V5P1V5
VCC
DGND DGNDDGND DGND DGND DGND DGND
DGND
DGND DGND DGND DGND DGNDDGND DGND DGND DGND
Project:
1211 GENEVA 23SWITZERLAND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
Sheet:Module:European Organization
for Nuclear Research
4
TS/DEM
