PADI statusPADI status

Mircea CiobanuMircea Ciobanu

1111thth CBM Collaboration Meeting CBM Collaboration MeetingFebruary 26-29, 2007, GSIFebruary 26-29, 2007, GSI

FEE1 PADIPADI

OutlineOutline

Status of the PADI: Status of the PADI:

- electrical measured parameters- electrical measured parameters

- results in the beam test for rate evaluation- results in the beam test for rate evaluation

- preparations for beam test of - preparations for beam test of t

What to do nextWhat to do next Summary and OutlookSummary and Outlook

Measurement phase of PADIMeasurement phase of PADI• Electrical measurementsElectrical measurements• Measurements together TACQUILA3Measurements together TACQUILA3• Connection with a Diamond Detector to test inConnection with a Diamond Detector to test in

beam the rate capability and the stability of the beam the rate capability and the stability of the system in real conditions.system in real conditions.

Design phase of PADIDesign phase of PADI• Comparison NINO_FEE - FEE3Comparison NINO_FEE - FEE3• Simulations for new Preamplifier Discriminator PADISimulations for new Preamplifier Discriminator PADI

The PADI together with aThe PADI together with aSC Diamond (4 pixels) detectorSC Diamond (4 pixels) detector

PADI test PCBPADI test PCB

LVDS-PECLLVDS-PECL

Converter PCBConverter PCB

Interface PCBInterface PCB

+5V,GND,THR+5V,GND,THR

connectionsconnections

Time Output'sTime Output's

LAN-K5 cableLAN-K5 cable

~2.1m~2.1m

Connection'sConnection's

with with

SC DiamondSC Diamond

Pixel DetectorPixel Detector

Rate Histogram for 110 spillsRate Histogram for 110 spills(the beam has a fixed position)(the beam has a fixed position)

Integral numberIntegral number

of counts :of counts :pixel #1pixel #1 6.22030 x106.22030 x1066

pixel #2pixel #2 6.24211 x106.24211 x1066

pixel #4pixel #4 6.22465 x106.22465 x1066

average:average: 6.22902 x106.22902 x1066

individual error ~ +/- 0.2%individual error ~ +/- 0.2%

September 25 - 28, 2007 DresdenSeptember 25 - 28, 2007 Dresden

Summary of testsSummary of tests

The PADI design was successful The PADI design was successful tested, all channels are operational.tested, all channels are operational.

The connection of PADI with our TAQUILA3 Data Acquisition system

works properly.

The first results indicate:

Time res.(@10mV) [ps] < 10 Gain ~ 60 Bandwidth [MHz] ~ 180 Linear range [mV] ~ -5 to 5 CTRR [dB] ~ 26 - 40 CMRR [dB] > 40 Input impedance [] ~ 48 - 58 Power [mW/Ch] ~ 31

The PADI design was successful tested, together with a 4 pixels SC diamond detector. The system was stable in under beam conditions.

The AC transmission measurements shows a possible instability of the PADI preamplifier cell.

The connection of PADI with the detector is critical: the line used should have a flat frequency characteristic of the impedance to avoid particularly resonances.

If the input signal is near the threshold limit, the discriminated output signal has a very low width (~1ns). We have tried to transport such signals through a 110 twisted pair LAN-K5 cable and the channel rate limit was 1.5 x 108 hits/s.

Technological details for the direct bonding of the PADI ASIC on Technological details for the direct bonding of the PADI ASIC on the pcb. In the FOPI new START system we will test two variants: the pcb. In the FOPI new START system we will test two variants: in air bond-wires with mechanical protection and Glob Top (epoxi in air bond-wires with mechanical protection and Glob Top (epoxi

compound) protection.compound) protection.

The next step: Redesign of PADIThe next step: Redesign of PADI We started from the NINO1-CERN ASIC schematics used for We started from the NINO1-CERN ASIC schematics used for

the ALICE ToF. For a simple comparison between time over the ALICE ToF. For a simple comparison between time over threshold and Q measurement for WALK correction, we threshold and Q measurement for WALK correction, we have added an supplementary buffer block to obtain both have added an supplementary buffer block to obtain both information's: time and energy. The whole design was information's: time and energy. The whole design was matched for CMOS 0.18 matched for CMOS 0.18 m technology.m technology.

Very high time resolutionVery high time resolution Cope with pads and strips RPC'sCope with pads and strips RPC's Higher Integration Higher Integration Lower Power consumptionLower Power consumption Lower price per channelLower price per channel

PADIPADI

Design goalsDesign goals

Redesign goalsRedesign goals

1. Four channels instead of three.1. Four channels instead of three.

2. The increase of closed loop stability.2. The increase of closed loop stability.

3. The increase of bandwidth of the 3. The increase of bandwidth of the preamplifier cell.preamplifier cell.

The redesign work can be finished at the The redesign work can be finished at the end of May and the layout at the end end of May and the layout at the end of July.of July.

Preamplifier: AC equivalent diagramPreamplifier: AC equivalent diagram

t ~√Nd /(As*√BW)

September 20-22, 2006 StrasbourgSeptember 20-22, 2006 Strasbourg

OutlookOutlook

To make tests together with the standard RPC detector.To make tests together with the standard RPC detector. We are ready to connect the PADI test plate with the new generation We are ready to connect the PADI test plate with the new generation

of TAC.of TAC. It is the necessary to evaluate QDC versus ToT methods for charge It is the necessary to evaluate QDC versus ToT methods for charge

evaluation before the redesign of PADI!evaluation before the redesign of PADI! To redesign PADI for a 4 channel variant, and to take into account the To redesign PADI for a 4 channel variant, and to take into account the

following:following:

- Special simulations of the system stability to be above the - Special simulations of the system stability to be above the suspicious of instability.suspicious of instability.

- The increase of PADI preamplifier - discriminator actual bandwidth is - The increase of PADI preamplifier - discriminator actual bandwidth is a hard task, but we will try to evaluate the limit of the used a hard task, but we will try to evaluate the limit of the used architecture. We will focus on the reduction of the parasitic architecture. We will focus on the reduction of the parasitic capacitances present at the preamplifier input and output ports capacitances present at the preamplifier input and output ports which in this moment dominates. which in this moment dominates.

We acknowledge the support of the European We acknowledge the support of the European Community- Community-

Research Infrastructure Activity under the FP6 Research Infrastructure Activity under the FP6

"Structuring the European "Structuring the European Research Area" programme Research Area" programme (HadronPhysics, contract number RII3-CT-2004-506078).(HadronPhysics, contract number RII3-CT-2004-506078).