Pactron Ate Introduction

EMS Solutions, Moving from Mind to Market


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About Pactron Founded in 1988 Headquarters in Sunnyvale, CA

Support centers in Dallas & Penang

Design Centers in India

PCBA Engineering, Design, & Manufacturing Semiconductor related services

Telecom, industrial & medical

Registered to ISO9001 Diversified and long standing customer base

Pactron Confidential


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The Pactron Team Designers: (Calif. & India)

Utilize at least 12hr+ days, enabling customers to get designs done faster.

Approximately 50+ designs a month with room to increase capacity! Dedicated Scalable Team for Texas Instruments

Which in turn gives you zero wait time, no queue!

Engineering: (Calif. & India)Applications plays a key role!!

• Technical Interface between the customers & Pactron

• Provide Project Management ~ single point of contact

Manufacturing: Handle High Layer count boards: 50layers .325” thick

Hybrid materials…Rogers/ Nelco / Gtek /FR-4

Complete coordination with FAB, parts procurement, and assembly & test



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Broad Product Range Product Evaluation Boards

Reference Designs Validation Boards Evaluation / Demo Kits Emulation Boards

TIU Boards Test Load Boards DUT Cards ESD Test Boards

Characterization Boards System Boards

Motherboards / PCI Cards Power supply and driver boards System Integration / Box Build Flex Circuits



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Pactron’s End to End Services

DesignLayout

SimulationAnalysis

PartsProcurement

PCB Fab/Assembly

TestSchematicCapture

•Orcad

•Concept

•DX Designer

•WG2K

•Allegro

•Expedition

•PADS

•Altium

•Ansoft HFSS - 3D Modeling •HSPICE•SpectraQuest

•PowerPlane

Analysis

•Parts Sourcing

•Inventory Mgmt.

•SMD & PTH

•BGA/Fine Pitch

•X-Ray Inspection

•AOI

•Functional

•Boundary Scan

•Flying Probe

•Planarity


Design & Engineering Manufacturing


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Typical Design Flow


Customer Input (Schematic or Block

Diagram or Pin List)

Schematic and BOM

Generation

Routing Guidelines

and Stack-up

Placement

RoutingIPC Check and Gerber

Out

Customer Approval

Customer Approval

Parts Procurement (Newark)

Signal Integrity Simulations


Pactron Signal Integrity Expertise

7Pactron Confidential


Challenges for High-end Designs

• Stack-Up -- Dielectric Material Selection

• Interconnect design ~ 50 ohms (Via/Connector Modeling)

• Routing challenges ~ BGA ~ fine pitch

• Stub reduction – back drill vias/blind vias

Pactron Confidential 8


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Signal Integrity Analysis

High Speed Channel Simulation – Modeling

• Ansoft’s High Frequency Structural Simulator (HFSS) for S/Y/Z Parameter Extraction• 3D Full-Wave Finite Element Method is used to extract electrical behavior of high frequency components • Optimized footprint for SMA, Connectors, Contactor• Optimized via structure – anti-pad, spacing to ground vias dimensions• Ansoft SI Wave for any 2D extraction including traces



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Differential Via Optimization



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Insertion Loss of differential via



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Single ended via optimization



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Insertion Loss of single ended via



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S Parameter Extraction with SMA Connector Model



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Measured and Simulated Co-Relation



Differential Pair – S Parameter


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Sample SMP Connector Footprint



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High Speed Channel Analysis -- Next Steps

• Synopsys HSPICE Circuit Simulator for complete Channel Analysis• Eye-Diagrams • Jitter Measurement • Bit Error Rate• W-Element Modeling



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Signal Integrity AnalysisPre Layout Simulation

• Cadence SigXplorer Simulation Tool

• Analyze and simulate different topologies, termination schemes and I/O buffer selection for critical nets at desired frequency

• Provide placement and routing guidelines based on pre-layout analysis

Post Layout Simulation

• Setup board file with layer stack-up information

• Extract topology along with via models from the layout file for critical nets

• Perform simulation to match results from pre-layout analysis

• Perform Crosstalk analysis on critical nets

• System Level Simulation involving board to board interconnectsPactron Confidential


Pre-Layout Analysis (Topology)



Pre-Layout Analysis (Waveform and Results)



Post-Layout Analysis (Extracted Topology)



Post-Layout Analysis (Waveform and Results)



Post-Layout Crosstalk (Results)



Pactron Sample Designs Final Test Boards Wafer Probe Boards Reference/Evaluation Boards Characterization Boards



Pactron Sample Designs

Final Test Boards



ETS-364 Mixed Signal Board

LAYERS : 18

BOARD THICKNESS : 0.187”

8 Sites

Tester Resources used

APU, SPU, QTMU, Digital IO

Force and Sense Routing

Digital IO signals routed in a separate layer with 50ohm impedance



LAYERS : 14


4 Sites


APU, SPU, Digital IO





LAYERS : 12


2 Sites


APU, SPU, Digital IO





LAYERS : 14


3 Sites








LAYERS : 16

BOARD THICKNESS : 125 mils







ETS-500 MIXED SIGNAL BOARD

LAYERS : 8


2 Sites

Tester Resources

SPU, APU. QTMU, IO, MPU


Analog and Digital Signal separation

50ohm impedance



ETS-564 MIXED SIGNAL BOARD

LAYERS : 8


2 Sites

Tester Resources

SPU, APU. QTMU, IO, MPU



50ohm impedance



VLCT RASP Final Test Board

LAYERS : 32


8 Sites

Tester Resources



50ohm impedance

Digital traces are length matched


VLCT RASP Final Test

LAYERS : 14


2 Sites

Tester Resources



50ohm impedance




LAYERS : 24


2 Sites

Tester Resources



50ohm impedance




LAYERS : 8


2 Sites

Tester Resources



50ohm impedance




LAYERS : 18


2 Sites

Tester Resources



50ohm impedance



Final Test FUSION Board

LAYERS : 24


4 Sites

50ohm impedance

Pin swapped for better routing


Final Test FUSION Board

LAYERS : 14


2 Sites

50ohm impedance

Pin swapped for better routing


Final Test HFI Board


LAYERS : 12


2 Sites

3.5Gb/s High speed signals

Via back drills

50ohm impedance




LAYERS : 12


single site

3.5Gb/s High speed signals routed onthe top

Via back drills

50ohm +/- 5% impedance




LAYERS : 12


Quad Site


Via back drills

50ohm impedance




LAYERS : 16


Quad Site


Via back drills

50ohm impedance


Teradyne FLEX BOARD

LAYERS : 12


MATERIAL : FR4

2 Sites

Tester Resources

DC75, DC30, HSD, UDB




Teradyne FLEX BOARD

LAYERS : 12


MATERIAL : FR4

Octal Site

Tester ResourcesDC75, DC30, VHFAC, BBAC,

HSD, UDB




Teradyne MICROFLEX Board

LAYERS : 14


MATERIAL : FR4

Octal Site





Teradyne MICROFLEX Board

LAYERS : 14


MATERIAL : FR4

Quad Sites

DC30, DC75, HSD, UDB, BBAC, VHFAC


Ground Shielding for BBAC and VHFAC



Teradyne ULTRA FLEX BoardLAYERS : 18


MATERIAL :

Rogers 4350 & 370HR

4 Sites

SB6G Routing on Top and Bottom

Back drilling used to drill away Stubs.

Ground Shielding


Differential Pairs and Equal Length



Teradyne Catalyst Board

LAYERS : 12

BOARD THICKNESS : 187 mils

MATERIAL :

FR4

Single site

RF routing – coplanar

Matching components



NEXTEST – MAGNUM EV

LAYERS : 10


Digital Routing

50ohm impedance

Equal Length



Sample S93K Full Size DesignLAYERS : 44BOARD THICKNESS : 0.283”MATERIAL : ROGERS (High Speed Signals)NELCO4000-13 (Low Speed

Signals)Ground shield on High Speed

signals to minimize cross talk.Varied the Clearance in Gnd plane

where high speed signals connected.

Ground Isolation on all Power planes to avoid cross talk.

Stubs are Backdrilled for High Speed Signals

More no. of SMP’s are used for High Speed Testing

Differential PairsEqual Length



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Sample S93K Full Size Design

LAYERS : 44BOARD THICKNESS : 310”MATERIAL : ROGERS (High Speed Signals)GETEK (Low Speed Signals)Ground shield on High Speed

signals to minimize cross talk.Varied the Clearance in Gnd plane

where high speed signals connected.


Differential PairsEqual LengthDUT vias are Via-on-Pad pattern

and conductive filled



Sample 3/4 SIZE S93K3/4 Size S93K Template

LAYERS : 24


MATERIAL : Nelco 4000-13

Differential Pairs

Equal Length



Sample 1/2 SIZE S93K1/2 Size S93K Template

LAYERS : 26


MATERIAL : FR4

Differential Pairs

Equal Length



Sample Credence Quartet

LAYERS : 24


MATERIAL : FR408

2 Sites

Ground Shielding for High Speed Signal and Clock

traces

Equal length routing

Backrilling used

Differential Pairs



Sample Credence DesignLAYERS : 48


MATERIAL :

ROGERS (High Speed Signals)GETEK (Low Speed Signals)

High Speed Signals are backdrilled

Differential Pairs

Equal Length

DUT vias are Via-on-Pad pattern and conductive filled




CMT Sample DesignLAYERS : 34BOARD THICKNESS : 270”MATERIAL : ROGERS (High Speed Signals)GETEK (Low Speed Signals)

High Speed Signals routed to 6.5GDM connectors.

Low Speed signals routed to DM250 Connectors.

Ground shield on High Speed signals to minimize cross talk.

Varied the Clearance in Gnd plane where high speed signals connected.


Differential Pairs and Equal LengthDUT vias are Via-on-Pad pattern

and conductive filled

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CMT Sample DesignLAYERS : 34

BOARD THICKNESS : 270”MATERIAL : Nelco 4000-13

High Speed Signals routed to 6.5GDM connectors.

Low Speed signals routed to DM250 Connectors.

Blind Vias and backdrilling used for High Speed Signals

Ground shield on High Speed signals to minimize cross talk.



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Wafer Probe Boards



ETS-364 Probe CardLAYERS : 12

BOARD THICKNESS : 0.187”MATERIAL : FR4

Analog and Digital separation

Via Tenting

Cantilever Probe


ETS-364 Probe CardLAYERS : 10


MATERIAL : FR4


Via Tenting

Cantilever Probe


ETS-364 Vertical Probe CardLAYERS : 8


MATERIAL : FR4


Via Tenting

Cantilever Probe


Wafer Probe Board



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Teradyne Catalyst – Probe Card Impedance Control Device Checker



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Teradyne Flex – Probe Card Multiple Sites Impedance Control Device Checker



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Teradyne Flex Wafer Probe Multiple Sites Impedance Control POOL BOX Guard



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UltraFlex Probe Card Multiple Sites Impedance Control High Speed Routing



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Teradyne Flex Wafer Probe Daughter Board with

Probe Ring Analog Routing



Teradyne Flex Wafer Probe

LAYERS : 14


MATERIAL : FR4



BBAC routing with Ground Shielding




Evaluation/Reference Boards



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Evaluation Board SFP Optical Transceiver Module Gigabit Ethernet Hyper Transport Edge Connectors SATA Interface On-Board DDR2 Memory High Speed USB Interface Manual Routing and length

matching

Sample Evaluation Board




LAYERS : 12


MATERIAL : FR4

Gigabit Ethernet

Ground Shielding for High Speed Signal and Clock traces

DDR2 DIMM

SERDES




LAYERS : 12


MATERIAL : FR4

High Speed routing

PCIe 4 lane

DDR2 Interface

QDR Memory

SODIMM Interface



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LAYERS : 14

Thickness: 0.125”

MATERIAL : FR-4

Differential Pairs

High Speed/Equal Length

DFT: Boundary SCAN




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Demonstration platform Voice over WLAN SoC RF Baseband transceiver 2.4GHz Band Radio 802.11g Wireless Standard Balun and Band Pass Filter USB, RS-232, SDIO Interface Keypad and LCD Connectors Audio Codec with Mic/Speaker Interface USB/Ethernet for PC Interface 8 Layers, FR4 Material

Sample System Board


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Optical Transceiver Connector

Analog and Digital Portion

Ethernet Interface Mini PCi Interface USB 2.0 Interface 1 GSPS ADC

Sample System Board


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Evaluation Board Gigabit Ethernet PHY SERDES Differential

Pairs SDRAM Interface

Sample System Board


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Sample Evaluation Boards



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Analog and Digital Components Proper separation of digital and

analog components during placement

Local digital current loops reducing noise in analog side

SERDES Interface

Sample Mixed Signal Board



Sample RF Design


Dual Radio:

•WLAN (802.11an 5GHz)

• WLAN (802.11bgn 2.4 GHz)

•MAC SoCs with Mini PCI (2GHz) and PCI Express (5GHz) Interfaces

Layers: 6

Material: FR408RF SoC

BP filter

LNA

SPDT Switch

Diplexer

AntennaConnector


Sample RF Design



Sample RF Design



Characterization Boards



Characterization BoardLAYERS : 28


MATERIAL : Nelco4000-13

5GHz High-speed RF traces


Ground Shielding for theHigh-speed Traces

Traces were routed in arc pattern

10 Sets of Backdrilling used to reduce stub.




Characterization Board


Pactron Manufacturing and Test Capability



Manufacturing Procurement

• Long lead parts are ordered during design.

• Component Engineering for

• long lead and high minimum order quantity parts

• Obsolete parts

• Assembly requirements

• Tooling requirements

• Sockets, stiffener and fixtures

• Cables

• Procure and manage inventory through ERP system

• Maintain minimum stock level for long lead parts

• Publish real time inventory report to customer

• Frequent cycle count

• ftp site to publish inventory



Manufacturing PCB

• Complex boards built

• 52 layer board

• 330 mils thick

• 8 site .4mm pitch BGA board

• High aspect ratio 30:1

• HDI boards .3 mm pitch with stacked/staggered micro via and copper fill

• 5% impedance tolerance with 100% tdr measurement.

• Hybrid boards with 3mil per inch warpage tolerance

• Material

• Hybrid construction with high speed material

• Nelco 4000-13, Nelco 4000-13SI, Getek, Rogers RO4350, RO4403, RO4003, P95 polyimide, (Taconic)



Manufacturing Assembly

• Pick and Place Methodology for ATE & Reference boards.

• Faster turn around

• Better quality

• Capability to handle fine pitch and leadless components

• Assembly of fine pitch components like .28 mm pitch BGA

• Specialized rework stations for assembling and reworking BGA and fine pitch components

• Solder Paste Height Measurement

• ROHS Compliance

• IPC-610- Inspection Standards

• Flying Probe, Boundary Scan & Functional Test



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BGA/Emerging Technology Assembly

ONYX AIR-VACAssembly / Rework Station 0201, Flip Chip, MicroBGA/CSP, BGA Assembly

Lead Free Assembly

Position accuracy of up to 10 microns

2000W Top Heater/ 6000W Bottom Heater

Interactive Thermal Profiling “On the Fly” adjustments

Next Generation Process Control System

Non-Contact Site Cleaning



BGA/QFN 3D X-Ray

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Maximum Inspection Area – 24” X 24”

Oblique views at highest magnification (2800X)

Tilt 60 degree, rotate 360 degree for inspection at different angles

In the production of BGAs and flip-chips, non-destructive testing and inspection capability of X-ray has become an important factor in quality control and process analysis

Inspection of BGA and fine pitch area array devices(uBGAs and flip-chips), multi-layer boards , high density interconnects and encapsulated components



Examples – BGA X-Ray

BGA Open BGA Voids

BGA Overview BGA Overview



Solder Paste Printer

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Automated Process Uniform Paste Deposition Fiducial alignment recognition

through lighting Post Optical Inspection for

missed Paste printing Board Size : 24” x 20” to 2” x 2” Board Thickness: 0.008” to

0.138” or 0.032” to 0.196”



Automatic Optical Inspection

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Fast Program Setup Full Defect Coverage Low False call rate High Resolution Imaging Capability: 0201 and 01005 Board Size: 22” X 20” (560mm

X 510mm) Yield Management Tools - SPC



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Board Level Testing Planarity Testing

Fixture established 3 point plane of reference parallel to the top surface of the Granite table

Measurements are taken around perimeter of top surface of the board.

Measurement locations are supplied by customer.

Measurements are then compared to those of customer specs at said test point.

Automatically determines whether board is in spec.

Current setup is only on unpopulated boards. Working on enhancements to test methodology such as

populated boards and automated measurements.



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Board Level Testing Boundary Scan Testing

Asset Interconnect Boundary Scan Tool

Uses the TAP Port & Scan Chain for verification

Check High Pin count BGA connectivity to PCB

BSDL Validation

Flying Probe SEICA Pilot Flying Probe Equipment

Utilizes moving probes & accessible test Points

Checks for all assembly issues (opens, shorts, wrong value, missing components, device orientation..)

Effectively verifies mounting of BGAs, ICs,passives, sockets and connectors.



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Board Level Testing Leakage Test

Current measurement in pico amp range

Measure leakage between adjacent nets

Measure leakage between power and ground

Automated with Flying Probe



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In Summary ~ Why Pactron?• Ideal model for constantly evolving technology

• Engineering Talent• Investment in high end tools• Scalable capacity (zero queue time)

• Flexible & Agile Fab Strategy• Pactron = Multiple fab vendors

•Strategic global presence• US – Sunnyvale, Dallas• Asia – India, Penang

•One Stop Shop for both ATE Hardware & Reference/Evaluation Boards


A Turn-Key Solutions ProviderHigh End Designs – Manufacturing - Final Test

Pactron Ate Introduction

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