PACKAGING IN MINIMAL FAB - SEMICON Taiwan€¦ · packaging-line which realizes a manufacturing...
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Transcript of PACKAGING IN MINIMAL FAB - SEMICON Taiwan€¦ · packaging-line which realizes a manufacturing...
PACKAGING IN MINIMAL FAB
Michihiro Inoue, Ph.D
National Institute of Advanced Industrial Science and Technology (AIST)
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Outline
Overview of Minimal Fab
Packaging Technology in Minimal Fab
Minimal Fab as an IoT/IoE Platform
Summary
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Overview of Minimal Fab
Packaging Technology in Minimal Fab
Minimal Fab as an IoT/IoE Platform
Summary
Traditional MEGA FAB
200m 2m
10m 0.3m
wafer size: 0.5”
Fab investment 0.5～30B$ Fab investment 0.5～30B$
Fab investment 5～30M$ Fab investment 5～30M$
wafer size: 12”
1/1
00～
1/1
,00
0
1/1
,00
0 Minimal FAB
No clean room
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To solve the issue of huge investment
Half inch wafer:
f 12.5mm
Minimal Shuttle
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Minimal Process Tool, Wafer, Shuttle
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The Feature of Minimal Fab
One by one device production 0.5 inch size wafer
Ultra short cycle time Several minutes per one process → One day device production
No clean room is required New local clean technology
“Mortal valley” in R&D to mass production doesn‘t exist R&D tools and production tools are exactly the same
Ring Oscillator
PMOS
CMOS
Cantilever
MEMS core： cantilever
Hybrid
pMOSFET
CMOSFET
CMOSFET
2012
2013
2015 Ring Oscillator
Ring Oscillator
BGA package
Hybrid
Full Minimal
Full Minimal
Full Minimal
Hybrid
2016
Full Minimal
3D structures
&MEMS
2017
Full Minimal
Micro Needle Array
Full Minimal
Accele-ration sensor
nMOSFET
Hybrid
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Minimal Device Fabrication History
CMOS IC (4bit Shift Resistor)
2018 Full Minimal
◇ Packaged IC
■DFF
■Input Buffer
■Protector for Power supply
■OUtoput Buffer (Tri-state)
Circuit Unit Trs. per unit No. of
Unit Total Tr.
DFFCK 62 4 248
IBUF 6 4 24
TBUF 14 1 14
CORNER 6 4 24
VDDCORE 2 4 8
VSSCORE 2 4 8
VDDOUT 2 4 8
4bit SHIFT
REGISTER - - 334
■4-bit Shift Resistor
Ready for Circuit Integration
(334 Tr. work at 357kHz with 3V)
Courtesy of JAXA
4-bit Shift Resistor (Co-work with JAXA)
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JAXA:
Japan Aerospace eXploration Agency
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Overview of Minimal Fab
Packaging Technology in Minimal Fab
Minimal Fab as an IoT/IoE Platform
Summary
0.5”wafer
Seamless Integrating line
Parallel line
package
Wafer process-line
Mega fab
Minimal fab
Packaging process-line
Wafer process-line Packaging process-line
package
Seamless Integrating Line
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Half-inch size package in which single φ12.5mm
wafer can be just stored
Apply the minimal standard tool
Utilize the minimal local clean system and transport system
Flexible redistribution layer (RDL) and external
terminal
Keys of Minimal Package
PLAD: Particle Lock Air-tight Docking
Process
room
Control room
PLAD3
0.5” wafer vehicle “minimal shuttle”
開発した局所クリーン化生産システム
man
outside
class 1million No clean suit
No clean room
manufacturing tool
PLAD3
PLAD
Docking Port
Wafer transfer robot
PLAD
wafer
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Minimal Local Clean System
The packaging-line employs the same tool and clean/transport system
as the wafer process-line
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Die bonding
Molding
Via opening
Cu electro-plating
Cu redistribution-layer patterning
Solder-resist coating & patterning
Solder-ball mounting and reflow
Substrate
φ13.5mm
Si wafer
φ12.5mm
Solder-ball
Al pad
Mold compound
Solder-resist Cu RDL
BGA(Ball Grid Array) Package Process Flow
For Packaging For wafer process
Si wafer
stage
dome
Thickness
0.2±0.02 mm
f13.5 mm f 12.5 mm
Process
chamber
Control
unit
PLAD
Minimal shuttle
PLAD: Particle Lock Air-tight
Docking
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Minimal Packaging Components
Cu Electroplating (5μm)
Coating Thick Photoresist
(9μm)
Maskless Exposure
DOF 23.9μm
Developing
Cu Wet Etching
Resist Removing
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Fabrication of Cu RDL
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Issues of Interconnection
●Residue
●Redeposited
silica fillers
Disconnection,
High resistance
0.001 0.01 0.1 1 10 1000
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10
15
20
25
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Num
ber
of
via
-hole
s
Contact resistance []
44 vias
Rc = 10.2 W
s = 7.17 W
s / Rc = 70.3 %
Al-Si pad
85 vias
Rc = 16.1 mW
s = 4.80 mW
s / Rc =29.8 %
Cu/Ti pad
Cu 1μm
Ti 50nm
Al-Si 1μm
Via Contact Resistance Rc
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Fabrication of BGA Packaging Structure
Die-bonding Compression
Molding
Laser-Via Cu Electro-
plating
Cu RDL
Patterning
Solder-Resist Patterning
Solder Ball Mounting
Solder resist
42 Alloy
Substrate
Mold
Compound
Solder ball
13.5 mm
Total 16 process
13 Minimal tools used
Shuttle
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Inkjet
Printer
Maskless
Exposure
Laser
Ablation
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BGA Packaging Line
Die-bonder
Reflow
Ball
Mounter
Cu Wet-
Etcher
Cu
Electro-
plating
Compression
Mold
Cu Sputter
Coater Developer
Each tool executes one process.
Then, a wafer is transferred by a Minimal Shuttle between
wafer process and packaging processes.
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Overview of Minimal Fab
Packaging Technology in Minimal Fab
Minimal Fab as an IoT/IoE Platform
Summary
MPU chip Memory chip
RDL: Redistribution Layer
MPU MEM-
ORY
Wafer process tech.
System Integration by Packaging
SiP
(System in Package)
MPU MEM-
ORY
FOWLP
(Fan-Out Wafer Level Package)
● Huge investment
● High volume production
● Only top makers can effort
MPU chip Memory chip
Low speed High speed PCB like tech.
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Half-Inch IoT Platform
Sen-
sor ADC
Power Supply
Management
☑ Flexibl for customization
☑ Small number of external pins
< 100 pins
Lower Aspect Ratio
AMP
Half-Inch Size
Mem-
ory
(SRAM)
MPU
SoC
RF
Via + RDL
☑ Small number of
Via connections
Total 60 vias
5 11 13
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5
11
Via count
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Since the number of via
connections in this platform
is small, via can be formed
with a lower aspect ratio.
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Minimal Fab as an IoT Platform
0.5” wafer
…
Packaging Line
Various Devices
Smart watch
Automobile
…
BGA type Ball G rid Array
…
Customized
IoT Chip
SoC System
on Chip
SiP System
in Package
Wafer Process Line Wafer Process Line
CPU Amplifier Memory Sensors
2D
tools DBG
TSV, µBump, Bonding tools
Multi - chip pickup & bonding tool
Smartphone
3 D
…
…
CMOS （FEOL Transistor）
BEOL (Wiring＋Functional
Material & Device )
TSV-3D
Package Semiconductor industry to a new growing times
Wafer process
Ultra short cycle time High reliability production
Seamless integrating line can be built up from wafer process to 3D assembly and packaging
Assembly
Successive creation of new solution for semiconductor devices
Deployment to TSV-3D
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Minimal Fab Paves Way for Low-Profile Package Foundry Services
PKG substrate
Solder
bumps
Wire Bonding
Flip Chip Bonding
RDL(Redistribution Layer) Chip
Wire
Solder balls
Mold resin
RDL
Fan-Out WLP
Fan-In WLP
• Providing design flexibility and minimal development cycles with mask-less process
• Half delivery time of other companies
Package Foundry Service using Minimal Fab by PMT
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Summary
The minimal fab concept using a half inch wafer was proposed in
order to achieve a small semiconductor factory which is free from
huge investment and is suitable to high-mix and low-volume
production.
As a part of the minimal fab, we have developed a brand new
packaging-line which realizes a manufacturing system seamlessly
integrating a wafer process-line with a packaging-line.
We have developed process and equipment of a BGA-type package
to build up the first minimal packaging-line.
Multi-chips packaging and TSV-3D lines for SiP/FOWLP are under
development to make the future minimal fab more powerful.
Thank you for your attention
