Overview Sistem Komputer

7/24/2019 Overview Sistem Komputer

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Chapter 1

Computer System Overview

Dave BremerOtago Polytechnic, N.Z.

!!", Prentice #all

Operating Systems:

Internals and Design Principles, 6/E

$illiam Stallings


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%oa&map

' Basic (lements

' Processor %egisters

' )nstruction (*ecution

' )nterrupts

' +he emory #ierarchy

' Cache emory

' )-O Communication +echniues


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Operating System

/ (*ploits the har&ware resources o0 one or

more processors

/ Provi&es a set o0 services to system users

/ anages secon&ary memory an& )-O

&evices


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Computer2s

Basic (lements/ Processor

/ ain emory

/ )-O o&ules/ System Bus


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Processor

/ Controls operation, per0orms &ata

processing

/ +wo internal registers

' emory a&&ress resister 3%4

' emory 5u00er register 3B%4

/ )-O a&&ress register

/ )-O 5u00er register


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ain emory

/ 6olatile

' Data is typically lost when power is remove&

/ %e0erre& to as real memory or primary

memory

/ Consists o0 a set o0 locations &e0ine& 5y

seuentially num5ers a&&resses

' Containing either &ata or instructions


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)-O o&ules

/ oves &ata 5etween the computer an&

the e*ternal environment such as7

' Storage 3e.g. har& &rive4

' Communications euipment

' +erminals

/ Speci0ie& 5y an )-O &&ress %egister

' 3)-O%4


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System Bus

/ Communication among processors, main

memory, an& )-O mo&ules


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+op89evel 6iew


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%oa&map

' Basic (lements



' )nterrupts


' Cache emory



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Processor %egisters

/ :aster an& smaller than main memory

/ ;ser8visi5le registers

' (na5le programmer to minimi


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;ser86isi5le %egisters

/ ay 5e re0erence& 5y machine language

'vaila5le to all programs ' application

programs an& system programs

/ +ypes o0 registers typically availa5le are7

' &ata,

' a&&ress,

' con&ition co&e registers.


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Data an&

&&ress %egisters/ Data

' O0ten general purpose

' But some restrictions may apply

/ &&ress

' )n&e* %egister

' Segment pointer

' Stac= pointer


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Control an&

Status %egisters/ Program counter 3PC4

' Contains the a&&ress o0 an instruction to 5e

0etche&

/ )nstruction register 3)%4

' Contains the instruction most recently 0etche&

/ Program status wor& 3PS$4

' Contains status in0ormation


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Con&ition co&es

/ ;sually part o0 the control register

'lso calle& flags

/ Bits set 5y processor har&ware as a result

o0 operations

' %ea& only, inten&e& 0or 0ee&5ac= regar&ing

the results o0 instruction e*ecution.


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%oa&map

' Basic (lements



' )nterrupts


' Cache emory



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)nstruction (*ecution

/ program consists o0 a set o0 instructions

store& in memory

/ +wo steps

' Processor rea&s 30etches4 instructions 0rom

memory

' Processor e*ecutes each instruction


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Basic )nstruction Cycle


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)nstruction :etch

an& (*ecute/ +he processor 0etches the instruction 0rom

memory

/ Program counter 3PC4 hol&s a&&ress o0

the instruction to 5e 0etche& ne*t

' PC is incremente& a0ter each 0etch


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)nstruction %egister

/ :etche& instruction loa&e& into instruction

register

/ Categories

' Processor8memory,

' processor8)-O,

' Data processing,

' Control


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Characteristics o0 a

#ypothetical achine


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(*ample o0

Program (*ecution


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%oa&map

' Basic (lements



' )nterrupts


' Cache emory



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)nterrupts

/ )nterrupt the normal seuencing o0 the

processor

/ Provi&e& to improve processor utili


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Common Classes

o0 )nterrupts


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:low o0 Control

without )nterrupts


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)nterrupts an& the

)nstruction Cycle


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+rans0er o0 Control

via )nterrupts


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)nstruction Cycle

with )nterrupts


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Short )-O $ait


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9ong )-O wait


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Simple

)nterrupt Processing


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Changes in emory an&

%egisters 0or an )nterrupt


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ultiple )nterrupts

/ Suppose an interrupt occurs while another

interrupt is 5eing processe&.

' (.g. printing &ata 5eing receive& via

communications line.

/ +wo approaches7

' Disa5le interrupts &uring interrupt processing

' ;se a priority scheme.


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Seuential



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Neste&



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(*ample o0

Neste& )nterrupts


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ultiprogramming

/ Processor has more than one program to

e*ecute

/ +he seuence the programs are e*ecute&

&epen& on their relative priority an&

whether they are waiting 0or )-O

/ 0ter an interrupt han&ler completes,

control may not return to the program thatwas e*ecuting at the time o0 the interrupt


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%oa&map

' Basic (lements



' )nterrupts


' Cache emory



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emory #ierarchy

/ a>or constraints in memory

'mount

' Spee&

' (*pense

/ :aster access time, greater cost per 5it

/ ?reater capacity, smaller cost per 5it

/ ?reater capacity, slower access spee&


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+he emory #ierarchy

/ ?oing &own the

hierarchy

' Decreasing cost per 5it

' )ncreasing capacity

' )ncreasing access time

' Decreasing 0reuency o0

access to the memory5y the processor


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Secon&ary emory

/ u*iliary memory

/ (*ternal

/ Nonvolatile

/ ;se& to store program an& &ata 0iles


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%oa&map

' Basic (lements



' )nterrupts


' Cache emory



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Cache emory

/ )nvisi5le to the OS

' )nteracts with other memory management

har&ware

/ Processor must access memory at leastonce per instruction cycle

' Processor spee& 0aster than memory access

spee&/ (*ploit the principle o0 locality with a small

0ast memory


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Principal o0 9ocality

/ ore &etails later 5ut in short @

/ Data which is reuire& soon is o0ten close

to the current &ata

' )0 &ata is re0erence&, then it2s neigh5our might

5e nee&e& soon.


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Cache an& ain emory


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Cache Principles

/ Contains copy o0 a portion o0 main

memory

/ Processor 0irst chec=s cache

' )0 not 0oun&, 5loc= o0 memory rea& into cache

/ Because o0 locality o0 re0erence, li=ely

0uture memory re0erences are in that 5loc=

C h - i


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Cache-ain8emory

Structure


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Cache %ea& Operation


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Cache Design )ssues

/ ain categories are7

' Cache si


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Si


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apping 0unction

/ Determines which cache location the

5loc= will occupy

/ +wo constraints7

' $hen one 5loc= rea& in, another may nee&

replace&

' Comple*ity o0 mapping 0unction increases

circuitry costs 0or searching.


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%eplacement lgorithm

/ Chooses which 5loc= to replace when a

new 5loc= is to 5e loa&e& into the cache.

/ )&eally replacing a 5loc= that isn2t li=ely to

5e nee&e& again' )mpossi5le to guarantee

/ (00ective strategy is to replace a 5loc= that

has 5een use& less than others' 9east %ecently ;se& 39%;4


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$rite policy

/ Dictates when the memory write operation

ta=es place

/ Can occur every time the 5loc= is up&ate&

/ Can occur when the 5loc= is replace&

' inimi


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%oa&map

' Basic (lements



' )nterrupts' +he emory #ierarchy

' Cache emory



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)-O +echniues

/ $hen the processor encounters an

instruction relating to )-O,

' it e*ecutes that instruction 5y issuing a

comman& to the appropriate )-O mo&ule.

/ +hree techniues are possi5le 0or )-O

operations7

' Programme& )-O' )nterrupt8&riven )-O

' Direct memory access 3D4


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Programme& )-O

/ +he )-O mo&ule per0orms the reueste&

action

' then sets the appropriate 5its in the )-O status

register' 5ut ta=es no 0urther action to alert the

processor.

/ s there are no interrupts, the processormust &etermine when the instruction is

complete

Programme& )-O


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Programme& )-O

)nstruction Set/ Control

' ;se& to activate an& instruct &evice

/ Status

' +ests status con&itions

/ +rans0er

' %ea&-write 5etween process register an& &evice

Programme&


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Programme&

)-O (*ample/ Data rea& in a wor& at a

time

' Processor remains in status8

chec=ing loo= while rea&ing


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)nterrupt8Driven )-O

/ Processor issues an )-O comman& to a

mo&ule

' an& then goes on to &o some other use0ul

wor=.

/ +he )-O mo&ule will then interrupt the

processor to reuest service when it is

rea&y to e*change &ata with theprocessor.

)nterrupt


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)nterrupt8

Driven )-O/ (liminates nee&less

waiting

' But everything passes

through processor.


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Direct emory ccess

/ Per0orme& 5y a separate mo&ule on the

system

/ $hen nee&ing to rea&-write processor

issues a comman& to D mo&ule with7' $hether a rea& or write is reueste&

' +he a&&ress o0 the )-O &evice involve&

' +he starting location in memory to rea&-write' +he num5er o0 wor&s to 5e rea&-written


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Direct emory ccess

/ )-O operation &elegate& to

D mo&ule

/ Processor only involve&

when 5eginning an&en&ing trans0er.

/ uch more e00icient.

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