Overview of SLB ASIC

March 15th 2005 PRR of the TGC SLB and SSW (Reported by CF) 1

Overview of SLB ASIC

IntroductionSLB Internal StructureEvaluation for Radiation ToleranceInspection procedure in the productionPlan for Mass-Production


Introduction

SLB (Slave Board) ASICROHM (Kyoto, J) 0.35um CMOS processed in 9.86x9.86mm2 dieTotal 800Kgates (200K for random logic)Four Blocks can be identified in the mask pattern photo

Macro-core place and routing

Input

JTAG

Readout

Trigger


Internal Structure

Four BlocksTriggerReadoutJTAGInput

clk,BCR,ECR and

20bit(+20bit)

x4


Trigger Block: Low pT Trigger6 < pT < 20GeV/C, 3 trigger Schemes

3 out of 4

2 out of 3

1 out of 2~EI/FI

W & S S & EI/FIW


Readout Block

L1Buffer: 212 input bits x 128 step shift register array

Derandomizer 212+4+2 input bits x 128 depth FIFO block

Hit data of three bunch crossings around L1A (Previous, Current and Next) are sent to ROD via SSW


Input and JTAG Block

Double Mask (160bit x2) StructureFour types of Mask = through, 0, 1 and Test Pulse Pattern

All the internal registers are accessible with JTAGAll the internal registers with R/W prepare so called voting logic structure


Evaluation for Radiation Tolerance

Measurements of Radiation Characteristics of ROHM 0.35um CMOS (presented in LECC2004)

Radiation Environment of SLBTID test results with soft rays from Cobalt-60SEE test results with proton 70 MeV


Radiation Environment

Ionizing Dose: Gy/year2-3Gy/10year => 140-210Gy/10year

(with Safety Factor:70)

Total Hadron (>20MeV) :/cm2/year

1.4-2.8x1010 hadrons/cm2/10year


TID test results of ROHM 0.35um CMOS

PP ASIC (Leakage current vs. Dose)

TID test of Patch Panel ASIC (ROHM CMOS 0.35um)

Four Chips irradiated with form Cobalt-60 (3 chips till 300Gy, 1 till 900Gy)Maximum dose for SLB estimated is 200Gy.No significant current increase has been observed till 300Gy for all the chips.


TID test results CMOS ROHM 0.35umPP ASIC and Ring-Oscillator ASIC

PP ASIC VCON(V) of PLL circuit for variable delay

Special Made Ring Oscillator


SEE Test results (with Proton 70MeV)

Instead of SLB, we have evaluated SEE of ROHM 0.35um CMOS with 4 bit 256 stage shift registers.Total 185 soft SEE for four chips tested, no hard SEE observed with proton fluence of 6.3x1012 (protons/cm2)SEE = 2.8x10-14 (cm-2/bit) estimatedSEU rate = SEE x Nbits x SRLSEEx SFsim

SRLSEE = 2.11x102 (protons/cm2/s) : Radiation Level (hadrons) at SLBSFsim = 5 : Safety Factor (predefined)

Assume Nbits/SLB~3000, Number of SLB chips/System~3000,then SEU rate (day) in whole system ~ 25

Note: this is estimated w/o voting logic


Inspection of products in the Production Process

More than 3000 SLB ASIC chips will be produced.We anticipate a few % of products will have flaws either in a silicon or in a package.6.4% (1640 out of 25809) failure rate was observed in the PP ASIC routine test last year. Reject them before install chips on PS-board.An effective system and procedure must be established for the chip inspection.


Inspection Board & Sequence

Trigger TestSet registers of SLB via JTAG3Set SLB Input pattern via JTAG1or set MASK and Test Pulse TriggerSet DATA_LATCH_ & read Output via JTAG2Check Data with PC

Readout TestSet registers of SLB via JTAG3Set SLB Input pattern via JTAG1or set MASK and Test Pulse TriggerInput L1A signal from CPLDReadout data synchronised with RCLK from SLB to CPLDCheck Data with PC


Inspection Procedure

Inspection must be done by routine-operators for all chips delivered.The Test procedure planned is as follows:

Standard power-on test (current measurement)Check of SLB register access (R/W)Trigger output check with five different types (WD, WT, SD, ST and EI/FI)

With Different delay valuesWith Different coincidence conditionsUsing SLB input or mask set with test pulse trigger

Readout data during the test by inputting L1A in appropriate timing, and check of data consistency.

The test frequency will be suitably determined but lower than 40MHz.


Plan for mass-production

We have now one working version of SLB (version so called 4ECO2).

In the end of March 2005 (next week), version 6 will be delivered. We then check this one, and determine which will be used for the production if version 6 works fine. If every part of version 6 works fine, this must be selected for the production.We will make this decision in the middle of April.

We will order ROHM for production immediately. The production takes 1.5-2 months. We will get products early in June at latest.

The inspection will take a month subsequently. We complete SLB production in the beginning of August.

Overall costs for production including inspection takes \15M ~ SFr150K

Overview of SLB ASIC

Documents

Transcript of Overview of SLB ASIC