Overview
description
Transcript of Overview
![Page 1: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/1.jpg)
© 2013 IBM Corporation
POWER™ SynthesisThe transition from custom circuit design to large block synthesis in a high performance environment
Jeff Brownscheidle, Maureen Delaney, Eric Fluhr, Pat McIlmoyle, Tien Tran – IBM Systems & Technology Group
![Page 2: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/2.jpg)
2
Overview
VLSI Design: A Brief History of Recent Processor Design at IBM
Methodology Evolution: From Custom-driven to Synthesis-driven
A New Design Style: Large Block Synthesis (LBS)
Converting Custom Designs into LBS Designs
Advantages and Techniques of LBS
![Page 3: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/3.jpg)
3
A POWER™ Retrospective
0
500
1000
1500
2000
2500
Ch
ip T
ran
sis
tor
Co
un
t (m
illi
on
s)
![Page 4: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/4.jpg)
4
Mechanisms of Microprocessor Complexity
POWER4 POWER7
180nm technology; 412mm2 45nm technology; 567mm2
Dual Core 8-Core
Single Threaded 4-way Simultaneous Multi-Threading per core
8 Execution Units 12 Execution Units
2 Single-Precision Floating Point Units 4 Double-Precision Floating Point Units
Decimal Floating Point Unit
Vector Unit supporting VMX/AltiVec
Shared L2 cache; Off-Chip L3 cache Dedicated L2 cache per core; On-Chip L3 cache (eDRAM)
![Page 5: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/5.jpg)
5
The Conventional Approach: Less Synthesis, More Custom
ISU Generation 1 ISU Generation 2
Custom
Synthesized
![Page 6: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/6.jpg)
6
Trending Towards Synthesized Designs
64% 65%
37% 39%
24%19%
Gen 1 Gen 2 Gen 3
% of Designs % of Unit Area
ISU Generation 3Synthesized Logic
Percent of Unit
![Page 7: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/7.jpg)
7
Design Type Spectrum
5) Custom Design
1) VHDL structuring &parm customization
2) Latch, Local Clock Buffer Preplacement
3) Embedded, Un-RoutedCustom Components
4) Embedded, Fully Routed Custom Components
0) Random Logic Module (“Flat” Synthesis)
Design Effort
De
sig
n C
usto
miz
atio
n
New D
esig
n Te
chni
ques
![Page 8: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/8.jpg)
8
A New Design Type—Large Block Synthesis (LBS)
Sample Configurations Design Example
SynthesizedRandom
Logic
![Page 9: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/9.jpg)
9
The Power of LBS
“Structured” Flat Design
Flexibility & Incremental Customization
Scalability
Fast path to initial timing
Reduction in layout time
![Page 10: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/10.jpg)
10
Design Merging
Individual Designs Merged LBS
![Page 11: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/11.jpg)
11
Migrating a Design to LBS
Custom LBS
![Page 12: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/12.jpg)
12
VHDL Structuring
LatchesLatchesLatches Latches
![Page 13: Overview](https://reader033.fdocuments.in/reader033/viewer/2022052702/56814674550346895db39825/html5/thumbnails/13.jpg)
13
Summary
Large Block Synthesis: A modern, versatile alternative to custom high-performance design
Potential power and area savings over full custom design
Ability to iteratively increase custom designer input to converge toward a circuit solution
Long-term outlook: Can LBS radically influence future time-to-market expectations?