Overmolded Plastic Pad Array Carriers (OMPAC): A Low Cost, High Interconnect Density IC Packaging Solution

for Consumer and Industrial Electronics

eu Bruce Freyman and Robert Pennisi

Advanced Manufacturing Technology Group Motorola

Communications Sector Ft. Lauderdale, Florida

I n t r o d u c t i o n A new surface mount leadless semiconductor packaging technology, OMPAC - overmolded plastic pad array carrier (Figures 1 and 2) , has been developed to meet the requirements of next generation portable electronic products. Benefits of OMPAC's compared to conventional surface mount leaded plastic packages such as plastic leaded chip carriers (PLCC) and quad flat packs (QFP) include: smaller size, higher package interconnect density*, higher test and solder assembly yields due to the use of pre-applied solder bumps (Figure 3) and greater technology extendibility in the areas of high speed integrated circuits, multichip modules and fine pitch soldering. Component level qualification of OMPAC was successfully completed using industry standard environmental tests. C-mode Scanning Acoustical Microscopy (C-SAM) was extensively used to optimize package design and processing.

B a c k g r o u n d Current trends in portable industrial and consumer electronic products toward smaller size, lower cost and increased functionality have resulted in greater emphasis on the development of semiconductor packaging technologies which can accommodate larger, more complex integrated circuits in smaller, thinner packages. The need for greater product functionality has led t o an increased number of integrated circuits per product as well as an increase in the average gate count and resultant number of I/O's per integrated circuit. Although advances in wafer fabrication technology continue to shrink device geometries below 1.0 micron the increase in device complexity has more than offset these advances and led to larger chip sizes. For example, next generation two-way radio and cellular telephone technology will use integrated circuits measuring 12 millimeters or greater per side with 1/0 counts of 250 or greater. As the size and number of chips in portable electronic products continue to grow, the task of reducing overall product size becomes more problematic. The product area and th i ckness required t o accommoda te g rowing numbers of integrated circuit packages has become the driving factor in many new product designs.

Most o f the semiconductor packaging industry has responded to the requirement for higher lead count, lower profile, smaller packages by continuing to evolve the leaded plastic package. This evolution has seen leaded plastic package technology move from the 100 mil pitch dual in-line package (DIP) to the 50 mil pitch plastic leaded chiD carrier (PLCC) to the

* Package interconnect density is defined as the number of signal, power and ground connections made from the package to the printed circuit board per occupied printed circuit board area.

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40 mil (1.0 mm) pitch quad flat pack (QFP). Quad flat packs have continued to evolve to the current commercially available state of the art 20 mil (0.5 mm) pitch packages. This evolution - from DIP to fine pitch QFP - has resulted in a ninety-three percent reduction in the printed circuit board area consumed by a 64 pin leaded plastic package. Concurrently, the thickness of these packages has evolved from 250 mil thick DIP'S to the recently introduced 40 mil thick thin small outline packages (TSOP) for memory devices. These developments have led to the proliferation of QFP's in consumer and industrial products.

Although widely used, the implementation and continued use of fine pitch QFPs has not been easy for many systems houses. The major problems confronting users of QFP's are 1) poor solder assembly yields due to poor control of lead co- planarity and 2) poor fine pitch solder printing yields as package lead pitch continues to shrink. With each succeeding generation of fine pitch packages the problems relating to control of lead co- planarity and solder paste screen printing are exacerbated. The continuing requirement to shrink package size while maintaining very high electrical test and solder assembly yields and low cost packaging led to the development of OMPAC t e c h n o l o g y .

OMPAC technology is a low cost extension of the ceramic pad array carrier technology used by Motorola and others during the 1980's in order to reduce the s ize and/or increase the electrical performance of their systems (1). T h e major advantages of overmolded plastic pad array carriers compared to leaded surface mount packages include the following. 1) Increased packaging interconnect density. Pad array carriers distribute the I/O in an evenly spaced matrix of solder connections on the bottom side of the package. Figure 4 shows the packaging density advantage of OMPAC's relative to conventional leaded plastic packages. 2) Higher solder assembly yields. Fine pitch solder printing is eliminated due to the application of pre-applied solder bumps to the packages. 3) No lead co- planarity problems. OMPAC's do not have leads. Lead co-planarity related yield loss in leaded package assembly, electrical test and soldering is a problem that continues to plague the industry.

This paper describes materials and processes used for OMPAC assembly, solder assembly advantages, environmental testing procedures and results, and process optimization using C-SAM analysis.

0569-5503/91/0000-0176 $1 .OO "1991 IEEE

OMPAC Design The overall height of the OMPAC is dependent on several factors but ranges from 40 mils (1.0 mm) to 80 mils (2.0 mm) without the solder bumps. Solder bumps add an additional 15 mils ( .38 mm) to the height of a soldered OMPAC. The area consumed by an OMPAC is dependent on the solder pad pitch used (Figure 4). Currently designed OMP'AC's use solder pad pitches between 50 mils (1.27 mm) and 70 mils (1.77 mm). The ability to use a 40 mil (1.0 mm) pitch has been established (1). The high interconnect dens i ty ach ievab le with pad array ca r r i e r technology is apparent by realizing that a 40 mil pi tch array of solder pads i s capable of interconnecting over 600 I/O per square inch. To date, all OMPAC designs have used double-sided printed circuit boards; future plans include the investigation of multilayer boards to accommodate multichip and high speed (low dielectric constant) circuit applications.

All of the OMPAC's currently in production are fabricated with 1/2 oz. copper clad .008" thick BT- epoxy printed circuit board laminate. The printed circuit board top side metallization pattern is shown in Figure 5 . The top side metallization is comprised of a die pad for back side device grounding and the wire bond fingers. The wire bond fingers extend outward to plated thruholes in the printed circuit board located near the edge of the package. The plated thruholes provide electrical continuity from the top side to the bottom side of the package. The signal path is completed on the bottom side of the package by plated copper traces extending from the plated thruhole to the solder bump termination. With the exception of the solder bumps, all metal f ea tu re s on t he pr inted circui t board are photodefined, etched and electroplated with copper, nickel and gold. Photodefined soldermask is used on the bottom side of the package to contain the flow of solder during IR reflow.

Fabrication of the printed circuit board circuitry is done in panel form. After completion of the panel, individual strips are routed from the panel; each strip containing an array of package metallization patterns. This array is the functional equivalent of a plastic leaded package leadframe; all OMPAC assembly processes are completed in strip form using off t he shelf semiconductor packaging e q u i p m e n t .

Conventional epoxy die attach and gold ball bonding technologies are used to interconnect the integrated circuit to the printed circuit board base. After die and wire bonding the printed circuit board strip is molded using conventional epoxy transfer molding technology. A number of different epoxy mold compounds have been found to yield excellent adhesion to the die and printed circuit board surfaces. Figure 6 shows the adhesion strengths of different mold compounds to printed circuit board coupons. Adhesion strength was measured by torque testing a 0.5" x 0.5" molded epoxy block from a 1.0" x 1 .O" BT-epoxy printed circuit board coupon. Torque tested samples that experienced 100% cohesive fai lure of the BT-epoxy substrate and/or the molding compound (Figure 7) were characterized as having excellent adhesion. Samples exhibiting this level of adhesion had no interfacial delamination. Cohesive failure of the printed circuit board surface occurred at approximately 275 in-lbs.

After post-mold curing, the packages are solder bumped, singulated from the strip and electrically tested.

OMPAC Solder Assembly Solder bumped OMPAC's offer significant solder assembly advantages over conventional leaded plastic packages. The primary advantage is that solder bumped OMPAC's can be IR reflowed in a production environment to standard printed circuit boards with extremely low soldering defect levels. Solder assembly defect levels under 20 parts per million solder joints (ppmj) are commonly achieved (without any form of rework) in Motorola factories employing 60 mil (1.5 mm) pitch solder bumped pad array carriers. Solder defect levels for 25 mil (.65 mm) pitch QFP's are typically reported throughout the industry at levels above 200 ppmj (without any form of rework).

The use of solder bump technology diminishes the impact of three contributing factors responsible for yield loss during solder assembly of surface mount packages: opens due to lack of adequate lead or pad co-planarity or skew, shorts between leads or pads due to solder balls, and opens or shorts due to package mis-placement. Lead co-planarity and skew problems are solved with solder bumped OMPAC's by the elimination of leads. Lead or pad shorting is reduced due to the larger solder bump pitch on OMPAC's compared to fine pitch packages. OMPAC placement tolerances are not as critical as the placement tolerances for fine pitch packages due to the i r l a r g e r pad p i t ch and se l f - cen te r ing capabilities during solder reflow. The self-centering of OMPAC's during the solder reflow process is due to solder wetting forces which tend to align the package on the solder pads of the motherboard. This phenomenon increases the allowable positional tolerance for placement of the package on the printed circuit board.

E n v i r o n m e n t a l T e s t i n g The OMPAC was subjected to autoclave (2 ATM; 121C) and thermal shock testing (liquid to liquid: -55 C to 125 C) after preconditioning the package with two cycles of a standard 60/40 Sn/Pb IR reflow profile and a 24 hour simulated electrical bum in at 120C: these thermal environments simulated the actual factory environments that OMPAC's will experience. OMPAC's with Motorola MC68HCll HCMOS die (.261" x .263") were environmentally tested and evaluated for open and shorts as well as for electrical functionality with a Trillium electrical test system. A C-Mode Scanning Acoustical Microscope (C-SAM) was used to monitor the integrity of the mold compound - substrate interface, mold compound - die interface, die - die paddle interface and any internal cracking of the die (Figure 1). The appl icat ion of C-SAM and other acoust ical microscopy techniques to IC plastic package failure analysis are reviewed in the references (2 - 5).

T h e C-SAM i s a pulse echo type acoustical microscope that generates an acoustical image of a package 's internal layers by measuring t h e amplitude and phase of the reflected signal. Cracks, voids or interfacial delaminations not detected by other non destructive techniques such as X ray can easily be identified. The frequencies of the measurement ranged from 10 and 100 MHz. An internal layer of the package can be focused on by gating techniques in which the detector is "on" only when the return signal for the desired layer reaches the detector. This excludes all other signals from the image (Figure 8). The resolution of the image in plastic materials is 2-20 microns in the xy plane and 0.1 micron in the z axis (3).

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Environmental testing was set up such that the C- SAM would be used to monitor the interfaces on i n c o m i n g pa r t s a f t e r e a c h p r e c o n d i t i o n i n g procedure and after electrical testing. Electrical testing was done every 48 hours of autoclave and every 200 cycles of thermal shock (Figure 9).

The acoustical micrographs of the first lot of incoming packages indicated a small amount of delamination at the mold compound - solder resist interface (Figure IO). Data processing of the image estimated the level of delamination to be about 6%. No delamination or cracking was identified at the die - mold compound, die - substrate interfaces nor were any s igns o f d i e c racking observed . Preconditioning of these parts with no bakeout increased the level of delamination of the mold compound-solder resist interface and initiated the delamination of the mold compound from the corners of the die (Figure 11). Autoclave testing continued to increase mold compound- solder resist de lamina t ion until l if ted wire bonds caused electrical opens at 144 hours (Figure 12).

Process modifications were made to improve the adhesion of the mold compound to all surfaces. Although no quantitative peel strength data was obtained, the acoustical micrographs indicated no delamination at any of the mold compound interfaces on 100% of the parts. Subsequent preconditioning (without bakeout) resulted in no delamination (Figure 13) and the autoclave (Figure 14) and temperature shock testing (Figure 15) showed a marked improvement in the package reliability. Open and short failures were detected after 288 hours of autoclave. No failures were observed after 4000 cycles of thermal shock (Figure 16).

S u m m a r y The continuing trend towards the use of higher interconnect density integrated circuit packages and the need for high solder assembly yields has led to the development and introduction of OMPAC. OMPAC technology offers system designers higher package interconnect density and solder assembly

yield than is available with commercially available leaded plastic packages. These advantages coupled with the ability to extend OMPAC technology to low cost printed circuit board-based multichip modules and higher 1/0 single chip packages indicate that this new technology will gain acceptance within the industry. Future plans for OMPAC include IEDEC registration of a family of standard molded body and package outline sizes.

A c k n o w l e d g e m e n t s The authors wish to thank Frank Juskey, Bill Mullen, Kingshuk Banerji, Robert Darveaux, Ken Thompson, Lynn Davis, Lonnie Bernadoni, Alex Shlinkman, Marc Papageorge, Barry Miles, Glenn Gold, Jill Flaugher, Gary Chapman and Robert Mulligan for their assistance in collecting and analyzing the data reported in this paper.

R e f e r e n c e s 1. Dohya Akihiro, et al, "Packaging Technology for the NEC SX-3/SX-X Supercomputer", 1990 Electronic C o m p o n e n t s a n d T e c h n o l o g y C o n f e r e n c e Proceedings, pp 525-533.

2. A d a m , Tom., "Inspect Plastic IC Packages with Ultrasound", Semiconductor International, August 1990, p.88.

3. Lin, R., Blackshear, E. and Serisky, P., "Moisture Induced Package Cracking in Plastic Encapsulated Surface Mount Components During Solder Reflow Process", IEEE/ Intemational Reliability Physics Symposium (IRPS) Proceedings", 1988, p.83.

4. Semmens, J. and Kessler, L.W., "Nondestructive Evaluation of Thermally Shocked Plastic Integrated Circuit Packages Using Acoustical Microscopy", International Symposium for Testing and Failure Analysis (ISTFA) Proceedings, 1988, p.211.

5. Santangelo, L. and Kessler, L.W., "Acoustical Microscopy: A Key Inspection Tool for Improving the Reliability of Surface Mount Capacitors and Plastic IC Packages", Surface Mount Technology, 1989.

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FIGURE 1. CROSS-SECTIONAL VIEW OF OMPAC

178

TOP FIGURE 2. BOTTOM OMPAC

FIGURE 3.

SOLDER BUMPS ON BOTTOM- SIDE OF OMPAC

Package Pin Count vs Package Area

QFP (.OX) / ' I I 3 - 4

FIGURE 4. PACKAGING INTERCONNECT DENSITY COMPARISON

FIGURE 5 . TOP SIDE VIEW OF OMPAC PCB METALLIZATION

179

Board / Mold Compound 450 T

Autoclave ,- Expose to factory

environment

400 hes l ve F a i l u r e

350

- 300 v; n + 250

- 200

g 150

IO0

50

0

c -

3

k

Test ,_ 1

Vendor A Vendor 6 Vendor C Vendor D Vendor E

Char t of Adhesive St renaths o f Mold Compounds

FIGURE 6. ADHESIVE STRENGTH OF MOLD COMPOUND T O PCB

FIGURE 7. FRACTURE INTERFACE OF BT-EPOXY PCB

AND MOLD COMPOUND AFTER TORQUE TESTING

C SAM ACOUSTICAL MICROSCOPY . . . . . . . . . . . . . ., . . . . . . . . . . . . . . . . . . . . . . . . . ... ... . . . . . .. .. . ..... . . . . . .... . . . . .. . . .. . . ....... . . . ..... . . . . .... .

- o +

PEFECT IDENTIFIED POLARITY PEAK SHAPE AMPLITUDE

FIGURE 8. C-SAM GATING OF ACOUSTICAL SIGNAL

180

FIGURE 10.

ACOUSTICAL MICROGRAPH OF MOLD COMFQLJND-

DELAMINATION IS DESIGNATED BY WHITE AREA IN UPPER LEFT CORNER.

SOLDER RESIST INTERFACE OF IN-COMING OMPAC.

FIGURE 11.

ACOUSTICAL MICROGRAPH OF MOLD COMPOUND- SOLDER RESIST INTERFACE AFlER EXPOSURE TO FACTORY SOLDER REFLOW ENVIRONMENT. AN

INCREASE IN THE AMOUNT OF DELAMINATION IS EVIDENT.

FIGURE 12.

ACOUSTICAL MICROGRAPH OF MOLD COMPOUND- SOLDER RESIST INTERFACE AFTER EXPOSURE TO 144

HOURS OF AUTOCLAVE. AN INCREASE IN THE AMOUNT OF DELAMINATION IS EVIDENT.

181

FIGURE 13. F I G U R E 14.

ACOUSTICAL MICROGRAPH OF MOLD COMPOUND SOLD= RESIST INTERFACE AFTER EXPOSURE TO FACTORY SOLDER REFLOW ENVIRONMENT. NO

DELAMINATION DETECTED. PROCESS MODIFICATIONS WERE MADE TO IMPROVE MOLD COMPOUND ADHESION.

ACOUSTICAL MICROGRAPH OF MOLD COMPOUND- SOLDER RESIST INTERFACE A F E R EXPOSURE TO 144

HOURS OF AUTOCLAVE. NO DELAMINATION D E E C E D .

F I G U R E 15

Autoclave

48 hrs 96 hrs

144 hrs 192 hrs 240 hrs 288 hrs 336 hrs 384 hrs

OMPAC failures

0135 0135 0135 0 1 3 5 0135 1 1 3 5 2135 4 / 3 5

0

Thermal Shock 200 cycles 400 cycles 600 cycles 800 cycles

1000 cycles 2000 cycles 3000 cycles 4000 cycles

F I G U R E 16.

OMPAC failures lDarametric)

0135 0135 0135 0135 0135 0135 9 / 3 5

30135

OMPAC failures 0135 0135 0135 0135 0135 0135 0135 0135

ACOUSTICAL MICROGRAPH OF MOLD-COMPOUND- SOLDER RESIST INTERFACE AFTER EXPOSURE TO loo0

THERMAL CHOCK CYCLES. NO DELAMINATION DEmCED.

182